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RAYCOM
Product Catalog
Silicon Solutions
• SDH
• PDH
• Converter
RAYCOM CO.,LTD.
Note: TU-12, TU-3 and AU-4 are switched through Provides a 8.192 MHz Serial Overhead Bus Interface
configuring registers. In order to switch correctly, all (SOI) so that tributary AIS information can be transferred
RC7830 provides two types of modes of 38.88MHz and Low power consumption, CMOS technology, 3.3V
77.76MHz. In the 38.88MHz mode, STM-1 data bus and power supply
bus timing are compatible to PMC5362 or RC7860. PQFP240 package
Features
Non-blocking array of switches for cross-connecting
SDH TU-12, TU-3 or AU-4
Provides non-blocking switching between 1008 TU-12
of sixteen STM-1 input streams and 1008 TU-12 of
sixteen STM-1 output streams within one chip
Enlarges the switching capacity to 3024 TU-12 in a 4x4
SDIA0 4/ 4 SDOO
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SDIA1 *
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SDIB7
SCDI
SCDO
RDATAMPIO(7...0]
7ADDMP(6...0]
i-ic
CSMPI
SJ02KI
RDMPI
BUSFREI WRMPI
RESETI
,SCOMP
SJ02KO IRQO
Applications
SDH Broadband Cross-Connects
SDH ADM/TM Multiplexer
Multi-service Transport Platform(MSTP)
Typical Application
RC7830
P
ADM Telecom-bus Telecom-bus
Multiplexer Mapper
provides telecom-bus which can be connected to external Special N2/0 multi-frame (similar to 16-byte Л ) for E1 port
to port management
mapper or EOS chip for more E1s and Ethernet. The
Assignment between an E1 and any TU-12 tributary, and
RC7880 integrates a Synchronous Equipment Clock
supports interzone service
module (SEC), an Engineer Ordering Wire processor
Hardware-based Protection Switching with a switch
(EOW), an 8.192Mb/s serial overhead bus, and two time less than 50ms
overhead extension E1s. Therefore, a single chip can be Optional HDB3/NRZ code format and built-in CDR
used to implement the main functions of a low-cost SDH HDB3 code violation (CV) detection and latched alarm
(ALS), Remote Power Detect (RPD), built-in PRBS Bit external mapper or EOS chip for more E1s and Ethernet
Supports aligned TU-12/TU-3 structure
Error Rate Tester (BERT), and supports in-band Data
Use C1Л V1 and SPE(sharing pins with the E1 port) to mark
Communication Network (DCN) for management.
VC-4 payload
The RC7880 complies with ITU-T G.707/783/813/704/703
Tributary unit pointer process
recommendations.
Supports Add/Drop Multiplexer(ADM)
TU-12/TU-3 pointer interpretation and APS
Features TU-12/TU-3 line-loop
Synchronous equipment clock
Two work modes
Complies with ITU-T G.783 recommendation
Monolithic multiplexer(SOC)
24E1smapper(E1MAP) Generates 38.88MHz equipment clock(TO) and synchronized
8.192MHz clock for serial overhead bus
STM-1 optical line process
Free-running, locked and holdover working mode
Dual STM-1 lines overhead termination/generation
The timing source can come from 4 optical lines(T1), 2 E1
Built-in CDR and LVDS interface
lines(T2), 2 external timing references(T3) and output 2
AU-4/TU-3/TU-12 pointer interpretation/generation
timing signals(T4), T3 and T4 can be 2MHz or 2Mb/s
MSOH/RSOH/VC-4 overhead termination/generation
Digital Phase-Locked Loop with configurable bandwidth
OOF, LOF, LOM, MS-AIS, AU-LOP/AIS and TU-LOP/AIS
(0.05Hz - 20Hz)
monitoring
External VCO component is necessary to generate
B1, B2, B3, V5, M1, G1 and VC12-REI monitoring
155.52MHz clock for optical transmission
J0(1/16Byte), J1(16Byte) and J2(Byte) overhead bytes
Supports G.704 frame on T3, SSM termination/generation
termination/generation
Overhead interface(OHI)
ALS and RPD functionality
One 8.192Mb/s synchronous serial overhead bus
Optical diagnostic loopbacks
Two overhead extension E1s(G.704 frame) for communication
E1 interface
Generates tone of dial, ring, ringing back, engaged, howling 0.18um CMOS and low power consumption
1 5V for kernel, 3.3V for I/O
Support DTMF
LQFP256 package, without lead, 5V tolerance
Generic serial interface(GSIO)
Block Diagram
Note'Multiplexed pins
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po[22:24]'e1no[22:24]'
Ieipl[22:24]to1ni[22:24]-
retcKian.vplrlkhn*
pdpi/pdni
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mclk38mo
i nip 2 ко
apllsl
Applications
SDH Add/Drop Multiplexer
SDH Terminal Multiplexer
Multi-service Transport Platform (MSTP)
Customer Premises Equipment (CPE)
Typical Applications
F NMS Phone
SDH Add/Drop Multiplexer
Microprocessor
RC7880
West STM-1
(SOC mode) A- East STM-1
Telecom bus
Syn port
H3H
T
21/24«E1
t
n*E1
t
mxETH
SDH E1 Mapper
Add/Drop Telecom bus
RC7880
(E1 map mode)
24xE1
Ethernet into SDH with little delay. It also supports GFP-F, Concatenation
LCAS protocols and provides virtual concatenation of 63 Supports single VC-12 mapping
Supports 1/4 virtual concatenation group of 1 to 63 independent REI, RDI, BIP-2 on the two add buses
V5 byte Signal Label Mismatch(SLM), Unequipped(UNEQ),
VC-12s
BIP-2 errors, Far End Block Errors(REI), Remote Defect
Provides optional Link Capacity Adjustment Scheme
Indication(RDI) detection, BIP-2 generation, and RDI REI
(LCAS) protocol, and will realize bandwidth dynamic automatic generation
adjustment with interval of 2.0176Mb/s SDRAM interface
Auto-adaptive mechanism of the receiving LCAS bit External 4M><16 SDRAM of 64Mbit
and GFP parameters, convenient for the communica- Clock frequency is 507100MHz
tion with equipment of other manufactures Read and write in burst8 mode and the CL is 3
Add/Drop
Telecom -bus A
A N.
Add/Drop
Telecom-bus В
l\
«
/
Application
Typical Applications
щ H Mil
RC6100F H • 10/100Mb/s
•* м
RMII
m •м^я
Ethernet 10/100Mb/s
RC6400F №^•^•4 Switch / 10/100Mb/s
№fliBM 10/100Mb/s
M •4 PHY
10/100Mb/s
Monolithic SDH equipment timing source solution from 0.05Hz to 20Hz, which can be adjusted based on
Complies with the timing accuracy, pull-in, pull-out, the different applications of the network element to
noise generation, noise tolerance, transfer characteristic, solve the confliction for the jitter and wander
short term phase transient response, long term phase Provides microprocessor interfaces for the setup and
Meets ITU-T G.783 standards Integrates two independent STM-1 clock recovery units
Accepts eight fully independent line reference clock (T1) for two links
Accepts two PDH 2Mb/s reference clocks (T2) with E1 Two parallel/serial and serial/parallel data converters
framers supporting SSM function are designed to connect with STM-1 framers
Accepts two 2Mb/s or 2MHz external synchronization signals Supports IEEE 1149.1 JTAG edge scanning function
as reference and supports SSM if 2Mb/s is selected Single 3.3V operation and 5V I/O compatible
Generates two output clocks (T4) with optional 2MHz or
QFP176 package
2Mb/s selection and supports SSM if 2Mb/s is selected
Application
SDH ADM/TM Multiplexer
Typical Application
ADM Multiplexer
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• 65.537MHz
Application
SDH ADM/TM Multiplexer
Typical Application
C064K/V24/E1
10
LTDAO[7:0] 4- UNEQG
LTC19MAI
LTFPAI i
UNITB(SIMUX)
LRDBI[7:0] RXr
LRC19MBI
OLOSBI
ALMBO[0:9] ^~J\
LLOOf
LTDBO[7:0] ADB(3:0]
UNEQG AC1J1BI/BENI
LTC19MBI ASPEBI
LTFPBI тх;_^^^^___^^^^ i AMFP2KBI
DBIO[7:0]
SCLK8MI
SPF8KI
SOT8MI
SOR8MO
Е^^^И ^^Я ADDRI[9:0]
RDNI
WRNI
CSNI
INTNO
г±±
ш ш 5Г о*
16 1Ш
О о
RESETI
о
§ о
5
р
И
§ 1
= й
11
PDH Solution
RC7017 8Е1&100М Ethernet Multiplexer
Application
8 E1
4¥
шм I I
10/100M
LED
12
§
ш
_i
soQvoO2'
HJBLI RESETI
CLK65MI
RD232I[0:3]
BIASEI
BIASEO
E1NI[0:7]
E1PI[0:7] OS ENAO
TSDPAO
MTXD[3:0] TSDNAO
OS_ENBO
MTXEN TSDPBO
MTXC TSDNBO
SCRAWL MODI
CLK9M| FORCEAI
FORCEBI
CRNT_ WORKO
MRXD [3:0
MRXDV OSDAI
MRXC RSDPAI
RSDNAI
RSDPBI
E1 Щ 0 : 7 ] RSDNBI
E1PO[0:7] OSDBI
TD232O[0:3]
HJBLO
>СЛС/>(/> >zi~r-i-m
groro2
C( roOmm^
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ooogSw
ТСЯСДся
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13
• Integrates optical and E1/ Fractional E1 interfaces on line output data delay can be configured by registers on the
• Optical bit rate is 4.096 Mb/s, LVDS, or LVTTL interface bidirectional asynchronous timing
Block Diagram
RPD 16K Channel SA Channel
Alarm Interface Interface(A)
System [ ARSTI
Signal ! CLK65MI
16
tolerable
Applications
• Multi-service Fiber- Modem/Converter
LED
Optical
MP
'-O
Transceiver
Router
RC7235A
E1
PS-BUS
74XX165
'-O PCM
Router
PS-BUS
74XX165
17
interface, and transferred to the other side. ered form the line, more flexible for different applications
- PCM30/31 mode selectable, CRC-4 check function auto
The RC7222 integrates excellent statistic functions that
adaptive
can monitor work status and performance information of :
Detailed status and alarm information for statistic record
Ethernet, HDLC and WAN interfaces; furthermore, it
generating
provides both UART and I2C interfaces, enhancing the : User-activated local and remote loop-back functions .helpful
management capability and accessing convenience. for link diagnosis
: A transparent sync 20Kbps data path provided via spare
bits (SA) in FE1 mode
Features • Optical interface
• Ethernet bridge chip with multiple WAN interface : 4.096Mbps channel for an E1 data path (carrying Ethe
options: framed E1 (FE1 for short), unframed E 1 , rnet and ST_BUS signals) and a transparent
asynchro nous 16Kbps user-defined data path
optical line interface and HDLC interface
: Built-in Clock Data Recovery (CDR) unit
• Multiplexing ST_BUS signals into E1/FE1 or optical
: Direct connection to optical transceivers of TTL
channels voltage level
• Ethernet interface • HDLC interface
; Standard Media Independent Interface (Mil) and MDIO : Maximum bandwidth: 50Mbps
management interface for connection to Ethernet PHY l Frame format compatible with some Ethernet bridge
! 10M/100Mbps, full/half duplex supported,comply with IEEE chips from other vendors
802.3 • SDRAM interface
i 32-address LAN table, with automatic learning and aging ) Built-in SDRAM controller, seamless interface to external
: Forwarding only the frames destined for WAN, otherwise filtering 64Mbit SDRAM
'• Frames with length from 64 to 2024 bytes transparently : Integrated SDRAM tester for board debugging
transferred l Data buffer resizable, from 32 frames to 512 frames
:
Illegal frames such as bad CRC packets, undersized packets
18
: 19.2Kbps UART interface and 100Kbps I2C interface prevent Ethernet frames from looping back in case
avai-lable for access of unexpected E1 loop-back
: 8-bit configurable address, for up to 256 bridge pairs to be Ethernet data can be allocated to any slot of E1
managed frame, and the slot occupation on either side can be
; Local RC7222 and Ethernet PHY can be monitored and coupled accordingly
configured 0.25um CMOS technology
: Status of the remote RC7222 and PHY can be retrieved in Voltages: Core 2.5V; I/O 3.3V
FE1 mode LQFP128 package
! Extra low-speed data path provided for users, extending
management capability
: Chip reset can be activated by the management console as
well as the reset pin
Block Diagram
E1PI/HDLC.RC
/ OPT_SDI
HDLC ТСИ6К Dl
E1_NO(HDLC_DO
/OPT DO
Config Bus
19
E1-*—* 10/100 M
10/100M
UART LED
V.35/DS3/E3 •
, t
•* »•
SET Al
20
Overview Features
RC7210 is composed of the following modules: Ethernet • Broadband Ethernet remote bridge via 1-4 E1 links
MAC Controller, E1Rx Control module, E1Tx Control • 10M/100M, full/half-duplex Mil interface, complying
module, TX Queue Management, Require Management, with IEEE 802.3
TX Queue Interface (SDRAM controller), Rx Queue • Maximum frame length of 1536 bytes, tolerance of
(internal RAM), System Control module, Control and the padded-frame in IEEE 802.1Q
Alarm interface, Clock Generation module and four • 1024-address LAN table, updated automatically
FIFOs integrated for speed compensation. • Ethernet frame FCS check module integrated, with
alarm output
To achieve a broadband Ethernet remote bridge, two
• Quad E1 interfaces, ITU-T G.703, G.704 and G.823
coequal RC7210 systems are to be connected via 1-4
compatible, with signaling slot occupied
point-to-point E1 links. In local system, RC7210 receives
• 2.048MHz clock recovery circuitry and HDB3 Codec
Ethernet MAC data, converts them into E1 frames and
circuitry inside
forwards the E1 serial stream to the other station through
• Auto detection of the availability of E1 links and
E1 links; in far-end system, RC7210 receives E1 frames,
using accordingly
recovers the original Ethernet data and hands them to
• Capability of resetting remote system
the LAN it connects via the Mil interface. Owing to the
• Loop back capability of E1 circuits
privacy of frame procedure and handshaking protocol,
• Built-in SDRAM controller, glue-less interface to
RC7210 must be used in pairs.
external 64Mbit SDRAM
• Selectable buffer size, for different applications
• 3.3 Volt power supply, 5V TTL tolerance on E1
Interfaces
• QFP144 package
Application
RC7210 Ethernet
4xE1 PHY 107100Mb/s
LED
21
Block Diagram
BA[1:0]
RASCASWE_N A[11:0] DQ[15:0] DQM Control Alarm
tt t t H i t
Control&Alarm
••Mi
MAC
RX_CLK
RX
RX_DV
FIFO
RX_ER
E1POD RXD[3:0]
E1NOD
System
E1PID
E1NID
22
2008 год