Mel ZG641 Course Handout

BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI
WORK INTEGRATED LEARNING PROGRAMMES

Digital
Part A: Content Design
Course Title CAD for IC Design

Course No(s) MEL ZG641
Credit Units 4
Credit Model Theory
Content Authors Debajyoti Biswas
Course Objectives
No Objective
CO1 To introduce VLSI design flow
CO2 To introduce the automation of different steps in VLSI design
CO3 To understand the interrelations between different steps in design
CO4 To understand the integration of steps to develop CAD tool for automation of VLSI design
Text Book(s)
T1 Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu, VLSI Physical Design: From Graph
Partitioning to Timing Closure, Springer, 2011
T2 Sadiq M. Sait, Habib Youssef, VLSI Physical Design Automation: Theory and Practice, World
Scientific Publishing, 1999.
T3 Sabih H Gerez, Algorithms for VLSI Design Automation, John Wiley & Sons Ltd
Reference Book(s) & other resources
R1 N Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Publications, 1999
R2 M Sarrafzadeh and C K Wong, An Introduction to VLSI Physical Design, McGraw Hills.
R3 IEEE, ACM, Elseiver Journals and Transactions
R4 G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill
Learning Outcomes:
No Learning Outcomes
LO1 To understand the VLSI design flow and role of CAD tools in automation
LO2 To understand the working of CAD tools and their interdependence in design flow
LO3 To understands the importance of front-end and back-end tools for IC design satisfying all
constraints.
Part B: Learning Plan
Academic Term First Semester 2022-2023
Course Title CAD for IC Design
Course No MEL ZG641
Lead Instructor Debajyoti Biswas
Contact Hour 1
Type Content Ref. Topic Title Study/HW Resource Reference
Pre CH
During Introduction to VLSI design flow T1 – Ch 1

CH T2 – Ch 1
Post CH
Contact Hour 2
Pre CH
During VLSI Design Styles T1-Ch 1

CH Physical Design Optimizations T2-Ch 1, Appendix A
Graph Theory Terminologies
Post CH
Contact Hour 3
Pre CH
During Partitioning Problem, Constraints T1-Ch 2

CH and Optimization Goals. T2-Ch 2
Post CH
Contact Hour 4
Pre CH Graph Theory
During Partitioning Algorithms- T1-Ch 2

CH Kernighan-Lin (KL) Algorithm T2-Ch 2
and its variations
Post CH Problems based on KL Algorithm
Contact Hour 5
Pre CH Graph Theory
During Partitioning Algorithms- Fiduccia- T1-Ch 2

CH Mattheyses (FM) Algorithm, T2-Ch 2
Simulated Annealing
Post CH Problems based on FM Algorithm
Contact Hour 6
Pre CH Graph Theory
During Clustering and Multilevel T1-Ch 2

CH Partitioning
Post CH
Contact Hour 7
Pre CH
During Floorplanning Problem, T1-Ch 3

CH Constraints and Optimization T2-Ch 3
Goals.
Post CH
Contact Hour 8
Pre CH Graph Theory
During Floorplanning Algorithms- T1-Ch 3

CH Floorplan Sizing, Cluster Growth T2-Ch 3
Post CH Problems on Floorplanning
Contact Hour 9
Pre CH
During Floorplanning Algorithms- T1-Ch 3
CH Simulated Annealing T2-Ch 3
Post CH Problems on Floorplanning
Contact Hour 10
Pre CH
During Placement Problem, Constraints T1-Ch 4

CH and Optimization Goals. T2-Ch 4
Post CH
Contact Hour 11
Pre CH
During Placement Methods - Min-Cut T1-Ch 4

CH Placement, Analytic Placement T2-Ch 4
Post CH Problems on Placement
Contact Hour 12
Pre CH
During Placement Methods - T1-Ch 4

CH Simulated Annealing T2-Ch 4
Post CH Problems on Placement

Contact Hour 13
Pre CH
During Optimization Goals for Routing T1-Ch 5

CH and Global Routing Flow
Post CH
Contact Hour 14
Pre CH
During Single Net Routing - Rectilinear T1-Ch 5

CH Routing, Global Routing in
Connectivity Graph, Shortest
Paths with Dijkstra’s Algorithm
Post CH Problems on Routing
Contact Hour 15
Pre CH
During Full-Netlist Routing and Modern T1-Ch 5

CH Global Routing T2-Ch 5
Post CH Problems on Routing
Contact Hour 16
Pre CH
During Channel Routing Problem, T1-Ch 6

CH Constraints and Optimization T2-Ch 6
Goals.
Post CH
Contact Hour 17
Pre CH
During Channel Routing Algorithms - T1-Ch 6

CH Left-Edge Algorithm T2-Ch 6
Post CH Problems on Channel Routing
Contact Hour 18
Pre CH
During Channel Routing Algorithms - T1-Ch 6

CH Dogleg Routing, Switchbox T2-Ch 7
Routing
Post CH Problems on Channel Routing
Contact Hour 19

Pre CH
During Standard Cells and Optimization of T2-Ch 8

CH Standard Cell Layout
Post CH
Contact Hour 20
Pre CH
During Gate-matrix Layout and its T2-Ch 8

CH Optimization
Post CH
Contact Hour 21
Pre CH
During Layout Editors and Compaction T2-Ch 9

CH
Post CH
Contact Hour 22
Pre CH
During Gate Level Modeling and T3 - Ch 10
CH simulation - Signal Modeling, Gate
Modeling, Delay Modeling
Post CH
Contact Hour 23
Pre CH
During Gate Level Modeling and T3 - Ch 10

CH simulation - Connectivity
Modeling, Compiler Driven
Simulation, Event Driven
Simulation
Post CH Examples on modeling and

simulation
Contact Hour 24
Pre CH
During Switch Level Modeling and T3 - Ch 10

CH Simulation
Post CH Examples on modeling and

simulation
Contact Hour 25
Pre CH
During Combinational Logic Synthesis, T3 - Ch 11

CH Binary-decision Diagrams for
Verification
Post CH Examples on Logic Synthesis
Contact Hour 26
Pre CH
During Two-level Logic Synthesis T3 - Ch 11

CH
Post CH
Contact Hour 27
Pre CH
During Hardware Models for High -Level T3 - Ch 12

CH Synthesis
Post CH
Contact Hour 28
Pre CH
During Hardware Allocation and T3 - Ch 12

CH Assignment
Post CH Examples on Allocation and
Assignment
Contact Hour 29
Pre CH
During Scheduling and Algorithms T3 - Ch 12

CH
Post CH Examples on Scheduling
Contact Hour 30
Pre CH
During Timing Analysis - Static and Lecture notes

CH Dynamic, Power Analysis
Post CH
Contact Hour 31
Pre CH
During Design for Testability (DFT) - Lecture notes

CH Introduction
Post CH
Evaluation Scheme:
Legend: EC = Evaluation Component; AN = After Noon Session; FN = Fore Noon Session
No Name Type Duration Weight Day, Date, Session, Time
EC-1 Assignment-1 Open Book 10% August 16-30, 2022
Assignment-2 Open Book 10% September 16-30, 2022
EC-2 Mid-Semester Test Open Book 2 hours 30% Saturday, 24/09/2022 (FN)
EC-3 Comprehensive Exam Open Book 2 hours 50% Saturday, 26/11/2022 (FN)
Syllabus for Mid-Semester Test (Open Book): Topics in Session Nos. (1 -15)
Syllabus for Comprehensive Exam (Open Book): All topics (Session Nos. 1 to 31)
Important links and information:
Elearn portal: https://elearn.bits-pilani.ac.in
Students are expected to visit the Elearn portal on a regular basis and stay up to date with the latest announcements
and deadlines.
Contact sessions: Students should attend the online lectures as per the schedule provided on the Elearn portal.
Evaluation Guidelines:
1. For Closed Book tests: No books or reference material of any kind will be permitted.
2. For Open Book exams: Use of books and any printed / written reference material (filed or bound) is
permitted. However, loose sheets of paper will not be allowed. Use of calculators is permitted in all exams.
Laptops/Mobiles of any kind are not allowed. Exchange of any material is not allowed.
3. If a student is unable to appear for the Regular Test/Exam due to genuine exigencies, the student should
follow the procedure to apply for the Make-Up Test/Exam which will be made available on the Elearn
portal. The Make-Up Test/Exam will be conducted only at selected exam centres on the dates to be
announced later.
It shall be the responsibility of the individual student to be regular in maintaining the self study schedule as given in
the course handout, attend the online lectures, and take all the prescribed evaluation components such as
Assignment/Quiz, Mid-Semester Test and Comprehensive Exam according to the evaluation scheme provided in
the handout.

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BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI

WORK INTEGRATED LEARNING PROGRAMMES

Course Title CAD for IC Design

CO1 To introduce VLSI design flow

CO2 To introduce the automation of different steps in VLSI design

CO3 To understand the interrelations between different steps in design

Reference Book(s) & other resources

Part B: Learning Plan

Academic Term First Semester 2022-2023

Course Title CAD for IC Design

Course No MEL ZG641

Lead Instructor Debajyoti Biswas

Type Content Ref. Topic Title Study/HW Resource Reference

During Introduction to VLSI design flow T1 – Ch 1

Type Content Ref. Topic Title Study/HW Resource Reference

During VLSI Design Styles T1-Ch 1

Type Content Ref. Topic Title Study/HW Resource Reference

During Partitioning Problem, Constraints T1-Ch 2

Type Content Ref. Topic Title Study/HW Resource Reference

Pre CH Graph Theory

During Partitioning Algorithms- T1-Ch 2

Post CH Problems based on KL Algorithm

Type Content Ref. Topic Title Study/HW Resource Reference

Pre CH Graph Theory

During Partitioning Algorithms- Fiduccia- T1-Ch 2

Post CH Problems based on FM Algorithm

Pre CH Graph Theory

During Clustering and Multilevel T1-Ch 2

Type Content Ref. Topic Title Study/HW Resource Reference

During Floorplanning Problem, T1-Ch 3

Type Content Ref. Topic Title Study/HW Resource Reference

Pre CH Graph Theory

During Floorplanning Algorithms- T1-Ch 3

Post CH Problems on Floorplanning

Type Content Ref. Topic Title Study/HW Resource Reference

Post CH Problems on Floorplanning

Type Content Ref. Topic Title Study/HW Resource Reference

During Placement Problem, Constraints T1-Ch 4

Type Content Ref. Topic Title Study/HW Resource Reference

During Placement Methods - Min-Cut T1-Ch 4

Post CH Problems on Placement

Type Content Ref. Topic Title Study/HW Resource Reference

During Placement Methods - T1-Ch 4

Post CH Problems on Placement

Type Content Ref. Topic Title Study/HW Resource Reference

During Optimization Goals for Routing T1-Ch 5

Type Content Ref. Topic Title Study/HW Resource Reference

During Single Net Routing - Rectilinear T1-Ch 5

Post CH Problems on Routing

Type Content Ref. Topic Title Study/HW Resource Reference

During Full-Netlist Routing and Modern T1-Ch 5

Post CH Problems on Routing

During Channel Routing Problem, T1-Ch 6

Type Content Ref. Topic Title Study/HW Resource Reference

During Channel Routing Algorithms - T1-Ch 6

Post CH Problems on Channel Routing

Type Content Ref. Topic Title Study/HW Resource Reference