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Published in IET Power Electronics
Received on 3rd July 2013
Revised on 15th February 2014
Accepted on 6th March 2014
doi: 10.1049/iet-pel.2013.0514

ISSN 1755-4535

Analysis, design and performance of a soft-switching

single-phase inverter
Chien-Ming Wang, Chang-Hua Lin, Hsin-Yi Lin, Shih-Yung Hsu
Department of Electrical Engineering, National Ilan University, 1, Sec. 1, Shen-Lung Road, I-Lan, 260, Taiwan
E-mail: cmwang@niu.edu.tw

Abstract: A soft-switching pulse-width modulation (PWM) single-phase inverter using a voltage clamp soft-switching step-up/
down dc link is proposed in this study. The proposed voltage clamp soft-switching step-up/down DC link not only provides the
switches in the section of conventional PWM buck inverter operate at zero-voltage-switching (ZVS), but it has a step-up/down
input voltage function and the switches in itself also operate at ZVS. Thus, except for the switch in the section of ZVS-PWM
auxiliary circuit, all power semiconductor devices in proposed inverter operate at ZVS turn-on and turn-off. The switch in the
section of ZVS-PWM auxiliary circuit operates at zero-current-switching (ZCS) turn-on and turn-off. Besides operating at
constant frequency, the proposed inverter has no voltage stress and current stress on the main switch compared to the hard
switching inverter counterpart. Auxiliary components rated at very small current are used. The principle of operation,
theoretical analysis and experimental results of the proposed soft-switching inverter, rated 1 kW and operated at 40 kHz, are
provided in this study to verify the performance.

1 Introduction quasi-RDCL power converters [3–20] for zero-voltage-

Voltage-source pulse-width modulation (PWM) inverters
have been widely used in industrial application such as
uninterruptible power supplies, static frequency changers
and variable speed drivers. This is because of it offers some
advantages as it is easy to implement and the harmonic
power spectrum is located in switching frequency multiples.
The harmonic can easily be eliminated by power filter and
it has a capability in allowing continuous and linear control
of the frequency and fundamental component of the output
voltage. However, for increasing power density, it must
increase the switching frequency to reduce the size and
weight of components. This solution will result in the more
switching losses and electromagnetic interference. Recently,
for improving this problem, a number of soft-switching
PWM technique were proposed aimed at combining
desirable features of both the conventional PWM and
resonant techniques. One of the techniques used in inverters
is to make use of resonant circuit in the DC link. By
obtaining the resonance of the circuit, it can be seen that at
certain moments the voltage is reduced to zero. If the
inverter switches are switched at this moment, then zero
power losses are achieved. There are several circuits
available for producing a resonant DC link (RDCL) and
they are presented in [1–10]. Some of these circuits work at
fixed resonant frequency, that is, the switching moments of
the inverter switches are predetermined by the resonance
period [1, 2]. These kinds of circuits are unsuitable for
PWM techniques because they have not a function which is
continuous variation of the pulse width. In order to improve
this drawback, ‘lot of works have been done on’ the
switching (ZVS) techniques to eliminate switching losses in
pulse-width modulated inverters. These schemes generate
zero voltage instants in DC link at controllable instants,
which can be synchronised with any PWM transition
command, thus ensuring zero voltage switching condition.
As a result, these inverters can be operated at high
switching frequencies with high efficiency, reduced size and
device stresses. ‘However, their AC output voltages are
limited below and cannot exceed the DC-rail voltages.
Thus, they need an additional boost DC/DC converter to
obtain a desired AC output voltage. This solution will
increase system cost and decrease system efficiency’. For
improving this problem and heaving function of inverter,
‘lot of works have been done on the inverter’ with boost
input voltage function [22–30]. In [22], it employs a
soft-switching boost converter to obtain boost function.
However, the switches in conventional inverter stage are
operated at hard switching. For improving it, the
soft-switching techniques about it have been proposed in
[23, 24]. ‘They can obtain good performances’. However,
they are not suitable for conventional inverter topology. The
other topologies are also proposed with boost input voltage
function. They are Z-source inverters [25–30]. They employ
a unique impedance network to couple the inverter main
circuit. They have good performance. They are more
suitable for three-phase inverter. However, they are not
more suitable single-phase inverter.
In order to keep previous function and overcome some
problems, a voltage clamp soft-switching step up/down
DC-link circuit for PWM unipolar single-phase inverter is
proposed in this paper. This proposed voltage clamp

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soft-switching step up/down DC-link circuit is generated from
modified buck–boost DC/DC converter and uses new control
strategy to obtain high frequency pulse DC link in input of
inverter. Thus, the proposed voltage clamp soft-switching
step up/down DC-link circuit not only owns the step up/
down voltage characteristic but provides the ZVS on all
semiconductors in the PWM unipolar single-phase inverter.
Also, the switching cycle of the proposed voltage clamp
soft-switching step up/down DC-link circuit and PWM
unipolar single-phase inverter is synchronous. The
switching noise interference can be removed. Furthermore,
in order to achieve the aim that all semiconductor devices
in the proposed converter operate in soft-switching without
additional voltage stress and current stress, a ZVS-PWM
commutation cell is used in the proposed voltage clamp
soft-switching step up/down DC-link circuit to provide the
semiconductor devices in the proposed voltage clamp
soft-switching step up/down DC-link circuit operate in
soft-switching. Thus, the switching losses in the proposed
inverter can be reduced. For achieving good dynamic
regulation and properly gating the power switches, the
sinusoidal PWM (SPWM) control strategy is designed in
the proposed inverter. System analysis for predicting and
evaluating the inverter performance are conducted.
2 Principle of the proposed soft-switching
single-phase inverter
The power stage diagram of the proposed soft-switching
single-phase inverter is shown in Fig. 1. The circuit can be
divided in three sections. The first section is a conventional
PWM buck inverter with unipolar voltage switching. It is
composed of the switches S1, S2, S3, S4 and output filter Lf,
Cf. This section performs the operation of conventional
PWM buck inverter with unipolar voltage switching. The
second section is the proposed voltage clamp soft-switching
step up/down DC-link circuit, composed of LB, SB, CB and
the body diodes of the switches S1, S2, S3 and S4. This
section is synchronous with the first section circuit. It
provides a step up/down voltage function in high frequency
pulse DC link and the ZVS on all semiconductors in the
first section circuit. The third section is a ZVS-PWM
auxiliary circuit to provide the ZVS on the switch SB and
the body diodes of the switches S1, S2, S3 and S4. It is
Fig. 1 Proposed soft-switching inverter using a voltage clamp soft-switching step up/down DC link
IET Power Electron., 2014, Vol. 7, Iss. 9, pp. 2412–2423
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composed of the auxiliary diodes Da1, Da2, the resonant
inductors Lr, the resonant capacitors Cr, transformer Tr and
auxiliary switch Sa, which are rated for a small power
compared to the output power. To simplify the analysis, it
is assumed that the proposed soft-switching single-phase
inverter is operating in the kth switching period and the
following assumptions are made during one switching cycle.
1. The inductor LB is large enough to assume that the current
ILB is constant during the kth switching period and is much
greater than resonant inductor Lr.
2. The output filter inductor Lf is large enough to assume that
the output current ILfk is constant during the kth switching
period.
3. The capacitor CB is large enough to assume that the
voltage VCB is constant during the kth switching period.
4. Input voltage Vin is constant.
5. During the kth switching period, the resonant voltage
vCr(t) equals Vin + VCB, and the resonant currents iLr(t)
equals zero.
Based on these assumptions, circuit operations in one
switching cycle can be divided into 12 stages. The 12
dynamic equivalent circuits of the proposed soft-switching
single-phase inverter during one switching periods are shown
in Figs. 2–4. The ideal relevant waveforms of the proposed
soft-switching single-phase inverter are shown in Fig. 5.
2.1 Stage of operation of the proposed
soft-switching single-phase inverter
Stage 1 [Fig. 2a: t0 < t < t1]: Before t = t0, the switches S1,
S2, SB and Sa are in turn-off state, the switches S3 and S4 are
in turn-on state. The energy stored in inductor LB is delivered
to capacitor CB while the output loop is in a freewheeling
state. This stage begins when Sa turns on with
zero-current-switching (ZCS). The resonant inductor Lr
charges linearly from Vin and VCB. Thus, The resonant
current iLr(t) is increased linearly. The stage ends when the
resonant current iLr(t) reaches ILB + ILfk and body diodes
of switches S1, S2, S3 and S4 turn off with ZCS at t = t1
Vin + (n − 1/n)VCBk
iLr (t) = (t − t0 ) (1)
Lr
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Fig. 2 Commutation stage diagrams of stages 1–4 of proposed soft-switching inverter

a stage 1 c stage 3
b stage 2 d stage 4

Fig. 3 Commutation stage diagrams of stages 5–8 of proposed soft-switching inverter

a stage 5 c stage 7
b stage 6 d stage 8

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Fig. 4 Commutation stage diagrams of stages 9–12 of proposed soft-switching inverter

a stage 9 c stage 11
b stage 10 d stage 12

vCr (t) = Vin + VCBk (2) ZCS and, the auxiliary switch Sa also can be turned off at
ZCS in this moment
Stage 2 [Fig. 2b: t1 < t < t2]: During this stage, the
Vin + (n − 1/n)VCBk
ZVS-PWM auxiliary circuit performs resonance behaviour. iLr (t) = (Iin + ILf k ) + sin vr (t − t1 )
The resonant current iLr(t) increases and resonant voltage Zo
vCr(t) decreases. The energy stored in capacitor CB and DC VCBk
input source voltage are gradually provided to the PWM − (t − t2 ) (7)
Lr
unipolar buck inverter. The stage is finished when the
resonant voltage vCr(t) is dropped to zero vCr (t) = 0 (8)

Vin + (n − 1/n)VCBk
iLr (t) = (Iin + ILf k ) + sin vr (t − t1 ) Stage 4 [Fig. 2d: t3 < t < t4]: During this stage, the inductor
Zo
LB continuously charges energy from DC input source. The
(3) DC input source and the energy stored in capacitor CB

 continuously supply to output stage
vCr (t) = Vin + VCBk − (n − 1/n)VCBk cos vr (t − t1 ) (4)
iLr (t) = 0 (9)
where
 vCr (t) = 0 (10)
Zo = Lr /Cr (5)
Stage 5 [Fig. 3a: t4 < t < t5]: This stage begins when the
1
vr =  (6) switch SB turns-off at ZVS. The current ILB charges linearly
Lr Cr the resonant capacitor Cr. The resonant voltage vCr(t)
increases linearly. This stage is finished when the resonant
Stage 3 [Fig. 2c: t2 < t < t3]: This stage begins when the voltage vCr(t) is equaled Vin + VCB
resonant voltage vCr(t) equals zero and the switch SB turns
on at ZVS. The energy stored in resonant inductor Lr is iLr (t) = 0 (11)
delivered back to capacitor CB via the transformer Tr. The
Iin
resonant current iLr(t) is decreased linearly. The inductor LB vCr (t) = (t − t4 ) (12)
charges energy from DC input source. The DC input source Cr
voltage and the energy stored in capacitor CB are
continuously supplied to output stage. This stage ends when Stage 6 [Fig. 3b: t5 < t < t6]: This stage begins when the
the resonant current iLr(t) is dropped to zero and the body body diode of the switches S1, S2, S3 and S4 turn-on at
diode of the switch SB, diodes Da1, Da2, naturally close at ZVS. The energy stored in inductor LB is delivered to

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Fig. 5 Ideal relevant waveforms of the soft-switching single-phase inverter

capacitor CB. The output stage starts a freewheeling state.
This stage is finished when switch Sa is triggered again
iLr (t) = 0
vCr (t) = Vin + VCBk
Stage 7 [Fig. 3c: t6 < t < t7]: This stage begins when Sa
turns-on with ZCS again. The resonant inductor Lr charges
linearly from Vin and VCB again. The resonant current iLr(t)
(13) is increased linearly. The stage ends when the resonant
current iLr(t) reaches ILB and body diodes of switches S1
(14) and S2 turn off with ZCS at t = t7

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Vin + (n − 1/n)VCBk switching period
iLr (t) = (t − t0 ) (15)
Lr
vCr (t) = Vin + VCBk (16) iLr (t) = 0 (25)

Stage 8 [Fig. 3d: t7 < t < t8]: During this stage, the vCr (t) = Vin + VCBk (26)
ZVS-PWM auxiliary circuit performs resonance behaviour
again. The resonant current iLr(t) increases and resonant
voltage vCr(t) decreases. The output stage performs a
freewheeling state. The stage is finished when the resonant After stage 12, the circuit operation is returned to the first
voltage vCr(t) is dropped to zero stage. The voltage of the resonant capacitor Cr equals to
Vin + VCB, and the current of the resonant inductor Lr is
also equaled to zero. Thus, the assumption previously made
Vin + (n − 1/n)VCBk
iLr (t) = (Iin + ILf k ) + sin vr (t − t7 ) is proven to be valid.
Zo
(17)

 2.2 Conduction time of the switch of ZVS-PWM
vCr (t) = Vin + VCBk − (n − 1/n)VCBk cos vr (t − t7 ) (18) auxiliary circuit

From the stage 1 analysis of the circuit operation in previous

Stage 9 [Fig. 4a: t8 < t < t9]: This stage begins when the section, the resonant current can be obtained as following
resonant voltage vCr(t) equals zero and the switch SB
turns-on at ZVS. The energy stored in resonant inductor Lr
Vin + (n − 1/n)VCB
is delivered back to capacitor CB via the transformer Tr. iLr (t) = (t − t0 ) (27)
The resonant current iLr(t) is decreased linearly. The Lr
inductor LB charges energy from DC input source. The
output stage continuously performs a freewheeling state.
where n is transformer turns ratio of the ZVS-PWM auxiliary
This stage ends when the resonant current iLr(t) is dropped
circuit and resonant current iLr(t) reaches ILB + ILfk at the end
to zero and the body diode of the switch SB, diodes Da1,
of stage 1. Thus,
Da2, naturally close at ZCS and, the auxiliary switch Sa also
can be turned-off at ZCS in this moment
Vin + (n − 1/n)VCB
V + (n − 1/n)VCBk iLr (t1 ) = ILB + ILf k = (t1 − t0 ) (28)
iLr (t) = (Iin + ILf k ) + in sin vr (t − t7 ) Lr
Zo
VCBk
− (t − t8 ) (19) Lr (ILB + ILf k )
Lr Dt1 ; t1 − t0 = (29)
Vin + (n − 1/n)VCB
vCr (t) = 0 (20)
The resonant voltage vCr(t) drop to zero at the end of the stage
Stage 10 [Fig. 4b: t9 < t < t10]: During this stage, the 2. Thus
inductor LB continuously charges energy from DC input
source. The output stage still performs a freewheeling state vCr (t2 ) = 0
iLr (t) = 0 (21) VCB
= + (Vin + (n − 1/n)VCB ) cos vr (t2 − t1 ) (30)
n
vCr (t) = 0 (22)
 
1 −1 −VCB
Stage 11 [Fig. 4c: t10 < t < t11]: This stage begins when the Dt2 ; t2 − t1 = cos (31)
vr nVin + (n − 1)VCB
switch SB turns-off at ZVS. The current ILB charges linearly
the resonant capacitor Cr. The resonant voltage vCr(t)
increases linearly. This stage is finished when the resonant The resonant current iLr(t) in stage 3 can be obtained as
voltage vCr(t) is equaled Vin + VCB following

iLr (t) = 0 (23)

VCB /n
iLr (t) = iLr (t2 ) − (t − t2 ) (32)
I Lr
vCr (t) = in (t − t10 ) (24)
Cr
The resonant current iLr(t) drop to zero at the end of the stage
Stage 12 [Fig. 4d: t11 < t < t12]: This stage begins when the 3. Thus
body diode of the switches S1, S2, S3 and S4 turn-on at ZVS.
The energy stored in inductor LB is delivered to capacitor CB.
VCB /n
The output stage continuously performs a freewheeling state. iLr (t3 ) = 0 = iLr (t2 ) − (t3 − t2 ) (33)
This stage is finished when switch Sa is triggered again in next Lr

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where 2.3 Output characteristics
  In steady-state operation, the integral of the inductor voltage
1 −VCB
Dt2 ; t2 − t1 = cos−1 (34) vLBk over the kth switching period must be zero. Thus
vr nVin + (n − 1)VCB

Ts
Vin + (n − 1/n)VCB vLBk dt = 0 (39)
iLr (t2 ) = ILB + ILf k + 0
Zo
  
−1 −VCB Thus
× sin cos (35)
nVin + (n − 1)VCB
Dcon Ts − (2Dt1 + Dt2 )
  VCB  (40)
1 nZo iLr (t2 ) (1 − Dcon )Ts + (2Dt1 + Dt2 )
Dt3 ; t3 − t2 = sin−1 (36)
vr VCB The output voltage Vok is

In order to achieve soft commutation at ZVS for the active

Ts
switches, for the described operation mode, the following Vok = vAB dt
inequalities should be satisfied. The time interval Dton,Sa to 
0

turn on the switch Sa is governed by Dt2 Dt5
= Dinvk Ts − Dt1 − − (Vin + VCB ) (41)
2 2
Dton,Sa = Dt1 + Dt2 + Dt3
 where
1 Zo (I LBk + ILf k )
=
vr Vin + (n − 1/n)VCB (37) Cr (Vin + VCB )
  Dt5 = (42)
−VCB nZ i (t ) ILBk + ILf k
+ cos−1 + o Lr 2
nVin + (n − 1)VCB VCB
2.4 Control strategy
and this time interval must be less than the minimum
conduction time The block diagram of the proposed soft-switching inverter is
shown in Fig. 6. The controller of proposed soft-switching
inverter consists of an isolated voltage sensor, a sinusoidal
Dton,Sa ≤ Dinv, min Ts (38) generator, a voltage error amplifier, a current error
amplifier, a pulse-width modulator and a control logic
where Dinv, min is minimum duty-cycle of inverter. circuit. It uses two control loops which are voltage and

Fig. 6 Controller of the proposed soft-switching inverter

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current control loops and SPWM technique to obtain good Thus
dynamic function. The voltage error amplifier is necessary
to compare the sampled output voltage signal with the iDS1, max = iDS2, max = iDS3, max = iDS4, max  io, max
reference from the sinewave generator. The output signal of √
voltage error amplifier is inputted to the current error 2Po, max
= (48)
amplifier and compared with the sampled inductor current Vo,rms
signal. Then, the output signal of current error amplifier
drives the pulse-width modulator to generate a pulse train, vD1, max = vD2, max = vDS1, max = vDS2, max  VCB
which is prescribed to have a constant period with a Vin
variable duty ratio for gating the power switch. After the = (49)
pulse-width modulator and control logic circuit, the gating 1 − Dcon
signals for SB, Sa, S1, S2, S3 and S4 can be obtained. Po, max
iDSB, max = (50)
Vin
3 Design considerations
vDSB, max = Vin + VCB (51)
The implemented power stage circuit of proposed
soft-switching single-phase inverter is shown in Fig. 1. The
design procedure of proposed converter is described as
follows with previously described circuit characteristics: And, the maximum current through the auxiliary switch Sa
and the maximum voltage across the auxiliary switch Sa can
(1) Considerations on inductor current ripple and select the also be obtained as follow from the circuit operation
input inductor LB: the inductor current ripple on inductor
can be denoted as follows Vin + VCB (n − 1/n)
iDSa, max  Iin + io, max +
Zo
Vin √ (52)
DILB = D T (43) P 2Po, max Vin + VCB (n − 1/n)
LB con s = o, max + +
Vin Vo,rms Zo
Under certain input current ripple requirement, the value of vDSa, max  Vin + VCB (1 + 1/n) (53)
input inductor LB can be obtained as follows

Vin And, the maximum current through the auxiliary diodes Da1,
LB = D T (44) Da2 and the maximum voltage across them can also be
DILB con s obtained as follow from the circuit operation

(2) Considerations on DC-link voltage ripple and select Vin + VCB (n − 1/n)
iDa1, max = Iin + io, max +
DC-link capacitor: The principal factor affecting the value Zo
of DC-link capacitance is utilisation of enough capacitance √ (54)
to meet device ripple current ratings. Subtracting input P 2Po, max Vin + VCB (n − 1/n)
= o, max + +
current from iSB is the current of DC-link capacitor. The Vin Vo,rms Zo
frequency of the current of DC-link capacitor is twice as
 
high as the switching frequency. Therefore the DC-link 1 V + VCB (n − 1/n)
ripple voltage can be reduced. Because the DC-link iDa2, max = Iin + io, max + in
n Zo
capacitor includes an equivalent series resistance (RESR), the  √
DC-link ripple voltage ΔVCB must be divided in two 1 Po, max 2Po, max Vin + VCB (n − 1/n)
sections which are the contributions from the capacitance = + +
n Vin Vo,rms Zo
and the equivalent series resistance. They can be estimated
as follows (55)

Iin vDa1, max  Vin + VCB (56)

DVC = D T (45)
CB con s vDa2, max  VCB (57)
DVRESR = iCB × RESR (46)
 (4) Select the resonant parameters: from circuit operation
DVCB  DVC2 + DVR2ESR (47) analysis, the resonant inductor peak current can be obtained
according to

Under certain output ripple voltage requirement, the value VCB n − 1

iSa,peak = iLr,peak = (ILB, max + ILf , max ) + · (58)
of output capacitor Co can be estimated. Zo n

(3) Select power switches and diodes: from the circuit
operation analysis, the maximum current through the main
switches and diodes SB, S1, S2, S3, S4, Sa, Da1, Da2 and the
maximum voltages across them in the proposed
soft-switching single-phase inverter are the same as for a
standard hard-switching single-phase buck inverter design.
it is possible to verify that high values of Zo will reduce the
values of iSa,peak. Thus, using a relatively large Zo value can
reduce the current stress of switch Sa. However, the value
of Zo is relative to the value of Δton,Sa. If the value of Zo is
too large, the effective duty ratio will be deteriorated. Also,

Zo = Lr /Cr ⇒ Cr = Lr /Zo2 and a small Lr value is usually

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Fig. 7 Voltage waveforms before and after output filter, and communication phenomenon of switches
a Voltage waveform VAB before output filter the voltage waveform Vo after output filter
b Commutation in the step up/down DC-link switch SB and auxiliary switch Sa.

Fig. 8 Communication phenomenon of main switches

a switch S1 c switch S3
b switch S2 d switch S4

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employed to avoid the effective duty ratio deterioration. Thus, 1 1 Zo (I LBk + ILf k )
if the value of Zo is too large, then Cr will have a relatively ⇒ vr =  ≥
small value, which can be smaller than the parasitical Lr Cr D T
inv, min s V in + (n − 1/n)VCB
  (61)
circuit/component capacitors increasing the difficulty in −1 −VCB nZo iLr (t2 )
design and circuit realisation. + cos +
nVin + (n − 1)VCB VCB
And, because the minimum conduction time of inverter is
set as following in this paper Thus, the Lr and Cr cab be obtained from Zo and ωr.

Dinv, min Ts (59) (5) Determination of the output filter components of the
inverter: the output filter inductor Lf and capacitor Cf to
Thus minimise the undesired harmonics of the output voltage.
They can be obtain form the cutoff frequency of output
 filter through standard single-phase inverter design.
1 Zo (I LBk + ILf k )
Dton,Sa =
vr Vin + (n − 1/n)VCB
  4 Experimental results
−VCB nZ i (t ) (60)
+ cos−1 + o Lr 2
nVin + (n − 1)VCB VCB To experimentally characterise the proposed soft-switching
single-phase inverter, a breadboard was constructed to the
≤ Dinv, min Ts specifications listed as follows:

Fig. 9 Experimental results of vo(t) and io(t) with

a Resistive load (RL = 12 Ω)
b Inductive load (RL = 12 Ω and LL = 15 mH)
c Rectifier with RLC load (RL = 12 Ω, LL = 4.5 mH and CL = 470 μF)

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† Input voltage: 200 VDC √
† Output voltage: vo (t) = 110 2 sin [2p(60)]t
† Output power: 1000 W maximum
† Switching frequency: 40 kHz
† Transformer turns ratio of ZVS-PWM auxiliary circuit:
n=3
Using the design procedure discussed in the previous
section as a guide, the experimental converter was
constructed using the following components:
† Input inductors LB: 650 μH
† DC-link capacitor CB: 940 μH
† Resonant inductor Lr: 12 μH
† Resonant capacitor Cr: 7.5 nF
† Main power switches SB, S1, S2, S3 and S4: IXFK44N80P
† Auxiliary power switch Sa: IRG4PC50UD
† Auxiliary power diodes Da1, Da2: S30L60
The voltage waveforms before and after output filter are
shown in Fig. 7a. The commutation phenomenon in the
switches SB, Sa, S1, S2, S3 and S4 are measured in Figs. 7b
and 8, respectively. The experimental results shown in
Figs. 7b and 8, demonstrate that ZVS is achieved at
constant frequency for the switches (SB, Sa, S1, S2, S3 and
S4). Therefore the switching energy losses for this
Fig. 10 Transient waveforms and experimental efficiency of
presented inverter
a Transient waveforms of the output voltage and current during load change
b Experimental efficiency comparison of the proposed soft-switching inverter
and the combination circuit of the conventional hard-switching PWM boost
DC/DC converter and PWM single-phase inverter
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soft-switching single-phase inverter are practically zero. ‘In
order to assess the dynamic performance of the presented
inverter, three kinds of loads (resistive R, inductive RL and
rectifier with RLC) are examined in Fig. 9, in which the
measured total harmonic distortions of output voltage for
the mentioned loads are given as 1.7% for the R load,
2.63% for the RL load and 5.25% for the rectifier with the
RLC load’. The transient waveforms of the output voltage
and current during load change are shown in Fig. 10a. The
efficiency of the presented soft-switching single-phase
inverter in comparison the combination circuit of the
conventional PWM boost DC/DC converter and PWM
single-phase inverter is also measured in Fig. 10b. The
experimentally obtained efficiency from the proposed
soft-switching single-phase inverter is equal to 93% and
from the combination circuit is equal to 87.5%, for rated load.
5 Conclusion
This paper has presented a soft-switching single-phase
inverter with a simple and compact configuration. The
operation of the proposed inverter was analysed with a
voltage clamp soft-switching step up/down DC link. The
proposed voltage clamp soft-switching step up/down
DC-link circuit not only owns the step up/down voltage
characteristic but provides the ZVS on all semiconductors
in the PWM unipolar single-phase inverter. All
semiconductor devices in the proposed soft-switching
single-phase inverter operate at ZVS turn-on and turn-off.
The proposed inverter is regulated by the conventional
SPWM technique at constant frequency. Therefore, the
proposed soft-switching inverter combines the advantages
of the SPWM and ZVS techniques, without additional
voltage stress current stress, in comparison with the
conventional hard-switching single-phase inverter,
improving the inverter performance and maintaining high
efficiency. High power efficiency over 93% is acquired
under the rated power of 1000 W for proposed
soft-switching single-phase inverter. Some experiment
results prove the truth of the theoretical prediction.
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