1

2
With transistor dimension shrinking into nanoscale regime, conventional gate
oxide thickness has also been scaled. This scaling trend brings issues about
carrier mobility degradation (among other SCEs) related to the high electric
fields (along the channel and normal to it).

3
The values indicated here are weak function of the fabrication technology.

4
5
6
- Lw 3arfeen el Affinity hn3dr n3rf e7na nzelna l8ayet feen mn awl el reference bta3en el hoaw el Evacuum, 4.22 maslan fe 7alet el pure Silicon, fe 7alet el SiGe hnzbtoh 3ala 4.1, y3ni hn3ml el Germanium
content el monaseb masalan b7es ygebli 4.1 deh w b3dha nrga3 tani 3and el Bulk Silicon El X=4.2.
- Ta7t el Ec hn7ot el Eg el heya 1.12 fe 7alet el Si 3and el Cap Si w el Bulk Si, w Eg,Ge=1ev bta3et el germanium el fel nos m7soba mn ta7t el Ec.
- El step fel Ec so8ayara w fel Ev kbera

Adjusted 3n taree2
el mole fraction x
FB Adjusted 3n taree2 el mole fraction x
EBD

Over an n-type Si substrate a thin layer of almost intrinsic (or slightly p-type)
epi-SiGe is grown then a capping n-type epi-Si layer if finally grown before
oxide formation.

According the energy band diagram (EBD) there will be a well that
confines the carrier flow in a region far from the Si/SiO2 interface
(see next slide).

In CMOS technology this is done exclusively for the PMOS while

the NMOS is left as it is without band gap modification. The result
is almost equal electrons and hole mobilities.

7
 El Ge
content
howa el
by7dd el
step deh 2d
eh

This EBD can be drawn under negative bias at the gate. A p-channel will
be confined to the thin region
where the Fermi level is close or higher than the valence-band edge Ev.
Since the channel hole confinement is far from the Si/SiO2 interface the mobility
is enhanced. The SiGe and capping Si layers should have a
proper interface (this is called a pseudomorphic structure
that will be defined in the next slide).

8
El mobility bta3et el electrons fel bulk btb2a fe range el 1400 lakn btnzel fel n-channel l range el 800 34an el interface states w el collisions m3 el interface states w el high field by5eli el surface mobility t2el
bardo w nafs el kalam l mobility el p-channel bs btb2a 2olyla awi w e7na 3amlan compensation lel PMOS 3n taree2 el buried channel

Surface mobility in classical pMOS = 300 – 350 cm2/Vs

After enhancement (buried channel) it becomes 750 – 800 cm2/Vs
which is in the same range as nMOSFET surface mobility
(around ½ bulk mobility value).
That is why we focus on SiGe pMOS enhancement to be identical with
the Si nMOS.

9
10
11
12
- hena 7atina el small lattice constant over el large lattice constant fa el silicon lw kan pseudomorphic w a5d nafs el lattice position bta3et el SiGe, hnla2i el Si atoms htbda2 tb3ed 3n b3deha fa dh tensile
stress ka2nena bn4ed el mada eli foo2 el heya el silicon
- ma3na en el atoms b3det 3n ba3d en keda el mobility of electrons htt7asen la2n el scatterting hy2el

The SiGe layer is a thick Epi-layer grown on the Si substrate.

Then a thin strained channel of epi-Si is grown over the relaxed SiGe.
The interface between the bulk Si and the relaxed SiGe is not
electrically important while that between the Si channel and the underlying
SiGe should be as ideal as possible. This pseudomorphic strained Si
layer makes low interface states with the underlying SiGi. It is also
under tensile stress which enhances the electron mobility in MMOS
transistors (there is a similarity with the microwave transistors called PHEMT:
pseudomorphic high electron mobility transistors while being low cost since
it is based on Si rather than compound semiconductors).

13
14
15
Lw 3amlna compressive stress hnkbar el mobility bta3et el holes fel p-type MOSFET
- Compressive stress yb2a el layer el foo2 heya el hatko el lattice constant bta3ha akbar mn el ta7t 34an lama a3ml el Epitaxy slowly and give the process the required and sufficient time and temperature,
and make a very thin layer (2 to 3 atomic layers) y2om el atoms bta3et el layer el foo2 t2rab mn ba3d 34an htb2a wa5da nafs el positions zy el layer el ta7teha fa y7sal el compressive stress

More compact structure results in less vibration motion and

scattering is hence lowered.

16
Upper surface in tension and lower surface in compression.
Transistors are fabricated and tested on a stressed wafer

17
El silicon el foo2 hya5od nafs el lattice constant bta3 el SiGe, bta3 el Si aslan as8ar fa lma n7oto 3ala 7aga leha lattice constant akbar w nt2kd enha 5adet nafs el structure bta3 el underlying layer el heya
SiGe hnla2i el Silicon 7asalo tensile(elongation) stress

Shallow
junction
under the
sidewall
oxide

- sSi: Strained Si
- SRB: Strain Relaxed Buffer. It is relaxed relatively thick SiGe epitaxially
grown on Si substrate (see B in Slide 6). The damaged lower interface
is not important.
- This results in NMOSFET with tensile stressed Si channel.
- Notice this is different than the buried channel (here x is lower).

18
- el cap heya el top layer of silicon el heya rofy3a (2 to 3 atomic layers) w bn3mlha by selective epitaxy w btkon strained la2nha over SiGe el 3ando lattice constant akbar mn bta3 el Silicon fa el Silicon
hyb2a under tensile stress fel 7ala deh
- lazm ykoon strained silicon la2n dh bydmnli aql interface states been el Si w el SiGe

electrons etgm3t hena Enhancement

3and el sat7 Due To
Stress
+ve Vgate 34an Engineering
N-MOSFET

Enhancement Due to
Energy Band Gap
Engineering

El holes etgm3t fel

burried channel
due to el electric field
Confined holes due to large barrier (burried channel) (current is in
the direction perpendicular to the page)

As seen under FB condition, the thick SiGe layer will be relaxed while the cap
thin Si layer will be strained (stretched).
There are two types of enhanced MOSFETs using this structure:
1- The buried channel for a PMOS ( x  30%). p+ D/S should be deep
enough to reach the buried channel.
2- The strained Si n-channel in the cap region (x  30 % - say 20%).
The n+ D/S should be shallow enough not to reach the Si/SiGe interface.
There will be also an opposite bias and doping for the two cases.

19
El stress akbar fi el Si3N4

This is a global stressor. Spacer (black feature) is necessary for LDD.

Nitride spacer is better than oxide spacer to enhance electron mobility.

- Worth noting that Silicon nitride (Si3N4) capping layer produces a high
level of stress. Si3N4 film can have either tensile or compressive strain
depending on the deposition process step (CVD: tensile, PECVD: compressive).
Si3N4 drive currents for both n- and p-channel MOSFETs can be improved
by controlling the stress of the Si3N4 layer selectively.

- Si3N4 capping layer cannot be too thick because it can cause wafer
bending and thus will cause wafer broken.

20
 Current a3la 34an el mobility et7asent

Process induced strain

Without any strain

El t8ayor fe dimensions el Si nategt el stress bta3 el Si3N4

21
 relatively lower density
relatively higher density

Plasme Enhanced CVD

- Si3N4 film can have either tensile or compressive strain

depending on the deposition process step (CVD: tensile, PECVD: compressive –
high density silicon nitride).
This layer stops the etching needed to form the D/S CONTACT.
It is called CESL: Contact Etch Stop Layer.
CTE is higher than Si in the tensile case and lower than Si in the
compressive case.
- In PECVD, films can be exposed to energetic ion bombardment during
deposition. This bombardment can lead to increases in the density of the film,
and help remove contaminants, improving the film's electrical and mechanical
properties.
- As density of the deposited nitride layer becomes higher, the thermal
expansion becomes harder. TCE of nitrides becomes lower than that of Si
leading to compressive stress.

22
23
Sa3b enena na5od goz2 mn el wafer n3melo CVD 3adi w goz2 tani Plasma enhanced CVD, el ashal enena nst5dm el SiGe nafso fel Drain w el source 34an n3mel compressive stress lel silicon w n7sol
3ala p-channel mosfet with better characteristics due to mobility enhancement

Note that the selective epi is in the vertical direction with larger
lattice constant SiGe over Si
No epi in the horizontal direction!

24
 Raised Drain/Source
Raised Drain/Source

Why not complete Ge (x = 1)?

Lattice mismatch is so high to get defect-free epi S/D.
Here we have to recess Si surface first then grow SiGe.
Raised D/S helps in forming better transistors with low series resistance.
RDS is easy to do in selective epitaxy.

25
PMOS NMOS

26
Assume acceptable NMOS drive current capability we stress only the PMOS
to try to get equal drives (equal mobilities). There will be no need to
increase the PMOS width.

TCAD simulation can be done to prove these concepts.

27
TCAD simulation can be done to prove these concepts.
The given pallet gives the stress scale (–ve for compressive stress).
The result shows the lateral compressive stress induced
by the embedded SiGe raised D/S and process stressor
cap and sidewalls (compressive).

Sometimes vertical compressive stress

inside SiC raised D/S (SiC has a lower lattice constant than Si),
puts the surface under lateral tensile stress which
enhances the electron mobility. This lateral expansion
is associated with vertical compression.

28
Intel starts using SiGe for PMOS in 2004 for the 90 nm node.

29
Intel starts using SiGe for PMOS in 2004 for the 90 nm node.

30
31