THE UNIVERSITY OF DA NANG

DANANG UNIVERSITY OF SCIENCE AND TECHNOLOGY

FACULTY OF ADVANCED SCIENCE AND TECHNOLOGY

GRADUATION THESIS
CMOS 28 NM PROCESS
SUB-BANDGAP VOLTAGE REFERENCE DESIGN:
TRADITIONAL AND SWITCHED-CAPACITOR ARCHITECTURE

INSTRUCTOR : PhD. LE QUOC HUY

STUDENT : NGUYEN DUC HUY – HUYNH NGOC TIEN
STUDENT ID : 122140019 – 122140049

DaNang, 02nd July 2019

 Contents

Overview

Bandgap Voltage Reference Theory

Traditional Sub-bandgap voltage reference

Switched-capacitor Sub-bandgap voltage reference

Conclusion

6/26/2019 Huy Nguyen – Tien Huynh 2

 Contents

Overview

Bandgap Voltage Reference Theory

Traditional Sub-bandgap voltage reference

Switched-capacitor Sub-bandgap voltage reference

Conclusion

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 OVERVIEW
OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAP BGR CONCLUSION

Sub-Bandgap Voltage Reference

 “Bandgap references are dc quantities that exhibit little dependence on

supply and process parameters and a well-defined dependence on the
temperature”1.

LOW POWER LOW VOLTAGE

Microprocessor die area scalling2

 The need of low voltage references, so that we call Sub-bandgap Voltage

Reference (Sub-BGR)

1 B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.

2 https://www.pcmag.com/article/352738/intels-10nm-process-its-more-than-just-chip-scaling

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 Contents

Overview

Bandgap Voltage Reference Theory

Traditional Sub-bandgap voltage reference

Switched-capacitor Sub-bandgap voltage reference

Conclusion and Future Work

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 OVERVIEW BGR
BGRTHEORY
THEORY TRADITIONAL BGR SWITCHED-CAP BGR CONCLUSION

Reference Voltage
VDD
VDD

IC nI0 I0

VEB + ∆VEB -
V V
Q
Q1 1:N Q2

0C 0C

VCTAT (complementary to absolute temperature) VPTAT (proportional to absolute temperature)

V𝑅𝐸𝐹 = α1 V𝐵𝐸 + α2 ∆𝑉𝐵𝐸

α1 , α2 are chosen so that:
𝜕VEB1 𝜕∆V𝐸𝐵
α1 +α2 = 𝑇𝐶𝑉𝑅𝐸𝐹 = 0
𝜕𝑇 𝜕𝑇

VREF is independent of temperature

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 Contents

Overview

Bandgap Voltage Reference Theory

Traditional Sub-bandgap voltage reference

Switched-capacitor Sub-bandgap voltage reference

Conclusion

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAP BGR CONCLUSION

Requirement Specification

Parameter Value
Supply voltage (V) 1.2  1.8V
Technology process CMOS 28nm
Temperature range (0C) -40  1050C
VREF(V) 0.6 V
Temperature variation (corner) 1%
Current consumption (µA) 5 µA

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAP BGR CONCLUSION

Schematic

OP AMP

Trimming Circuit

Start-up Bandgap Core

Schematic design of the whole BGR circuit

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAP BGR CONCLUSION

Bandgap Core

𝑉𝐸𝐵1 − 𝑉𝐸𝐵2 𝛥𝑉𝐸𝐵

𝐼𝑅1 = =
𝑅1 𝑅1
𝑉𝐸𝐵1
ISUM ISUM 𝐼R2 =
𝑅2
N3 N4 𝑉𝐸𝐵1 𝛥𝑉𝐸𝐵
OP AMP IR1 IR2 𝐼𝑆𝑈𝑀 = +
𝑅2 𝑅1

N1 N2 𝑉𝐸𝐵1 𝛥𝑉𝐸𝐵
𝑉𝑅𝐸𝐹 = 𝑅3 +
𝑅2 𝑅1
1 : 41
𝑅3 𝑅3
α1 = , α2 =
𝑅2 𝑅1
Bandgap voltage reference architecture proposed by Leung1

• Adjust R1,R2 to have ZTC

• Adjust R3 to have suitable value of VREF
1P. K. M. K. N. Leung, "A Sub-1-V 15-ppm/ C CMOS Bandgap Voltage Reference Without Requiring Low Threshold Voltage Device," IEEE Journal of Solid-State Circuits, vol. 37,
no. 4, p. 526–530, 2002.

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAP BGR CONCLUSION

Op-Amp

OP AMP

Traditional bandgap voltage reference architecture

 The op-amp is used to maintain equal node voltage  Make the voltage
drop on resistor R1 be exactly equal the different of VBE between Q1 and Q2.

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAP BGR CONCLUSION

Op-Amp

41dB

43°

Frequency response of the whole circuit

Schematic design of the symmetrical Op-Amp Closed-loop time response for 450,600, and 900
phase margins1

The phase margin (PM) which is equal to 430 is not large enough for the circuit.

1 B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAP BGR CONCLUSION

Op-Amp
 In order to improve PM, the use of a technique is called “Miller compensation”1.

41dB

62°

Frequency response of the whole circuit

This value of PM is large enough for the

Schematic design of the symmetrical Op-Amp BGR circuit work stably.
1 B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAP BGR CONCLUSION

Start-up Circuit

OP AMP

Trimming Circuit

Start-up
Schematic design of the whole BGR circuit

 BGR circuit consists a zero state: Vin+ and Vin- are at the ground potential
 no current flow in the bandgap core and no voltage reference at the output.

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAP BGR CONCLUSION

Start-up Circuit

 Generating VO that provide for the gate of 3

PMOS in BGR core -> Creating current in core
and then VREF

 Two requirements:
- Having the least effect on the proper operation
of the BGR circuit.
- Completely isolated with the BGR core when
the proper bias point is established.

Schematic design of Start-up circuit

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAP BGR CONCLUSION

Layout Design

 The total drawn is 162.52μm by 71.74μm.

- Differential pair: use common centroid

technique.
- Current source: use interdigit technique.

Common centroid technique

Interdigit technique

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAP BGR CONCLUSION

Performance of The Design

 Supply voltage dependence
Run DC simulation with supply voltage varies from 1.1 to 2V at 250C

601mV

599.15mV

Reference voltage with supply voltage from 1.1 to 2V

 Conclusion: The output reference voltage (VREF) varies from 599.15 to 601mV
=> ∆VREF/supply voltage = 1.85mV
=> 𝑃𝑆𝑅𝑅 ≈ −54𝑑𝐵
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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAP BGR CONCLUSION

Performance of The Design

 Temperature dependence
Run DC simulation with temperature varies from -40 to 1050C at 1.2V supply

600.65mV

600.26mV

The curve of reference voltage versus temperature

 Conclusion: The variation is about 0.39mV

=> The temperature coefficient: TC = 4.5ppm.

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAP BGR CONCLUSION

Performance of The Design

Reference voltage versus temperature at different supply voltage
VDD (V) VREF (mV) ∆VREF (mV) TC (ppm)
1.1 600.44 ÷ 601.16 0.72 8.3
1.2 600.26 ÷ 600.65 0.39 4.5
1.3 599.88 ÷ 600.38 0.5 5.7
1.4 599.53 ÷ 600.15 0.62 7.1
1.5 599.25 ÷ 599.94 0.69 7.9
1.6 599 ÷ 599.76 0.76 8.7
1.7 598.82 ÷ 599.6 0.78 9
1.8 598.65 ÷ 599.46 0.81 9.3
1.9 598.5 ÷ 599.33 0.83 9.5
2 598.37 ÷ 599.22 0.85 9.8

 Conclusion: All results of TC in the expected range of VDD are smaller than
10ppm. Thus, the BGR circuit operate well with VDD from 1.1 to 2V.

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAP BGR CONCLUSION

Performance of The Design

 Simulation at different corner

605.85mV 604.7mV

6.3mV 6.5mV

599.55mV 598.2mV

Temperature dependence of VREF curvature Temperature dependence of VREF curvature

at VDD = 1.2V at VDD = 2V

 Conclusion: The variation of reference voltage at different corner vary in

range from 6.3 to 6.5mV, about 1%/ corner (required specification).

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAP BGR CONCLUSION

Comparison of References Performances

Reference [1] [2] [3] This work

Year 2014 2015 2017 2019
Technology 28nm 28nm 0.18 μm 28nm
VREF (mV) 500 600 893 600
Supply voltage (V) 1.1 1.4 ÷ 5 1.1 ÷ 2 1.1 ÷ 2
Current (A) N/A 2.5μ N/A 2.87μ
Power (W) 500μ 3.5μ (at 1.4V) 0.55μ 3.46μ (at 1.2V)
Min.temp. (oC) -40 -40 -30 -40
Max.temp. (oC) 125 105 80 105
TC (ppm) <10 33 19 <10
PSRR (dB) N/A -57 -50 -54
Area 0.086mm2 0.125mm2 0.018mm2 0.012mm2

 Conclusion: This BGR circuit has low TC variation, low power consumption.
1 D. B. a. E. Modica, "Curvature-corrected low-noise sub-bandgap reference in 28 nm CMOS technology," Electronics Letters, vol. 50, no. 5, pp. 396-398, 27th February 2014.
2 F.Neri, T.Brauner, E.D.Mey, "Low-power, Wide Supply Voltage Bandgap Reference Circuit in 28nm CM Bandgap MOS " in 2015 IEEE Jordan Conference on AEECT.
3 Nashiru Alhassan, Zekun Zhou, and Edgar Sánchez-Sinencio, "An All-MOSFET Voltage Reference With -50dB PSR @ 80 MHz for Low Power SoC Design" IEEE Transactions on

Circuits and Systems II: Express Briefs ( Volume: 64 , Issue: 8 , Aug. 2017 ).

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 Overview

Bandgap Voltage Reference Theory

Traditional Sub-bandgap voltage reference

Switched-capacitor Sub-bandgap voltage reference

Conclusion and Future Work

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

How to generate sub-bandgap voltage?

VCTAT Switched-capacitor Bandgap Reference

VREF  1  VBE1   2  VBE

VPTAT
Switched-Capacitor bandgap reference 1

1B. Jiang and J. Feng, "Arbitrary conversion ratio switched-capacitor (SC) networks design for SC bandgap reference," in Electron
Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference, Chengdu, China, 2014
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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

Requirement Specification

Parameter Value
Supply voltage (V) 0.71.8V
Technology process CMOS 28nm
Temperature range (0C) -40  105 0C
VREF(V) 0.6V
Temperature coefficient variation (corner) 3%

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

Top View Of Design

P1 φ1
I VREF
CURRENT CLOCK
SCBGR CORE
SOURCE P2 DOUBLER φ2

OSCILLATOR
The general overall SC Sub-BGR

Block Specification
Current Source Generate Current for Oscillator block, I = 60nA
Oscillator Generate two non-overlapping clock phases, fsw = 150KHz
Clock Doubler Double the swing of two clock phases
SCBGR core Include capacitors and switches, VREF = 0.6V

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

P1 φ1
I0 VREF
CURRENT CLOCK
SCBGR CORE
SOURCE P2 DOUBLER φ2

OSCILLATOR

The general overall SC Sub-BGR

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

Switched-capacitor Bandgap Voltage Core

2x charge pump cell Switched-capacitor network
VEB1
VREF
S1 S2 S2 S2 S2 S2 S1

C4 C5
Q1
1 S1 S1 S1
S2 S2 Ca1 Ca2 Ca3
S1 C C C CLOAD
Vin

S1 S2 S2 S2 S2

C7 C8 VEB2
Q2
N Veb divider Veb multiplier
S2
S1

SC network:
Create reference voltage

Charge pump cell: 𝐂𝐚𝟐

𝐕𝐑𝐄𝐅 = 𝐕 + 𝟑𝚫𝐕𝐄𝐁
Make voltage VEB 𝐂𝐚𝟐 + 𝐂𝐚𝟏 𝐄𝐁𝟏

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

Switched-capacitor Bandgap Voltage Core

Phase 1: V1
VEB1

1 2 VREF
S1 S2 S2 S2 S2 S2 S1

C4 C5
Q1
1 S1 S1 S1
S2 S2 Ca1 Ca2 Ca3
S1 C C C CLOAD

Vin

S1 S2 S2 S2 S2

C7 C8 VEB2
Q2

S2
S1
Node 1: Ca1 and Ca2 are parallel
Q1= (Ca1+Ca2)V1

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

Switched-capacitor Bandgap Voltage Core

VEB1 VEB1
Phase 2: 1 2 VREF
S1 S2 S2 S2 S2 S2 S1

C4 C5
Q1
1 S1 S1 S1
S2 S2 Ca1 Ca2 Ca3
S1 C C C CLOAD

Vin

S1 S2 S2 S2 S2

C7 C8 Q2 VEB2
N
S2
S1
Node 1: Ca1 charge to ground, Ca2 is connected to VEB1
Q1= Ca2 VEB1
The conservation of charge at node 1 between 2 phase
(Ca1+Ca2)V1=Ca2VEB1
𝑪𝒂𝟐
 VCTAT= V1(in phase 1)= 𝑪 𝐕𝐄𝐁𝟏
𝒂𝟐 +𝑪𝒂𝟏
And the charge of Ca3 is the same in 2 phase.
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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

Switched-capacitor Bandgap Voltage Core

𝐂𝐚𝟐
Phase 1: 𝐕𝐑𝐄𝐅 = 𝐕 + 𝟑𝚫𝐕𝐄𝐁
𝐂𝐚𝟐 + 𝐂𝐚𝟏 𝐄𝐁𝟏
VEB1

1 2 VREF
S1 S2 S2 S2 S2 S2 S1

C4 C5
Q1
1 S1 S1 S1
S2 S2 Ca1 Ca2 Ca3
S1 C C C CLOAD

Vin

S1 S2 S2 S2 S2

C7 C8 VEB2
Q2

S2
Node 2: 3 capacitor C transfer from parallel(in phase 2) to
S1 series(in phase 1), we have:
𝐂𝐚𝟐
V2(in phase 1)= VREF = 𝐂 +𝐂 𝐕𝐄𝐁𝟏 + 𝟑𝚫𝐕𝐄𝐁
𝐚𝟐 𝐚𝟏

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

Switched-capacitor Bandgap Voltage Core

VEB1 VEB1 ΔVEB
Phase 2: 1 2 VREF
S1 S2 S2 S2 S2 S2 S1

C4 C5
Q1
1 S1 S1 S1
S2 S2 Ca1 Ca2 Ca3
S1 C C C CLOAD

Vin

S1 S2 S2 S2 S2

C7 C8 Q2 VEB2
N
S2
S1

Node 2: 3 capacitor C are parallel

The top plate of C is connected to VEB1, while the bottom plates of C
are connected to VEB2
 V2(in phase 2) = the voltage across 3 capacitor= VEB1-VEB2 = ΔVEB
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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

Wareform OF VEB & ΔVEB

Vout
S1 S2
Vin IQ
C CL
Q1

S2
S1

VEB ΔVEB
800 150
750 140
700
130
650
600 120

Voltage(mV)
550
Voltage(mV)

110
500
100
450
400 90
350 VEB1 CTAT behavior at -2.05mV/℃
80
300 ∆VEB PTAT voltage at 0.33mV/℃
70
250
200 60
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110
Temperature(℃) Temperature(℃)

VEB1 VEB2 ΔVBE

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

Oscillator & Clock Doubler Design

P1 φ1
I0 VREF
CURRENT CLOCK
SCBGR CORE
SOURCE P2 DOUBLER φ2

OSCILLATOR

The general overall SC Sub-BGR

P1

fsw
P1

P2
P2

Two non-overlapping clock phases Waveform of non-overlapping clocks

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

Oscillator & Clock Doubler Design

 Oscillator circuit
VDD Five-stage Ring Oscillator Frequency of the
IREFP
M4
Ring Oscillator:
I0 Non-overlapping clock I0
IN
M3
RAMP1 RAMP2 RAMP3 RAMP4 OUT
P1 f 
P2
NCVDD
M2

C C C C
IREFN
M1
P2
P1
EN

Two Non-overlapping clock phases

 Clock doubler circuit 1 P1

VDD

A1 M0 A2 M3 P2
LVT X1 LVT X2

VDD
Cd1
VDD
Cd2
X1
P1 A2 P2 A1

X2
X1 X2

M2
X1
M5 𝛗1
X2 φ1 φ2

M1
P2
M4
𝛗𝟐
P1

6.6µs
1 A. Shrivastava et al., "A 32 nW bandgap reference voltage operational from 0.5 V supply for ultra-low power systems," IEEE ISSCC Dig Tech. Papers, Feb. 2015
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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

Oscillator & Clock Doubler Design

 Oscillator circuit Frequency of the
VDD Five-stage Ring Oscillator
Ring Oscillator:
IREFP
M4
I0
I0 Non-overlapping clock f 
IN
M3
RAMP1 RAMP2 RAMP3 RAMP4 OUT
P1
P2
NCVDD
M2

C C C C
IREFN
M1
P2
P1
EN
Two non-overlapping clock phases

430ps
P1 P2
 Clock doubler circuit 1
VDD

A1 M0 A2 M3
LVT X1 LVT X2

Cd1 Cd2
VDD VDD

P1 A2 P2 A1

P2 430ps P1
X1 X2

X1
M2 M5
X2 φ1 φ2

P2
M1 M4
P1

1 A. Shrivastava et al., "A 32 nW bandgap reference voltage operational from 0.5 V supply for ultra-low power systems," IEEE ISSCC Dig Tech. Papers, Feb. 2015
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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

P1 φ1
I0 VREF
CURRENT CLOCK
SCBGR CORE
SOURCE P2 DOUBLER φ2

OSCILLATOR

The general overall SC Sub-BGR

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SWITCHED-CAP BGR CONCLUSION

Current Source Design

Start-up circuit Current source generator

VDD
Current Source generate a
precise current to control
M1 M7
ring oscillator in above.
W W C2
M5 M10 M12
L L
IREFP
M2 M8

M3 M9 Iout
V1 IREFN

M4 W W
M6 M11 M13 KL
L
POR
C1
Rs
Cs

The startup circuit brings out the reference

circuit from a dead (zero current) operating point
to its normal operating point and then is no
longer used once the reference circuit starts
operating properly
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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

Performance of the design

6.6µs
VREF Q1

Q2

VREF
1mV
2ms
Start-up time of reference voltage Ripple of reference voltage

• Start-up time is about 2ms and after start-up time , VREF reaches its operation point, it
is almost constant at the level of 0.6V
 Conclusion: To minimize ripple of VREF:
• Increasing the value of CLOAD, frequency operation of this circuit .
• Tradeoff start-up time and consuming more power.
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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

Performance of the design

Temperature curvature of VREF VREF versus supply voltage at 25°C

VREF @VDD=0.8V VREF @Temp=25℃
610 615

608 610

606 605
VREF(mV)

VREF(mV)
604 600

602
4.1mV
595 13mV
600 590

598 585
-60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Temperature(°C) VDD(V)

 Conclusion:
• The reference voltage variation with temperature is about 4.1mV
• The reference voltage variation with supply voltage is about 13mV
• Satisfying the initial specification (do not exceed 3%).
• This circuit operate from 0.7 to 1.8V to have good performance of VREF

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

Result at different corner

Temperature curvature of VREF VREF versus VDD at 25°C

VREF VREF
@VDD=0.8V @Temp=25℃
620 615

615
610
610
605
605

VREF(mV)
VREF(mV)

600 600

595 16.3mV
595 17mV
590
590
585
580 585
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Temperature(°C) VDD(V)

FF SS TT FS SF FF TT SS FS SF

• The variation is about 16.3mV (2.7%) • The variation is about 17mV

 Conclusion: The result is acceptable, because the variation of VREF is not over 3% .
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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

Physical Design

 Layout of the SC Sub-BGR core for estimate area

This area is about 153µmx167µm

CURRENT SOURCE &
START-UP CIRCUIT
 Current consumption
Current consumption This work
SWITCHED-CAP BGR SCBGR core 380(nA)
CORE Clock Doubler 7.29(nA)
Oscillator 22.39(nA)
Current Source 98.97(nA)
Total 508.65(nA)
OSCILLATOR

CLOCK DOUBLER

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAPBGR
SWITCHED-CAP BGR CONCLUSION

Results and Comparison

 Comparison of references’ performances.  Summary: The result is quite good, but the power is quite
large due to the high leakage current at 28nm node.

Reference [1] [2] [3] This work

Process 130nm 130nm 180nm 28nm
Year 2012 2015 2016 2019
Type VBE VBE VBE VBE
Min.temp (oC) -20 0 -25 -40
Max.temp (oC) 85 80 85 105
VREF (mV) 256 500 240 600
Supply voltage (V) 0.81.55 0.51.5 0.50.9 0.71.8
Power (W) 170n 32n 14.6n 409.4n
Ripple(V) 20m 50u N/A 1m
TC (ppm/°C) 40 75 58 61
PSRR(dB) -50@DC -40@DC -62@DC -40@DC
Area (mm2) 0.07 0.0264 0.07 0.025

1V. Ivanov, R. Brederlow and J. Greber, "An Ultra Low Power Bandgap Operational at Supply from 0.75V," IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1515-1532, July 2012
2 A. Shrivastava et al., "A 32 nW bandgap reference voltage operational from 0.5 V supply for ultra-low power systems," IEEE ISSCC Dig Tech. Papers, Feb. 2015

3Mu Junchao; Liu, Lianxi; Zhu Zhangming; Yang Yintang, “A 58ppm/°C, 40nW BGR at Supply from 0.5V for Energy Harvesting IoT Devices”, 2016
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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAP BGR CONCLUSION

Comparison two architecture

Parameter Traditional BGR SC BGR

Supply voltage (V) 1.1 V to 2V 0.7 to 1.4V
Technology process CMOS 28nm CMOS 28nm
Temperature range (0C) -40 → 1050C -40 → 1000C
Output voltage reference 0.6V 0.6V
Temperature variation 1% (corner) 3%(corner)
Current consumption 2.87µA 350nA
Chip area 162x71 µmxµm 153x167 µmxµm

 Traditional BGR:
• Simple topology in design.
• Small temperature coefficient.
 Switch-capacitor BGR:
• Low power consumption and low supply voltage.

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 OVERVIEW BGR THEORY TRADITIONAL BGR SWITCHED-CAP BGR CONCLUSION

Thank You
For Your Attention!

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