Applications of Feedback: - Oscillators - Phase-Locked Loop

S.
Boyd
EE102
Lecture 15 Applications of feedback
Oscillators Phase-locked loop
151
Oscillators
feedback is widely used in oscillators, which generate sinusoidal signals to generate sinusoidal signal at frequency 0, closed-loop system should have poles at j0 other poles should have negative real part (i.e., other terms decay) closed-loop pole at j0 L(j0) = 1, i.e., L(j0) = 180 + q360, |L(j0)| = 1
intuition: gain around whole loop, including sign, is q360; the feedback regenerates the signal (at frequency 0)
Applications of feedback
152
Example. voltage amplier has gain a, a > 0

PSfrag replacements
vin(t) a
vout (t)
design variables: R, C, a transfer function of RC feedback network is 1 Vin(s) = F (s) = Vout(s) (sRC)3 + 5(sRC)2 + 6(sRC) + 1 loop transfer function is L = aF
Applications of feedback 153
Bode plot of F :
|F (jRC)|
20 40 60 80 2 10
10
10
10
RC
0
F (jRC)
180
PSfrag replacements
360 10
2
10
10
10
RC
want loop transfer function L = aF = 1 at 0 L(j0) = aF (j0) = F (j0) = 180 from Bode phase plot we see 0 2.5/(RC) from Bode magniture plot we see F (0) 30dB, so we need a +30dB
analytically:
L(j0) = 180 is same as 1/L(j0) = 1 (j0RC)3 + 6(j0RC) = 0 a
so 0 =
6/(RC)
a a = , so we need a = 29 hence L(j0) = 2+1 29 5(j 6)

summary: with gain a = 29, system oscillates at freq. 0 = (can check third pole is real & negative)
6/(RC)
in practice, gain needs to be a little larger; nonlinearities limit amplitude of oscillation (careful analysis is hard)
intuitive analysis of RC oscillator: at 0 = 6/(RC), RC network gives 180 loop phase shift
amplifer gain a = 29 makes up for amplitude loss of RC network at 0
156
Phase-locked loop (PLL)

PLL is widely used to synchronize one signal to another applications: synchronize clocks, frequency multiplication/division video signal sync FM demodulation synchronize data communications transmitter, receiver track varying frequency source (e.g., Doppler from space vehicle or aircraft)
157
basic PLL block diagram:

in
Phase detector PSfrag replacements
vphase
Loop lter
osc vout
VCO
signals on left (marked in, osc) are frequency-varying sinusoids, of form cos((t)t); instantaneous frequency (t) varies only a small amount around some xed value signals on right (vphase, vout) are (usually) voltages idea: feedback from phase detector adjusts voltage controlled oscillator (VCO) frequency to match input frequency
Phase detector
phase detector generates voltage proportional to phase dierence of freqeuncy-varying sinusoids
vphase(t) = kdeterr(t)
t
err(t) =
0
(in( ) osc( )) d
provided phase dierence err is less than 90 or so kdet is the detector gain (V/rad)
159
Voltage controlled oscillator

VCO generates frequency-varying sinusoid, with frequency depending on its input voltage vout(t): osc(t) = free + koscvout(t) free is called the free running frequency kosc is the VCO gain (in (rad/sec)/V) real VCOs have a minimum and maximum frequency
1510
LTI analysis of PLL

loop lter is often LTI, i.e., T.F. G(s)
in 1 s err vphase kdet G(s)
PSfrag replacements
osc free
kosc
vout
this LTI model of PLL is good provided |err| 90 (or so)
osc stays within limits

transfer function from free to osc is s s + kdetkoscG(s) which is zero at s = 0, so free does not aect osc (in steady-state) transfer function H from in to osc is H(s) = kdetkoscG(s) kdetkoscG(s)/s = 1 + kdetkoscG(s)/s s + kdetkoscG(s)
phase detector gives integral action: H(0) = 1 for constant in, osc(t) in as t , i.e., VCO frequency locks to input frequency
1512
First order loop
simplest PLL uses G(s) = 1, which yields 1 H(s) = 1 + s/(kdetkosc) (hence the name rst order)
kosckdet is called loop bandwidth osc(t) tracks in(t), with time constant 1/(kdetkosc)
1513
Second order loop

very common PLL uses lowpass loop lter 1 G(s) = 1 + s/loop which yields 1 H(s) = 1 + s/(kdetkosc) + s2/(loopkdetkosc) (hence the name second order) common choices for loop: loop = 4kdetkosc (sets both poles of H to loop/2 = 2kdetkosc) loop = 2kdetkosc (sets poles of H to (1 j)loop/2 = (1 j)kdetkosc) osc is 2nd order lowpass ltered version of in
Phase detectors
basic idea of common phase detector:
v1(t) w1(t)
PSfrag replacements
F (s)
v2(t)
w2(t)
input signals are converted to squarewaves, then multiplied lowpass ltered (averaged) by F (s)
1515
w1(t)
w2(t) PSfrag replacements
w1(t)w2(t)
1516
PSfrag average value replacements
of w1(t)w2(t) depends on phase dierence :
1 w1(t)w2(t) 0 1
180
360
this phase detector operates between 0 and 180 instead of 90; doesnt aect PLL if bandwidth of lowpass lter is w1(t)w2(t) input frequencies, its output
phase detector is linear (plus constant) for 0 180
1517
Lock range
lock range: range of in over which can the PLL can maintain lock recall that we must have |err| < /2 or so for linear phase detector operation transfer function from in free to err: F (s) = 1 s + kdetkoscG(s)
for in constant, we have in steady-state err in free = F (0)(in free) = kdetkoscG(0)
so lock range for slowly varying in is |in free| (/2)kdetkoscG(0)

lock range analysis for rapidly varying in: assume |in(t) free(t)| for all t err = f (in free) where f is impulse response of F by peak-gain analysis, peak of err(t) is no more than
|f ( )| d
so lock occurs for

0
|f ( )| d /2
1519
rst order loop lter (G(s) = 1): F (s) = so

0
1 s + kdetkosc
f (t) = ekdetkosct
1 |f ( )| d = F (0) = kdetkosc
therefore lock range, for rapidly varying in, is (/2)kdetkosc (same as slowly-varying lock range . . . )
1520
PLL: nonlinear analysis

our linear analysis holds as long as phase dierence stays in the linear range (say, 90) frequency stays within VCO limits (usually not the problem) when phase dierence moves out of linear range, dynamics of PLL are highly nonlinear, very complex
analysis of losing and acquiring lock is very dicult there is no complete theory or analysis, but lots of practical experience
1521

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S.

Lecture 15 Applications of feedback

Oscillators Phase-locked loop

Example. voltage amplier has gain a, a > 0

L(j0) = 180 is same as 1/L(j0) = 1 (j0RC)3 + 6(j0RC) = 0 a

a a = , so we need a = 29 hence L(j0) = 2+1 29 5(j 6)

amplifer gain a = 29 makes up for amplitude loss of RC network at 0

Phase-locked loop (PLL)

basic PLL block diagram:

Voltage controlled oscillator

LTI analysis of PLL

this LTI model of PLL is good provided |err| 90 (or so)

osc stays within limits

First order loop

Second order loop

w2(t) PSfrag replacements

PSfrag average value replacements

of w1(t)w2(t) depends on phase dierence :

phase detector is linear (plus constant) for 0 180

for in constant, we have in steady-state err in free = F (0)(in free) = kdetkoscG(0)

so lock range for slowly varying in is |in free| (/2)kdetkoscG(0)

so lock occurs for

rst order loop lter (G(s) = 1): F (s) = so

PLL: nonlinear analysis

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