COMMODORE SEMICONDUCTOR GROUP

commodore
mos technology
NMOS
950 Rittenhouse Rd., Norristown, PA 19403 · Tel.: 215/666-7950 · TWX: 510/660-4168

6545-1 CRT Controller (CRTC)

CONCEPT
The 6545-1 is a CRT Controller intended to provide capability for interfacing the
6500/6800 microprosessor families to CRT or TV-type raster scan displays. A


unique feature is the inclusion of several modes of operation, so that the system
designer can configure the system with a wide assortment of techniques.

FEATURES
· Single +t volt (±5%) power supply. · External light pen capability.
· Alphanumeric and limited graphics · Capable of addressing up to 16K
capabilities. character video display RAM.
· Fully programmable display (rows, · No DMA required.
columns, blanking, etc.). · Pin-compatible with MC6845.
· Non-interlaced scan. · Row/Column or straight-binary
· 50/60Hz operation. addressing for video display RAM.
· Fully programmable cursor. · Internal 8-bit status register.


ORDERING INFORMATION PIN DESIGNATION


MXS 6545-1 1 MHz 

Vss 1 40 VSYNC
MXS 6545A-1 2 MHz /RES 2 39 HSYNC
LPEN 3 38 RA0
CC0/MA0 4 37 RA1
CC1/MA1 5 36 RA2
CC2/MA2 6 35 RA3
CC3/MA3 7 34 RA4

CC4/MA4 8 33 DB0
CC5/MA5 9 32 DB1
CC6/MA6 10 6545-1

31 DB2
CC7/MA7 11 30 DB3
CR0/MA8 12 29 DB4
CR1/MA9 13 28 DB5
PACKAGE DESIGNATOR CR2/MA10 14 27 DB6
C = CERAMIC CR3/MA11 15 26 DB7

P = PLASTIC CR4/MA12 16 25 /CS
CR5/MA13 17 24 RS
Display Enable 18 23 phi2
CURSOR 19 22 R/W
Vcc 20 21 CCLK

6545 CRTC SHEET 1 / 12

COMMODORE SEMICONDUCTOR GROUP


MAXIMUM RATINGS COMMENT
 
Supply Voltage, Vcc -0.3V to +7.0V 
Stresses above those listed under "Absolute
Input/Output Voltage, Vin
-0.3V to +7.0v 
Maximum Ratings" may cause permanent
Operating Temperature, Top
0˚C to 70˚C damage to the device. These are stress ratings

Storage Temperature, Tstg -55˚C to 150˚C only. Functional operation of this device at these



or any other conditions above those indicated in

All inputs contain protection circuitry to prevent the operational sections of this specification is not
damage due to high static discharge. Care implied and exposure to absolute maximum
 
should be exercised to prevent unnecessary 
rating conditions for extended periods may affect

application of voltages in excess of the allowable device reliability.
limits.

ELECTRICAL CHARACTERISTICS (Vcc = 5.0V ± 5%, TA = 0-70˚C, unless otherwise noted)

Symbol
 Characteristic Min.
 Max.
 Unit


Vih
 Input High Voltage 2.0
 Vcc
 V


Vil
 Input Low Voltage -0.3 0.8
 V


Input
 leakage current

Iin
 (phi2, R/W, /RES, /CS, RS, LPEN, CCLK) - 2.5
 µA

 Three-State Input leakage (DB0-7)

Itsi - 10.0
 µA
Vin = 4V to 2.4V


Output High Voltage
Voh Iload = 205µA (DB0-7) 2.4 Vcc
 V
Iload = 100µA (all others)


Output Low Voltage 
Vol Iload = 1.6mA Vss 0.4 V

Pd Power Dissipation - 1000

 mW

Input

Capacitance 
Cin phi2, R/W, /RES, /CS, RS, LPEN, CCLK - 10.0
 pf

DB0-7 - 12.5
 pf

 
Cout Output Capacitance - 10.0
 pf


Vcc
 Vss
INTERFACE DIAGRAM
MPU 1/F DB0-7 HSYNC
VSYNC
DISPLAY ENABLE
phi2 6545-1 CRTC
R/W CURSOR
/CS LPEN
RS ! CCLK
/RES

(REFRESH RAM) MA0-13

 RA0-4
 (CHARACTER ROM)

6545 CRTC SHEET 2 / 12

COMMODORE SEMICONDUCTOR GROUP

MPU BUS INTERFACE CHARACTERISTICS

WRITE CYCLE

Tcyc

Tc

phi2
"$ #$%$ &$'$ ($)$ *$+$ ,$"$ # Tacw
 Tcah "$ #$%$ &$'$ ($)$ *$+$ ,$"$ #$%$ &$'$ ($)$ *$+$ ,$"$ #$%$ &$'$ ($)$ *$+$ ,$"$ #$"$ #$%$ &
"$
"$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$## "$
"$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$"$ "$#$ #$%$ %$&&
$#$
""$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$## $#$
""$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$"$ "$#$ #$%$ %$&&
/CS, RS "$
"$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$## "$
"$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$"$ "$#$ #$%$ %$&&

Twcw
- Tcwh
-

R/W

"$ #$%$ &$'$ ($)$ *$+$ ,$"$ #$%$ &$'$ ($)$ *$+$ ,$"$ #$%$ &$'$ ($)) Tdcw
 Thw
. "$ #$%$ &$'$ ($)$ *$+$ ,$"$ #$%$ &$'$ ($)$ *$+$ ,$"$ #$%$ &$'$ ($)$ *$+$ ,$"$ #$"$ #
"$
"$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$%$ %$&$ &$'$ '$($ ($) "$
"$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$"$ "$##
DATA BUS $#$
""$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$%$ %$&$ &$'$ '$($ ($)) $#$
""$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$"$ "$##
"$
"$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$%$ %$&$ &$'$ '$($ ($)) "$
"$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$%$ %$&$ &$'$ '$($ ($)$ )$*$ *$+$ +$,$ ,$"$ "$#$ #$"$ "$##

/
WRITE TIMING CHARACTERISTICS
(Vcc = 5.0 ±5%, Ta = 0 to 70˚C, unless otherwise noted)
6545-1
0 6545A-1
1

Symbol
 Characteristic Min.
 Max.
 Min.
 Max.
 Unit


Tcyc
 Cycle Time 1.0 40 0.5 40
 µs
5

Tc phi2 Pulse Width 470 - 235

4 - ns

Tacw
 Address Set-Up Time 180
2 - 90
 - ns

Tcah Address Hold Time 0 - 0

 - ns

Twcw
- R/W Set-Up Time 180
2 - 90
 - ns

Tcwh
- R/W Hold Time 0 - 0
 - ns

Tdcw
 Data Bus Set-Up Time 265
3 - 100
 - ns

Thw Data Bus Hold Time 10 - 10

 - ns

(Tr and Tf = 10 to 30 ns)

6545 CRTC SHEET 3 / 12

COMMODORE SEMICONDUCTOR GROUP

MPU BUS INTERFACE CHARACTERISTICS

READ CYCLE

Tcyc

Tc

phi2

6$ 7$8$ 9$:$ ;$<$ =$>$ ?$6$ 7 Tacr Tcar
 6$ 7$8$ 9$:$ ;$<$ =$>$ ?$6$ 7$8$ 9$:$ ;$<$ =$>$ ?$6$ 7$8$ 9$:$ ;$<$ =$>$ ?$6$ 7$6$ 7$8$ 9
6$
6$7$ 7$8$ 8$9$ 9$:$ :$;$ ;$<$ <$=$ =$>$ >$?$ ?$6$ 6$77 6$
6$7$ 7$8$ 8$9$ 9$:$ :$;$ ;$<$ <$=$ =$>$ >$?$ ?$6$ 6$7$ 7$8$ 8$9$ 9$:$ :$;$ ;$<$ <$=$ =$>$ >$?$ ?$6$ 6$7$ 7$8$ 8$9$ 9$:$ :$;$ ;$<$ <$=$ =$>$ >$?$ ?$6$ 6$7$ 7$6$ 6$7$ 7$8$ 8$99
$7$
66$ 7$8$ 8$9$ 9$:$ :$;$ ;$<$ <$=$ =$>$ >$?$ ?$6$ 6$77 $7$
66$ 7$8$ 8$9$ 9$:$ :$;$ ;$<$ <$=$ =$>$ >$?$ ?$6$ 6$7$ 7$8$ 8$9$ 9$:$ :$;$ ;$<$ <$=$ =$>$ >$?$ ?$6$ 6$7$ 7$8$ 8$9$ 9$:$ :$;$ ;$<$ <$=$ =$>$ >$?$ ?$6$ 6$7$ 7$6$ 6$7$ 7$8$ 8$99
/CS, RS 6$
6$7$ 7$8$ 8$9$ 9$:$ :$;$ ;$<$ <$=$ =$>$ >$?$ ?$6$ 6$77 6$
6$7$ 7$8$ 8$9$ 9$:$ :$;$ ;$<$ <$=$ =$>$ >$?$ ?$6$ 6$7$ 7$8$ 8$9$ 9$:$ :$;$ ;$<$ <$=$ =$>$ >$?$ ?$6$ 6$7$ 7$8$ 8$9$ 9$:$ :$;$ ;$<$ <$=$ =$>$ >$?$ ?$6$ 6$7$ 7$6$ 6$7$ 7$8$ 8$99

R/W

Twcr
- Tcdr
6$7$ 8$9$:$;$<$= Thr
.
6$
6$7$ 7$8$8$9$9$:$:$;$;$<$<$==
DATA BUS 66$
$7$ 7$8$8$9$9$:$:$;$;$<$<$==
6$
6$7$8$9$:$;$<$
$
7 $
8 $
9 $
: $
; <$==

Tcda

READ TIMING CHARACTERISTICS

(Vcc = 5.0 ±5%, Ta = 0 to 70˚C, unless otherwise noted)
6545-1
0 6545A-1
1

Symbol
 Characteristic Min.
 Max.
 Min.
 Max.
 Unit


Tcyc
 Cycle Time 1.0 40 0.5 40
 µs
5

Tc phi2 Pulse Width 470 - 235

4 - ns

Tacr Address Set-Up Time 180
2 - 90
 - ns

Tcar
 Address Hold Time 0 - 0
 - ns

Twcr
- R/W Set-Up Time 180
2 - 90
 - ns

Tcdr
 Read Access Time - 340
@ - 150
A ns

Thr
. Read Hold Time 10 - 10
 - ns

Tcda Data Bus Active Time (Invalid Data) 40 - 40

 - ns

(Tr and Tf = 10 to 30 ns)

6545 CRTC SHEET 4 / 12

COMMODORE SEMICONDUCTOR GROUP

MEMORY AND VIDEO INTERFACE CHARACTERISTICS

(Vcc = 5.0 ±5%, Ta = 0 to 70˚C, unless otherwise noted)
Tccy

Output
S Parameter

Tcch


MA0-13
 Tmad
Q

CCLK RA0-4  Trad
M
X Display-Enable Tdtd
B$
B$C$ C$D$ D$E$ E$F$ F$G$ G$H$ H$I$ I$J$ J$K$ K$B$ B$C$ C$D$ D$E$ E$F$ F$G$ G$H$ H$I$ I$J$ J$K$ K$B$ B$C$ C$D$ D$E$ E$F$ F$G$ G$H$ H$I$ I$J$ J$K$ K$B$ B$C$ C$B$ B$C$ C$D$ D$E$ E$F$ F$G$ G$H$ H$I$ I$J$ J$K$ K$B$ B$C$ C$D$ D$E$ E$FF HSYNC Thsd
OUTPUTS B$
B$C$ C$D$ D$E$ E$F$ F$G$ G$H$ H$I$ I$J$ J$K$ K$B$ B$C$ C$D$ D$E$ E$F$ F$G$ G$H$ H$I$ I$J$ J$K$ K$B$ B$C$ C$D$ D$E$ E$F$ F$G$ G$H$ H$I$ I$J$ J$K$ K$B$ B$C$ C$B$ B$C$ C$D$ D$E$ E$F$ F$G$ G$H$ H$I$ I$J$ J$K$ K$B$ B$C$ C$D$ D$E$ E$FF
BB$
$C$ C$D$ D$E$ E$F$ F$G$ G$H$ H$I$ I$J$ J$K$ K$B$ B$C$ C$D$ D$E$ E$F$ F$G$ G$H$ H$I$ I$J$ J$K$ K$B$ B$C$ C$D$ D$E$ E$F$ F$G$ G$H$ H$I$ I$J$ J$K$ K$B$ B$C$ C$B$ B$C$ C$D$ D$E$ E$F$ F$G$ G$H$ H$I$ I$J$ J$K$ K$B$ B$C$ C$D$ D$E$ E$FF
VSYNC
P Tvsd
R 
(SEE TABLE) CURSOR Tcdd
SYSTEM TIMING

N
SYSTEM TIMING CHARACTERISTICS
(Vcc = 5.0 ±5%, Ta = 0 to 70˚C, unless otherwise noted)
6545-1
0 6545A-1
1

Symbol
 Characteristic Min.
 Max.
 Min.
 Max.
 Unit


Tccy
 Character Clock Cycle Time 0.40 40 0.40 40
 µs
5

Tcch
 Character Clock Pulse Width 200
 - 200
 - ns

Tmad MA0-13 Propagation Delay - 300

 - 300
 ns

Trad RA0-4 Propagation Delay - 300
 - 300
 ns

Tdtd Display Enable Propagation Delay - 375
O - 375
O ns

Thsd HSYNC Propagation Delay - 375

O - 375
O ns

Tvsd VSYNC Propagation Delay - 375 - 375 ns

Tcdd CURSOR Propagation Delay - 375 - 375 ns


Tlph LPEN Hold Time 100
 - 100
 - ns

Tlp1 LPEN Set-Up Time 20 - 20
 - ns

Tlp2 CCLK to LPEN Delay 0 - 0
 - ns

Ts, Tf = 20 ns (max)

LIGHT PEN STROBE TIMING DEFINITIONS

CCLK
  
Tlp2 B$C$D$E$F$G$H$I$J$K$B$C$D$E$F$G$H Tlp1 Tlph
B$
B$C$ C$D$ D$E$ E$F$ F$G$ G$H$ H$I$ I$J$ J$K$ K$B$ B$C$ C$D$ D$E$ E$F$ F$G$ G$HHH
B$ C$ D$ E$ F$ G$ H$ I$ J$ K$ B$ C$ D$ E$ F$ G$
LPEN B$
B$C$ C$D$ D$E$ E$F$ F$G$ G$H$ H$I$ I$J$ J$K$ K$B$ B$C$ C$D$ D$E$ E$F$ F$G$ G$HH
B$C$D$E$F$G$H$I$J$K$B$C$D$E$F$G$H 
SEE NOTE

MA0-13 n n+
L 1 n L+ 2

NOTE:"Safe"

time position for LPEN positive edge to cause address n+2
to load into Light Pen Register. Tlp2 and Tlp1 are time positions
causing uncertain results.

6545 CRTC SHEET 5 / 12

COMMODORE SEMICONDUCTOR GROUP

MPU INTERFACE SIGNAL DESCRIPTION CURSOR

T The CURSOR signal is an active-high output and
phi2 - (Clock)
is used to indicate when the scan coincodes with
The input clock is the system phi2 clock and is the programmed cursor position. The cursor
U
used to trigger all data transfers between the position may be programmed to be any character in

system microprosessor and the 6545-1. the address field. Furthermore, within the character,
R/W - (Read/Write) the cursor may be programmed to be any block of
scan lines, since the start scan line and the end
The R/W signal is generated by the scan line are both programmable. The CURSOR
microprosessor and is used to control the direction position may be delayed by one character time by

of data transfer. A high on the R/W pin allows the setting bit 5 of R8 to a "1".

prosessor to read the data supplied by the 6545-1;

a low on the R/W pin allows a write to the 6545-1. LPEN
RS - (Register Select) The LPEN signal is an edge-sensitive input and is
used to load the internal Light Pen Register with the
The Register Select input is used to access contents of the Refresh Scan Counter at the time
internal registers. A low on this pin permits writes the active adge occurs. The active adge of LPEN is
into the Address Register and reads from Status the low-to-high transition.

Register. The contents of the Address Register is
the identity of the register accessed when RS is /RES - Reset Input
.high.
The /RES signal is an active-low input used to
V initialize all internal scan counter circuits. When
/CS - (Chip Select) !
/RES is low, all internal counters are stopped and

The Chip Select input is normally connected to cleared, all scan and video outputs are low, and
the prosessor address bus either directly or through control registers are unaffected. /RES must stay

a decoder. The 6545-1 is selected when /CS is low. low for at least one CCLK period. All scan timing is
W initiated when /RES goes high. In this way, /RES
DB0-7 - (Data Bus)
can be used to synchronize display frame timing

The DB0-7 pins are the eight data lines used for with line frequency.
transfer of data between the prosessor and the
36545-1. These lines are bi-directional and are MEMORY ADDRESS SIGNAL DESCRIPTION
normally high-impedance except during read cycles
-when chip is selected. MA0-13 - (Refresh RAM Address Lines)
These signals are active-high outputs and are
VIDEO INTERFACE SIGNAL DESCRIPTION used to address the Refresh RAM for character
storage and display operations. The starting scan
HSYNC - (Horizontal Sync) address is fully programmable and the ending scan
address is determined by the total number of

The HSYNC signal is an active-high output used characters displayed, which is also programmable,

to determine the horizontal position of displayed in terms of character/line and lines/frame.
test. It may drive a CRT monitor directly or may be
U There are two selectable address modes for
used for composite video generation. HSYNC time
 MA0-13:
position and width are fully programmable.
X In the Straight Binary Mode, characters are stored
VSYNC - (Vertical Sync) in successive memory locations. Thus, the software
The VSYNC signal is an active-high output used must be designed so that row and column character

to determine the vertical position of displayed text. co-ordinates are translated into
Y
Like HSYNC, VSYNC may be used to drive CRT sequentially-numbered addresses. In the
monitor or composite video generation circuits. Row/Column Mode MA0-7 become column
VSYNC position and width are both fully addresses CC0-CC7 and MA8-13 become row
 addresses CR0-5. In this case, the software can
programmable.
manipulate characters in terms of row and column
DISPLAY ENABLE locations, but additional address compression
The DISPLAY ENABLE signal is an active-high circuits are needed to convert the CC0-7 and
 CR0-5 addresses into a memory efficient binary
output and is used to indicate when the 6545-1 is
Z address scheme.
generating active display information. The number

of horizontal displayed characters and the number RA0-4 - (Raster Address Lines)

of vertical displayed characters are both fully
 These signals are active-high outputs and are
programmable and together are used to generate
DISPLAY ENABLE signal. Display Enable can be used to select each raster scan within an individual
 character row. The number of raster scan lines is

delayed by one character time by setting bit 4 of R8
to a "1". programmable and determines the character
height, including spaces between character rows.

6545 CRTC SHEET 6 / 12

COMMODORE SEMICONDUCTOR GROUP

DESCRIPTION OF INTERNAL REGISTERS


Figure 1 illustrates the format of a typical video Horizontal Total (R0)
q
display and is necessary to understand the This 8-bit register contains the total of displayed
functions of the various 6545-1 internal registers. and non-displayed character, minus one, per
Figure 2 illustrates vertical and horizontal timing. horizontal line. The frequency of HSYNC is thus
Figure 3 summarizes the internal registers and determined by this register.
indicates their address selection and read/write
capabilities.
Horizontal Displayed (R1)
This 8-bit register contains the number of
Address Register
displayed characters per horizontal line.

This is a 5-bit register which is used as a "pointer"
to direct 6545-1 data transfer to and from the Horizontal Sync Position (R2)


system MPU. Its contents is the number of the
desired register (0-31). When RS is low, the this This 8-bit register contains the position of the
register may be loaded; when RS is high, then the HSYNC on the horizontal line, in terms of the
 character location number on the line. The position
register selected is the one whose identity is stored
in this register. of the HSYNC determines the left-to-right location
of the displayed text on the video screen. In this
r way, the side margins are adjusted.
Status Register
s This register is used to monitor status of the
CRTC, as follows:

7 t
6 u
5 4 3 2 1 v
0

NOT USED w
NOT USED
VERTICAL BLANKING
"0" Scan currently not in vertical
blanking portion of its timing
"1" Scan currently is in its
vertical blanking time.
LPEN REGISTER FULL
"0" This bit goes to "0" whenever
either register R16 or R17 is
x read by the MPU
"1" This bit goes to "1" whenever
a LPEN strobe occurs

HOR TOTAL
y
HOR DISPLAYED
d e f g h i j k l m n o y
A B C D E F G H I J K L o SCAN
p LINES
M N O P
VERT DISPLAYED

{ [$\$]$^$_$`$a$b$c
[$
[$ \$]$ ^$_$ `$a$ b$cc
[$\$ \$]$ ]$^$ ^$_$ _$`$ `$a$ a$b$ |
VERT TOTAL

b$c
[$
[$\$]$^$_$`$a$b$
$
\ $
] $
^ $
_ $
` $
a b$cc y NUMBER OF
[$
[$ \$ ]$ ^$ _$ `$ a$ b$cc f SCAN LINES PER
[$\$]$^$_$`$a$b$
$
\ $
] $
^ $
_ $
` $
a b$c CHARACTER
ROW

z
VERT
TOTAL
ADJUST

Figure 1. Video Display Format

6545 CRTC SHEET 7 / 12

 1 COMPLETE FIELD (VERTICAL TOTAL)

~
VERTICAL DISPLAYED

DISPLAY
ENABLE

HSYNC
COMMODORE SEMICONDUCTOR GROUP

VSYNC

RA0-4


Figure 2. Vertical and

6545 CRTC
}
1 COMPLETE SCAN LINE (HORIZONTAL TOTAL)
HORIZONTAL DISPLAYED
CCLK

Horizontal Timing
DISPLAY
ENABLE

HSYNC

MA0-13

RA0-4

SHEET 8 / 12
COMMODORE SEMICONDUCTOR GROUP

Horizontal and Vertical SYNC Widths (R3) Control of those parameters allows the 6545-1 to
This 8-bit register contains the widths of both be interfaced to a variety of CRT monitors, since
HSYNC and VSYNC, as follows: the HSYNC and VSYNC timing signals may be
accommodated without the use of external one-shot
timing.
€ 

7 t
6 u
5 4 3 2 ‚
1 v
0
Vertical Total (R4)
The Vertical Total Register is a 7-bit register

8 7 t
6 u
5 4 3 2 1 containing the total number of character rows in a
frame, minus one. This register, along with R5,
VSYNC ƒ WIDTH* HSYNC WIDTH determines the overall frame rate, which should be
close to the line frequency to ensure flicker-free
„ „ appearance. If the frame time is adjusted to be
… (NUMBER OF SCAN †(NUMBER OF CHARACTER longer than the period of the line frequency, then
LINES) CLOCK TIMES) !
/RES may be used to provide absolute
‡* IF BITS 4-7 ARE ALL "0", THEN VSYNC WILL
BE 16 SCAN LINES WIDE synchronism.


Address Reg 
Address Reg
‘
Reg.
‹ Œ   ˜ ™ š › ‹ Œ  
‰
/CS Š
RS Ž 0
4 3 2 1 No.’ ‘ Name
Register • Info
Stored RD WD Ž 0
7 6 5 4 3 2 1
œ œ œ œ œ œ œ œ
‚
1 - - - - - - - X X X X X X X X
” œ œ œ € 
v
0 v
0 - - - - - - Address reg. Reg. No. —
yes X X X a4 a3 a2 a1 a0
 œ œ œ œ œ
v
0 v
0 - - - - - - Status Reg. —
yes w L
U  V X X X X X
–
v
0 ‚
1 v 0
0 v 0
v 0
v 0
v “
R0 Horiz. Total # Charac. —
yes · · · · · · · ·
–
v
0 ‚
1 v 0
0 v 0
v 0
v 1
‚ “
R1 Horiz. Displayed # Charac. —
yes · · · · · · · ·
–
v
0 ‚
1 v 0
0 v 0
v 1
‚ 0
v “
R2 Horiz. Sync Position # Charac. —
yes · · · · · · · ·
–
v
0 1 v 0
0 v 0
v 1 1 R3 VSYNC, HSYNC Widths #Scan Lines & #Char. Times —
yes v3 v2 v1 v0 h3 h2 h1 h0
–
v
0 1 v 0
0 v 1 0
v 0
v R4 Vert. Total # Charac. Row —
yes X · · · · · · ·
–
v
0 1 v 0
0 v 1 0
v 1 R5 Vert. Total Adjust. # Scan Lines —
yes X X X · · · · ·
–
v
0 1 v 0
0 v 1 1 0
v R6 Vert. Displayed # Charac. Rows —
yes X · · · · · · ·
–
v
0 1 v 0
0 v 1 1 1 R7 Vert. Sync Position # Charac. Rows —
yes X · · · · · · ·

v
0 1 v 1 0
0 v 0
v 0
v R8 Mode Control —
yes · · · · · · · ·
–
v
0 1 v 1 0
0 v 0
v 1 R9 Scan Line # Scan Lines —
yes X X X · · · · ·
œ
v
0 ‚
1 v 1
0 ‚ 0
v 1
‚ 0
v ‚
R10 Cursor Start Scan Line No. —
yes X b1 b0 · · · · ·
œ œ œ
v
0 ‚
1 v 1
0 ‚ 0
v 1
‚ 1
‚ ‚
R11 Cursor End Scan Line No. —
yes X X X · · · · ·
œ œ
v
0 ‚
1 v 1
0 ‚ 1
‚ 0
v 0
v ‚
R12 Display Start Addr (H) —
yes X X · · · · · ·

v
0 ‚
1 v 1
0 ‚ 1
‚ 0
v 1
‚ ‚
R13 Display Start Addr (L) —
yes · · · · · · · ·
œ œ
v
0 ‚
1 v 1
0 ‚ 1
‚ 1
‚ 0
v ‚
R14 Cursor Position (H) —
yes —
yes X X · · · · · ·

v
0 ‚
1 v 1
0 ‚ 1
‚ 1
‚ 1
‚ ‚
R15 Cursor Position (L) —
yes —
yes · · · · · · · ·
œ œ
v
0 ‚
1 ‚ 0
1 v 0
v 0
v 0
v ‚
R16 Light Pen Reg. (H) —
yes X X · · · · · ·

v
0 1 v 0
1 0 v 0
v 1 R17 Light Pen Reg. (L) —
yes · · · · · · · ·

Notes · Designates binary bit

X ž Designates unused bit. Reading this bit is always "0", except for R31, which
does not drive the data bus at all, and for /CS "1" which operates likewise.

Figure 3. Internal Register

ˆ Summary

6545 CRTC SHEET 9 / 12

COMMODORE SEMICONDUCTOR GROUP

X
Vertical Total Adjust (R5) Cursor Start (R10) and Cursor End (R11)
The Vertical Total Adjust Register is a 5-bit write These 5-bit registers select the starting and

only register containing the number of additional ending scan lines for the cursor. In addition, bits 5

scan lines needed to complete an entire frame scan and 6 of R10 are used to select the cursor mode,

q
and is intended as a fine adjustment for the video as follow:
frame time.

BIT
Vertical Displayed (R6) CURSOR
© MODE
This 7-bit register contains the number of 36 A5


displayed character rows in each frame. In this way,
the vertical size of the displayed text is determined. 0 0 No Blinking
U
0 1¨ No Cursor
Vertical Sync Position (R7) 1 0 Blink at 1/16 field rate
1¨ 1¨ Blink at 1/32
4 field rate
This 7-bit register is used to select the character

row time at which the VSYNC pulse is desired to


occur and, thus, is used to position the displayed Note that the ability to program both the start and
text in the vertical direction. end scan line for cursor enables either block cursor
or underline to be accommodated. Registers R14
Mode Control (R8) and R15 are used to control the character position
This register is used to select the operating of the cursor over the entire 16K address field.
modes of the 6545-1 and is outlined as follows:
Display Start Address High (R12) and Low (R13)
These registers together comprise a 14-bit
€  register whose contents is the memory address of

7 t
6 u
5 4 3 2 ‚
1 v
0
the first character of the displayed scan (the
character on the top left of the video display, as in
figure 1). Subsequent memory addresses are
Ÿ generated by the 6545-1 as a result of CCLK input
INTERLACE MODE CONTROL
pulses. Scrolling of the display is accomplished by
BIT
£
OPERATION changing R12 and R13 to the memory address
 
1 0 associated with the first character of the desired
¡   ¤ line of text to be displayed first. Entire pages of text
X 0 Non Interlace
¡ Ÿ may be scrolled of changed as well via R12 and
X 1¢ Invalid (Do Not Use)
R13.

Cursor Position High (R14) and Low (R15)

VIDEO DISPLAY RAM ADDRESSING
"0" for straight binary These registers together comprise a 14-bit
"1" for Row/Column
register whose contents is the memory address of
¥
the current cursor position. When the video display
MUST PROGRAM TO "0" scan counter (MAx lines) matches the contents of
this register, and when the scan line counter (RAx
¦ lines) falls within the bounds set by R10 and R11,
DISPLAY ENABLE SKEW
"0" for no delay
"1" to delay Display Enable one
then the CURSOR output becomes active. Bit 5 of
§character time the Mode Control Register (R8) may be used to
†
delay the CURSOR output by a full CCLK time to
CURSOR SKEW
"0" for no delay
accommodate slow access memories.
"1" to delay Cursor one character time

LPEN High (R16) and Low (R17)

¤
NOT USED
These registers together comprise a 14-bit
register whose contents is the light pen strobe
position, in terms of the video display address at
which the strobe accurred. When the LPEN input
r changes from low to high, then, on the next
Scan Line (R9) negative-going edge of CCLK, the contents of the
This 5-bit register contains the number of scan internal scan counter is stored in registers R16 and
lines per character row, including spacing. R17.

6545 CRTC SHEET 10 / 12

COMMODORE SEMICONDUCTOR GROUP

DETAILED DESCRIPTION OF OPERATION

Register Formats the row and column identity of the location must be
Register pairs R12/R13, R14/R15 and R16/R17 converted to its binary address before the memory

are formatted in one of two ways: may be written. The Row/Column mode, on the
other hand, does not need to undergo this
1. Straight binary if register R8, bit 2 is a "0". conversion. However, memory is not used as
efficiently, since the memory addresses are not
2. Row/Column if register R8, bit 2 is a "1". In continuous, but gaps exists. This requires that the
this case the low byte is the Character system be equipped with more memory than is
Column and the high byte is the Character actually used and this extra memory is wasted.
Row. Alternatively, address compression logic may be
employed to translate the Row/Column format into
Figure 4 illustrates the address sequence for the a continuous address block.
Rvideo display control for each mode.
« In this way, the user may select whichever mode is
Note from Figure 4 that the straight-binary mode best for the given application. The trade-offs
has the advantage that all display memory between the modes are software versus hardware.

¬
addresses are stored in a continuous memory Straight-binary mode minimizes hardware
­
block, starting with address 0 and ending at 1919. requirements and Row/Column requires minimum

The disadvantage with this method is that, if it is software.
desired to change a displayed character location,

TOTAL - 90
”
TOTAL - 90 COLUMN ADDRESS (MA0-7)
DISPLAY - 80 DISPLAY - 80
       
0 1¢ ®2 ¯
... ¯
... ²
77 ±
78 ³
79 80 81 ¯
... ³
89 0 1¢ ®2 ¯
... ¯
... ²
77 ±
78 ³
79 80 81 ¯
... ³
89
 
80 81 ®
82 ¯
... ¯
... ¶
157 ¶
158 ¶
159 µ
160 µ
161 ¯
... µ
169 ¶
256 ¶
257 ¶
258 ¯
... ¯
... ´
333 ´
334 ´
335 ´
336 ´
337 ¯
... °
345
 
µ µ µ ¯ ¯ ´ ´ ´ ° ° ¯ ° ¢ ¢ ¢ ¯ ¯ ± ³ ³ ³ ³ ¯
DISPLAY - 24

DISPLAY - 24

160 161 162 ... ... 237 238 239 240 241 ... 249 512 513 514 ... ... 589 590 591 592 593 ... 601
ROW ADDRESS (MA8-13)

· · · · · ·

· · · · · ·
TOTAL - 34

TOTAL - 34

· · · · · ·
¸ ¸ }
 
µ 1761
1760 µ 1762
µ ¯
... ¯ 1837
... ´ 1838
´ 1839
´ 1840
° 1841
° ¯ 1849
... ° ´ 5633
5632 ´ 5634
´ ¯
... ¯ 5709 5710 5711 5712 5713 ...¯ 5721
... ®

1840 1841 1842 ... ... 1917 1918 1919 1920 1921 ... 1929 ± 5889
5888 ± 5890
³ ... µ 5966
... 5965 µ 5967
µ 5968
µ 5969
µ ... 5977
     
1920 1921 1922 ... ³ 1998
... 1997 ³ 1999
³ 2000 2001 ... 2009 6144 6145 6146 ... ´
... 6221 6222 6223 6224 6225 ... 6233
           
¯
2000 2001 2002 ... ¯ 2077
... ² 2078
² 2079
² 2080
± 2081
± ¯ 2089
... ± ¯
6400 6401 6402 ... ¯ 6477
... ² 6478
² 6479
² 6480
± 6481
± ¯ 6489
... ±

· · · · · ·

° 2641
2640 ° 2642
° ¯
... ¯ 2717 2718 2719 2720
... ® 2721
® ¯ 2729
... ® ° 8449
8448 ° 8450
¶ ¯
... ¯ 8525
... ® 8526
® 8527
® 8528
® 8529
® ¯ 8534
... ´

·
STRAIGHT BINARY ADDRESSING SEQUENCE ¹
ROW/COLUMN ADDRESSING SEQUENCE

Figure 4. Display Address Sequences (with

 Start Address = 0) for 80 * 24 Example

SYSTEM BUS
ÀVSYNC
HSYNC Á
°
6545-1 TO
CRT CONTROLLER †DISPLAY ENABLE †VIDEO
    CURSOR CIRCUITS
MA0-13 RA0-4
ºPIXEL
MPU DISPLAY ADDRESS
½
ADDRESS
¾
BUS
ADDRESS Ÿ
º
MPU
»
CONTENTION
SCAN LINE SHIFT
CONTROL
COUNT ¿
REGISTER

MPU DATA CHARACTER

¾
BUS £
DATA
£
CHARACTER
VIDEO DISPLAY
GENERATOR
RAM
¼
ROM
SCAN LINE
£
DOT PATTERN
Figure 5. Typical System
ª Configuration

6545 CRTC SHEET 11 / 12

COMMODORE SEMICONDUCTOR GROUP

Å
Memory Contention Schemes for memory
Addressing MPU Ö CYCLE MPU Ö CYCLE

Æ
From the diagram of Figure 4, it is clear that both
the 6545-1 and the system MPU must be capable phi2 CLOCK
Ç
È
of addressing the video display memory. The
6545-1 repetitively fetches character information to ×
phi1 ×
phi2
É
generate the video signals in order to keep the VIDEO
Ê DISPLAY 6545-1 MPU 6545-1 MPU
screen display active. The MPU occasionally MEMORY Ô
MA0-13 Õ
ADDRESS Ô
MA0-13 Õ
ADDRESS
Ë ADDRESSES
accesses the memory to change the displayed
information of to read out current data characters.
Figure 6. phi1/phi2 Interleaving
Three ways of resolving this dual-contention
requirements are apparent: Ø
Ì Cursor and Display Enable Skew Control
· MPU Priority
Bits 4 and 5 of the Mode Control register (R8) are
Ó
used to delay the Display Enable and Cursor
In this technique, the address lines to the video Ç
Í outputs, respectively. Figure 7 illustrates the effect
È
display memory are normally driven by the Ç
of the delays.
6545-1 unless the MPU needs access, in which
Î
Æ
case the MPU addresses immediately override
Ï
those from the 6545-1 and the MPU has
immediate access.
CCLK
· Vertical Blanking
Ð (NO DELAY)
Ï
With this approach, the address circuitry is
identical to the case for MPU Priority updates. CURSOR
The only difference is that the Vertical Retrace (WITH Â DELAY)
Ê
Æ
status bit (bit 5 of the Status Register) is used by
the MPU so that access to the video display
Ñ
Æ
memory is only made during vertical blanking DISPLAY (NO DELAY)
time (when bit 5 is a "1"). In this way, no visible ENABLE
Ê POSITIVE
screen perturbations result.
EDGE (WITH DELAY)
Ò
· phi1/phi2 Memory Interleaving
DISPLAY Ã
(NO DELAY)
This method permits both the 6545-1 and the
ENABLE
Æ
MPU access to the video display memory by NEGATIVE
time-sharing via the system phi1 and phi2 clocks. EDGE (WITH DELAY)
During the phi1 portion of each cycle (the time
when phi2 is low), the 6545-1 address outputs
Ë
are gated to the video display memory. In the
Ò Figure 7. Cursor and Display Enable Skew
phi2 time, the MPU address lines are switched in.
In this way, both 6545-1 and the MPU have
Ó
unimpeded access to the memory. Figure 6
illustrates the timings.

Ù
FRAME Ù
FRAME

VERTICAL DISPLAYED VERTICAL BLANKING

DISPLAY ENABLE

VERTICAL BLANKING
STATUS BIT (STATUS "0" - DISPLAY ACTIVE
REGISTER BITS)
SWITCHES STATE AT END OF Ú"1" - VERTICAL
BLANKING
LAST DISPLAYED SCAN LINE ÙACTIVE

Figure 8. Operation of Vertical Blanking Status Bit

COMMODORE SEMICONDUCTOR GROUP reserves the rights to make changes to any products herein to
improve reliability, function or design. COMMODORE SEMICONDUCTOR GROUP does not assume any
liability arising out of the application or use of any product or circuit described herein; neither does it convey any
license under its patent rights nor rights of others.

Ä
Postscript-conversion by Markku Alén - 24.Feb.2001

6545 CRTC SHEET 12 / 12