2680
12, DECEMBER 2005
1.25-Gb/s Burst-Mode Receiver ICs With
Quick Response for PON Systems
Makoto Nakamura, Member, IEEE, Yuki Imai, Member, IEEE, Yohtaro Umeda, Member, IEEE, Jun Endo, and
Yuji Akatsu, Member, IEEE
Abstract—This paper describes burst-mode receiver ICs with
quick response for 1.25-Gb/s optical access networks. In a
point-to-multipoint fiber access system, such as a passive optical
network (PON) system, the receiver should be able to handle
burst-data packets with different amplitudes. In burst-mode
transmission, a receiver with a quick response is desired for high
efficiency in data transmission. In addition, high sensitivity is
also required for such a shared access system. To achieve a quick
response and high sensitivity at the same time, a transimpedance
amplifier (TIA) with three gain modes has been designed. The
use of a hysteresis comparator enables fast gain mode switching.
A limiting amplifier with feed-forward auto-offset compensation
(AOC) is also used for quick response to burst data. These circuit
techniques require no external adjustment. Using these design
techniques, optical receiver ICs were fabricated in SiGe-BiCMOS
technology. The optical receiver built with the ICs exhibits a
settling time of under 20 bits and a sensitivity of 30 dBm with
wide dynamic range of over 26 dB using a p-i-n photodiode (PD)
for burst-mode optical input at 1.25 Gb/s. These fast-response
receiver chips improve the data transmission efficiency. The use of
a conventional p-i-n PD and the freedom from external adjustment
make it possible to build an inexpensive receiver.
Index Terms—Burst-mode receiver, limiting amplifier, optical
receiver, PON system, transimpedance amplifier.
I. INTRODUCTION
C OMMUNICATION traffic, which includes both voice and
image data, is growing rapidly as Internet use expands. To
provide broadband communications, a high-speed access net-
work like fiber-to-the-home (FTTH) is desired. There are two
types of optical wireline access network. One provides point-to-
point communication, which is expensive and mainly used for
leased lines. The other provides point-to-multipoint communi-
cation and is a passive optical network (PON) system [1]–[3]. A
PON is a promising optical subscriber system because it has big
advantages in both data transfer speed and cost. The speed has
been steadily increasing as it has gone from STM-PON to ATM-
PON, Broadband-PON [4], and Gigabit-class PON (GPON) [5],
[6]. In a PON system, a passive optical coupler allows optical
network units (ONUs) to share an expensive optical line terminal
(OLT) as shown in Fig. 1. Such a shared access system has a
large path loss due to the large number of ONU branches. Up-
stream and downstream data are multiplexed using two optical
wavelengths: 1.49 m for the downstream and 1.31 m for the
Manuscript received March 31, 2005; revised July 22, 2005.
The authors are with the NTT Photonics Laboratories, Atsugi-Shi, Kanagawa,
243-0198 Japan (e-mail: nakamura@aecl.ntt.co.jp).
Digital Object Identifier 10.1109/JSSC.2005.856582
0018-9200/$20.00 © 2005 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO.
upstream. In the downstream traffic, data are continuously trans-
mitted. In contrast, the data packets in the upstream traffic have
very different power levels because of the different transmission
distances between the ONUs and the OLT. Hence, one of the key
components is the optical receiver in the OLT.
The receiver in the OLT consists of a photodetector, a trans-
impedance amplifier (TIA), and a limiting amplifier, as shown
in Fig. 1. To handle upstream data packets, the receiver requires
high sensitivity, wide dynamic range, and a quick response to
burst data. To compensate for the shared access loss, the receiver
should have a high sensitivity and a wide dynamic range with
regard to the power of the input signals. In burst-mode trans-
mission, a quick response can improve the efficiency of data
transmission. The data structure of a packet is shown in Fig. 2.
Each packet consists of a preamble, a header, and a payload. The
receiver parameters are set according to the preamble data. To
prevent collisions between packets, the timing of each packet is
controlled and a guard time is inserted between them. The pre-
amble and the guard time are preliminary data. Shortening the
response time makes it possible to reduce the amount of pre-
liminary data, thereby improving the efficiency of data trans-
mission [7]. For fast response, a reset signal is added between
each data packet, as shown in Fig. 2, which helps in shortening
the response speed of the receiver circuit. For access networks,
the cost of the receiver must be low enough for subscriber use.
However, the OLT receivers in GPONs generally use an expen-
sive avalanche photodiode (APD) as a photodetector to obtain
high sensitivity [8].
To meet these requirements, the authors devised circuit de-
sign techniques that enable both quick response and high sen-
sitivity using an inexpensive p-i-n photodiode (PD). These cir-
cuit techniques also eliminate the need for external adjustments.
A burst-mode receiver built with the developed ICs exhibits a
quick response of under 20 bits and a sensitivity of 30 dBm
using a p-i-n PD.
II. PROBLEMS IN CONVENTIONAL CIRCUITS
To obtain a high sensitivity, gigabit-class optical receivers
usually employ an APD as a photodetector. However, such
receivers are very expensive because they require a high-
voltage power supply and complicated multiplication factor
control with adjustments, especially for burst-mode use. In ad-
dition, fast switching of the multiplication factor is difficult.
On the other hand, the p-i-n PD is a very common device and
has a great advantage with regard to cost; however, obtaining a
sensitivity as high as that of a receiver with an APD is difficult.
NAKAMURA et al.: 1.25-Gb/s BURST-MODE RECEIVER ICs WITH QUICK RESPONSE FOR PON SYSTEMS
Fig. 1. PON system and optical receiver for an OLT.
Fig. 2. Data structure in a data packet.
Fig. 3. Problems in conventional receivers for wide input dynamic range.
Moreover, in conventional receivers, several of methods gain
control are used to widen the input dynamic range. Fig. 3 shows
conventional gain control methods and the problems with wide
dynamic range. The main methods employ: 1) control of the
multiplication factor of an APD; 2) control of the feedback resis-
tance; or 3) control of the input current. Since these methods are
usually implemented by means of level detection, it takes a long
time for the receiver operation to settle. All of these methods use
a feedback loop with a level detection circuit. It takes a long time
to capture the received signal level because the average level is
usually used for precise detection. The average level is usually
2681
detected using an RC level-hold circuit whose time constant has
to be long in order to maintain the detected level. In addition,
controlling the multiplication factor is complicated. The mul-
tiplication factor of an APD is controlled by changing its bias
voltage. However, the voltage supply circuit contains a noise
reduction circuit, which has a long time constant, and cannot
be changed quickly. Effecting a fast change to burst data re-
quires complicated control. In the case of input current control,
the control circuit degrades the bandwidth. To draw out excess
current from a PD, the current control circuit is connected to the
input of the TIA. The parasitic capacitance of this control circuit
worsens the bandwidth and degrades the operation performance.
On the other hand, controlling the feedback resistance by means
of diodes provides a quick response but degrades the duty cycle
of the signal. When the TIA receives a large signal current, the
gain can be changed by using a feedback resistor with a diode.
However, the resistance is changed dynamically, and the duty
cycle of the output waveform degrades. These problems with
conventional receivers for GPON systems are summarized in
Table I. Lastly, a conventional receiver requires several adjust-
ments for high sensitivity. An adjustment-free receiver is essen-
tial for low cost.
Based on these considerations, we set our design target to
be the improvement of the sensitivity and response time of a
burst-mode receiver with a p-i-n PD.
2682
TABLE I
PROBLEMS WITH CONVENTIONAL RECEIVERS
Fig. 4. Design approach to improve sensitivity and input dynamic range for a
burst-mode receiver.
III. DESIGN APPROACH
To cope with above-mentioned problems, we used the fol-
lowing design approach in the development of burst-mode re-
ceiver ICs (Fig. 4).
First, to obtain a high sensitivity using a p-i-n PD, we use a
large feedback resistor in the TIA, which reduces thermal noise.
In an optical receiver, the noise generated in a TIA mainly deter-
mines the sensitivity because the TIA is used in the front-end of
the receiver. A TIA with low noise characteristics can improve
the sensitivity. In a TIA, the current noise due to the feedback
resistor is a dominant noise source. The noise current of the
feedback resistor is
(1)
where is Boltzman’s constant and is temperature [9]. Thus,
a large can reduce the noise current and improve sensitivity.
However, it also reduces the frequency bandwidth and limits op-
eration speed. In addition, at large input signal power, it also
degrades linearity and gives rise to signal distortion, which de-
grades the data transmission quality. As a result, the input dy-
namic range is reduced.
Second, to prevent such signal distortion and widen the input
dynamic range, we used gain mode switching in a TIA. As
the input signal current to the TIA increases, the gain mode
is switched from high to low before the output voltage of the
TIA reaches the nonlinear region in amplifier operation. This
gain mode switching ensures operation in the linear region and
avoids waveform distortion. It produces clear signals with little
distortion of signal waveform, thus improving the input over-
load current and widening the input dynamic range.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005
Fig. 5. Relationship between bandwidth f and feedback resistance R as
a parameter of open-loop gain A .
Fig. 6. Block diagram of the developed optical receiver.
Lastly, to improve the response to burst data, we devised re-
ceiver circuits with a fast response. That is, the gain mode of the
TIA changes quickly, and the auto-offset compensation (AOC)
of a limiting amplifier responds quickly. Conventionally, gain
mode switching takes time to detect the power level of the input
signal current of the TIA. To solve this problem, we devised fast
level detection and gain switching circuits for the TIA. In addi-
tion, offset compensation is needed in order to receive an input
signal with level variations, and the receiver amplifier should
remove the offset due to level variations. In burst-mode trans-
mission like that in a PON system, the receiver must handle data
packets whose powers vary widely because of the varying trans-
mission distance from each ONU to an OLT. Hence, it has to be
able to compensate for the offset for each packet and respond
quickly.
Moreover, to widen the bandwidth of a TIA with a large feed-
back resistor, we boost the open-loop gain. When a large feed-
back resistor is used, the input time constant of the TIA mainly
limits its frequency bandwidth. This input time constant is pro-
duced by an input parasitic capacitance and an input resis-
tance . Thus, to obtain a wide bandwidth, the TIA should
have a small input resistance. The frequency bandwidth of a TIA
is represented by
(2)
where is the open-loop gain [10]. This equation shows that
a large can reduce the input resistance and widen the band-
NAKAMURA et al.: 1.25-Gb/s BURST-MODE RECEIVER ICs WITH QUICK RESPONSE FOR PON SYSTEMS 2683

Fig. 7. Circuit block diagram of the TIA.

Fig. 8. Operational principle of gain mode change and internal reset generation.

width. The relationship between the bandwidth and the feed- A. TIA
back resistance as a parameter of the open-loop gain of a TIA A detailed circuit block diagram of the new TIA is shown
is shown in Fig. 5. It indicates that using a large reduces in Fig. 7. The TIA consists of an amplifier core with a vari-
the bandwidth. To achieve a wide bandwidth, we used an active able-feedback resistor controlled by means of a quick level
load to boost the open-loop gain, which provides small input re- detection circuit, a single-to-balance converter, and an output
sistance and widens the bandwidth. buffer. The level detection circuit is configured using compara-
tors with hysteresis characteristics. A large feedback resistor
is used in order to decrease thermal noise in the case of a small
IV. CIRCUIT DESIGN input signal, which results in high sensitivity. To avoid wave-
form distortion and widen the input dynamic range, the feedback
Following this design approach, we developed a TIA IC and a resistor , which comprises three resistors of a large ,a
limiting amplifier IC for a burst-mode receiver. A block diagram medium , and one small , is controlled by the level
of the amplifiers is shown in Fig. 6. The TIA has a variable feed- detection circuit. and are connected with in parallel
back resistor that is controlled by a level-detector circuit. The using MOSFET switches, which are controlled to change gain
limiting amplifier has two-stage amplifiers with feed-forward modes. The operational principle of fast gain mode switching is
AOC. External reset signals are fed into these ICs to initialize shown in Fig. 8. The TIA has three gain modes of high ,
the operation conditions for each data packet. The new circuit middle , and low . The resistance in each gain mode
design techniques for quick response and high sensitivity are is given as
described in the following. (3)
2684
Fig. 9. Circuit diagram of the limiting amplifier. (a) Block diagram of the limiting amplifier. (b) Examples of operational waveforms. (c) AOC circuit.
(5)
As the input signal current to the TIA is increased, the feed-
back resistor is changed from a large resistor to a smaller
one ( or ). To change the gain mode, when the ampli-
tude of the output voltage of the TIA reaches the threshold
voltage , switch SW1 turns “ON” and initiates the first
change from high to middle. After SW1 turns “ON”, SW2 be-
comes available through SW3, which is controlled by SW1. The
second gain mode change, from middle to low, is performed by
SW2. The level detection and switching circuits require no ex-
ternal adjustment, because the differential configuration of the
level detection circuit requires no reference voltage and makes
it possible to easily set the threshold voltage. This leads to stable
operation.
For burst data, fast control of the gain change is essential.
The response speed of the level detection and switching mainly
decides the speed of the gain mode change. Fig. 8(b) illustrates
the principle of quick level detection in the TIA. For high-speed
detection, we use a hysteresis comparator, which enables fast
level detection and hold. The circuit configuration is shown
in Fig. 7. It is based on a Schmitt trigger circuit, in which the
hysteresis voltage is generated by a positive feedback. The hys-
teresis voltage of the comparator is set to the threshold voltage
for the level detection. Once the input signal exceeds
the output is quickly changed to “ON”, because there is no
charge-up circuit, such as a level-hold capacitor. And the level
of the detected signal is maintained due to hysteresis transfer
characteristics. Thus, the level detection circuit can quickly
capture the input signal level and hold it. The comparators used
in the level detection circuit are operated by differential signals
so that the circuit does not require any reference voltages. This
means the TIA can quickly switch the gain without any external
adjustments.
On the other hand, using a large feedback resistor normally
reduces the bandwidth. To obtain wide frequency bandwidth,
we designed the TIA core circuit based on a cascode configura-
tion. The load resistor with an active load, which works in
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005
(4) high-gain mode, is also used. The active load can provide large
open-loop gain and enables us to decrease the input resistance
and broaden the bandwidth. In Fig. 7, represents the active
load in the case of the load resistor. For stable operation in each
gain mode, this load resistance linked with the feedback resis-
tance is also changed. That is, a large resistor is selected when
the feedback resistor is large, whereas a small one is selected
when the feedback resistor is small. This load resistor is also
controlled by switch SW1 and SW2, as is the case with the feed-
back resistor. The cascode configuration can reduce parasitic ca-
pacitance equivalently and boost the frequency bandwidth.
Accordingly, the TIA supplies a quick-gain change with a
high sensitivity and a wide dynamic range at a high-speed oper-
ation. In addition, to ensure stable operation, the TIA also has a
single-to-balance conversion circuit that drives the limiting am-
plifier with differential signals.
B. Limiting Amplifier
For burst-mode operation, the receiver should be able to
handle data packets with different amplitudes corresponding
to various transmission distances. To receive these signals, a
receiver amplifier should eliminate the offset voltage in each
data packet and generate a clear reshaping signal that can be
received in the following digital circuits.
, To achieve a quick response and constant amplitude, we use
a limiting amplifier with feed-forward AOC, which can remove
the offset in each data packet [10], [11]. A circuit block dia-
gram and the operation of the limiting amplifier are shown in
Fig. 9(a) and (b). The limiting amplifier consists of two-stage
amplifiers with feed-forward AOC and a buffer amplifier. In
a conventional limiting amplifier, AOC uses a feedback loop
configuration for stable operation. However, the feedback loop
takes a long time to respond to any change in offset conditions.
On the other hand, the feed-forward configuration provides a
quick response because there is no feedback loop. The circuitry
of the feed-forward AOC is shown in Fig. 9(c). It consists of a
level-hold circuit, which detects the peak level of the received
signal and holds it, and an offset control circuit. The level-hold
NAKAMURA et al.: 1.25-Gb/s BURST-MODE RECEIVER ICs WITH QUICK RESPONSE FOR PON SYSTEMS 2685

Fig. 10. Die photographs of the TIA and LIM ICs. (a) TIA IC. (b) Limiting amplifier IC. Chip sizes are 1.1 mm 2 1 mm and 1 mm 2 1.1 mm, respectively.

circuit consists of a diode and a hold capacitor with a switch. It

detects the maximum level of each differential input data, and
the difference between these detected levels is in proportion to
the offset voltage of the input signal. The control circuit makes
these peak levels the same, and this means the offset voltage be-
tween differential signals becomes zero.
In addition, to improve the accuracy and dynamic range of
offset compensation, the limiting amplifier has a two-stage AOC
configuration. When the input signal is small, coarse AOC op-
eration is performed in the first-stage AOC circuit, and fine
AOC operation is carried out in the second stage. For a large
input signal, the offset voltage is effectively cancelled in the
first-stage AOC circuit. In addition, this AOC circuit enables
high sensitivity without any external adjustments because the
two-stage configuration mitigates the accuracy requirement in
Fig. 11. Frequency response in the three gain modes of the TIA IC.
the level-hold operation.
In this circuit, an external reset signal to the AOC is added
V. EXPERIMENTAL AND RESULTS
between each data packet to initialize level detection and the
condition of offset compensation for each packet. This reset A. IC Fabrication
signal can quickly discharge the level-hold circuit, which makes Using these circuit design techniques, we fabricated TIA
a quick response possible. The reset circuit in the limiting am- and limiting amplifier ICs using 0.25- m SiGe-BiCMOS tech-
plifier receives the reset signal and reshapes it. The reset signal nology. Microphotographs of the TIA and limiting amplifier
can also remove the offset due to the extinction ratio of input ICs are shown in Fig. 10(a) and (b), respectively. The die size
optical signals. In the above manner, high-speed and wide-dy- is 1.1 mm 1.0 mm for the TIA IC, and 1.0 mm 1.1 mm for
namic range offset cancellation with small duty cycle variation the limiting amplifier IC. The supply voltages for both ICs are
in the output signal can be obtained without external adjustment. 3.3 V. The power dissipation of the TIA IC is about 150 mW,
For stable operation at a data rate of 1.25 Gb/s, a differen- and that of the limiting amplifier IC is about 150 mW, excluding
tial interface with 50- impedance matching is used between the output load current.
TIA and limiting amplifier circuits. The electrical output inter-
face of the limiting amplifier is differential low-voltage pos- B. TIA IC Performance
itive emitter-coupled logic (LVPECL). Consequently, the de- To verify that the gain mode of the TIA IC changes as
vised circuit techniques used in the TIA and limiting amplifier planned, the transimpedance gain of the TIA IC was evaluated.
enable a very small settling time and output data with constant Fig. 11 shows the frequency response of transimpedance gain
amplitude. , which was calculated from the measured S-parameters
2686
Fig. 12. Output waveforms of the receiver for each gain mode operated using
0
1.25-Gb/s PRBS data. (a) High-gain mode (at optical input power of 30 dBm).
0 0
(b) Middle-gain mode (at 24 dBm). (c) Low-gain mode (at 10 dBm).
in consideration of an input parasitic capacitance and induc-
tance. The S-parameters were measured using three different
input-signal currents, which correspond to each gain mode.
These results show that the TIA IC has high-, middle-, and
low-gain modes for the three different input signal currents.
The IC can change the voltage gain by over 30 dB, and the
gain is 96 dB with a frequency bandwidth of 860 MHz in the
high-gain mode. These results demonstrate that the gain mode
of the TIA IC changes properly and that the bandwidth is large
enough for 1.25-Gb/s operation.
C. Optical Receiver Performance
To assess the response speed and sensitivity, we evaluated the
receiver performance using optical input signals. A low-noise
signal source is needed for the evaluation because our target
sensitivity is very high. An optical signal source can provide
a clear signal with small noise. Thus, the TIA IC was connected
to a p-i-n PD with a responsivity of about 0.9 A/W and a par-
asitic capacitance of about 0.3 pF. The receiver was built with
this TIA IC with a p-i-n PD and the limiting amplifier IC. It was
operated using a 1.25-Gb/s pseudo-random bit stream (PRBS)
and performance was evaluated using burst-mode optical input
data. Fig. 12 shows the output waveforms of the receiver in the
high-, middle-, and low-gain modes at optical input powers of
30, 24, and 10 dBm, respectively, with an extinction ratio
of 10 dB. These results demonstrate that the receiver can gen-
erate signals with clear eye opening at a small input signal of
30 dBm and respond properly in all gain modes.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005
Fig. 13. Measured waveforms for 1.25-Gb/s burst data with different powers.
Fig. 14. Response to burst data in BER.
To demonstrate the burst response, the response waveform
for burst data was evaluated. An example of the receiver output
waveforms for data packets with different amplitudes is shown
in Fig. 13. The top waveform is an optical input signal and
the bottom one is the receiver output. The optical input power
of the first packet is 6 dBm and that of the second one is
30 dBm with a guard time of 32 bits. The receiver generated a
clear reshaped signal with constant amplitude. The output wave-
form also shows that the settling time for the second packet is
very short. These results demonstrate that the receiver responds
quickly to burst data and generates constant output amplitude
for an input optical signal with extremely different powers. We
also evaluated the response speed in consideration of gain mode
switching. The measured response to burst data in bit error rate
(BER) is shown in Fig. 14. The vertical axis is the BER and
the horizontal axis is the starting bit of the error count in a data
packet. This starting bit corresponds to the settling time in the
receiver. From these results, it is clear that the receiver achieves
a fast settling time of under 10 bits at a BER of 10 in the
high-gain mode. Even when the gain mode is changed, the set-
tling time is under 20 bits. In the high-gain mode, the response
speed is mainly governed by the AOC speed in the limiting
amplifier because a gain mode change does not occur in this
mode. On the other hand, in the middle- and low-gain modes,
the speed is governed not only by the AOC response but also by
NAKAMURA et al.: 1.25-Gb/s BURST-MODE RECEIVER ICs WITH QUICK RESPONSE FOR PON SYSTEMS
Fig. 15. Comparison of the sensitivities in burst-mode receivers for PON systems.
TABLE II
PERFORMANCE SUMMARY
the gain-switching speed in the TIA. This response speed satis-
fies both the International Telecommunications Union Telecom-
munication Standardization Sector (ITU-T) and IEEE specifi-
cations [IEEE 802.3ah (gigabit Ethernet PON, GE-PON) and
ITU-T G984.2 (GPON)] [5], [6]. The GPON specification is a
settling time of under 44 bits and the GE-PON specification is
one of under 500 bits. These results confirm that the receiver can
respond quickly to burst data even if the gain mode is changed.
The BER performance was also evaluated, and it was found
that the receiver exhibits a high sensitivity of 30 dBm and an
input dynamic range of over 26 dB at a BER of 10 for the
GPON specification, in which the extinction ratio of the input
optical signal is 10 dB. The sensitivities of burst-mode receivers
for PON systems are shown in Fig. 15. The sensitivity becomes
worse as the data rate increases. This is due to the thermal noise
of the feedback resistor in the TIA, which limits the sensitivity.
In a conventional circuit, as the data rate increases, the feed-
back resistance becomes small to enlarge the frequency band-
width. The devised circuit techniques make it possible to im-
prove the sensitivity compared with conventional ones [7], [10],
[12]–[14]. The measurement results also reveal that the sensi-
tivity of the developed receiver with a p-i-n PD is as high as that
of one with an APD for burst-mode use [8]. In addition, the re-
ceiver also exhibits a sensitivity of 29 dBm at a BER of 10
for the GE-PON specification, in which the extinction ratio of
2687
the input optical signal is 6 dB. The receiver satisfies both the
GPON Class C and GE-PON PX20 specifications, which are
the most severe specifications with regard to sensitivity. The
key performance data are summarized in Table II. The supply
voltage is 3.3 V, and the power dissipation is about 300 mW,
excluding the output load current. The receiver exhibits a high
sensitivity of 30 dBm and a wide dynamic range of over 26 dB
at 1.25 Gb/s. It also achieves a fast settling time of less than
20 bits when the gain changes. The electrical interface of the
receiver is differential LVPECL.
VI. CONCLUSION
Burst-mode optical receiver ICs with a quick response for
gigabit-class PON systems have been developed. To achieve a
quick response and high sensitivity at the same time, the au-
thors have devised a TIA circuit with three-gain modes that
employs hysteresis comparators and a limiting amplifier cir-
cuit with feed-forward AOC. In the TIA, gain mode switching
enables to achieve a high sensitivity and wide dynamic range.
Moreover, a level detection circuit using hysteresis comparators
reduces the response time in gain mode switching. The feed-for-
ward AOC provides a quick response to high-speed burst data
without external adjustments.
Using the proposed design techniques, the authors fabricated
burst-mode receiver ICs. An optical receiver built with these
ICs and a p-i-n photodiode exhibits a quick response and a
high sensitivity for burst data. Its sensitivity is comparable to
that of a receiver with an APD. Further, the performance is
good enough to satisfy both GPON and GE-PON specifications.
These burst-mode receiver ICs with fast response will be very
useful in improving the transmission efficiency of burst-mode
optical communication systems.
ACKNOWLEDGMENT
The authors would like to thank M. Tobayashi, Y. Urabe,
H. Iiduka, and M. Endoh for their useful discussions and help
with the design and experiments, M. Suzuki for his useful sug-
gestions, and H. Toba and H. Itoh for their encouragement.
2688
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Makoto Nakamura (M’92) was born in Gifu, Japan,
in 1964. He received the B.S., M.S., and Dr.Eng.
degrees in electronics engineering from Nagoya
University, Nagoya, Japan, in 1987, 1989, and 1998,
respectively.
In 1989, he joined LSI Laboratories, Nippon
Telegraph and Telephone Corporation (NTT), Kana-
gawa, Japan. Since then, he has been engaged in
the research and development of timing large-scale
integration (LSIs) and broadband amplifiers for
10 Gb/s and more high-speed optical transmission
systems and burst-mode transceiver LSIs for optical access networks. From
2000 to 2002, he worked at NTT Electronics Corporation, where he was
developing LSIs and modules for optical communications. He is currently a
Senior Research Engineer with NTT Photonics Laboratories, Kanagawa, Japan.
Dr. Nakamura is a member of the IEEE Solid-State Circuits Society, the In-
stitute of Electronics, Information and Communication Engineers (IEICE) of
Japan, and the Institute of Electrical Engineers (IEE) of Japan.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005
Yuki Imai (M’92) was born in Tokyo, Japan, in
1955. He received the B.S., M.E., and Dr.Eng.
degrees in applied physics from Waseda University,
Tokyo, Japan, in 1977, 1979, and 1991, respectively.
In 1979, he joined the NTT Electrical Commu-
nication Laboratories, where he was engaged in
the research of microwave GaAs and InP MESFET
fabrication technologies, low-current GaAs MMIC
design for mobile communications, and high-speed
GaAs IC design for 10-Gb/s and 40-Gb/s lightwave
communications. He is currently with the NTT
Electronics Corporation, Tokyo, Japan.
Yohtaro Umeda (M’89) was born in Kanagawa,
Japan, on September 1, 1957. He received the B.S.
and M.S. degrees in physics and the Ph.D. degree in
electrical engineering from the University of Tokyo,
Tokyo, Japan, in 1982, 1984, and 2000, respectively.
In 1984, he joined Nippon Telegraph and Tele-
phone (NTT) Corporation. He is currently with NTT
Photonics Laboratories, Kanagawa, Japan, where
he is engaged in the study of high-speed analog and
digital ICs for fiber-optic communication systems.
Dr. Umeda is a member of the Institute of Elec-
tronics, Information and Communication Engineers (IEICE), Japan.
Jun Endo received the B.E. and M.E. degrees in ap-
plied physics from Tohoku University, Sendai, Japan,
in 1997 and 1999, respectively.
In 1999, he joined the NTT Photonics Laborato-
ries, Atsugi, Japan, where he has been engaged in the
research and development of optical receiver circuits.
Yuji Akatsu (M’95) received the B.E., M.E., and
Ph.D. degrees from Hokkaido University, Sapporo,
Japan, in 1983, 1985, and 1988, respectively.
In 1988, he joined the NTT Opto-electronics Labo-
ratories, where he was engaged in research and devel-
opment on semiconductor crystal growth, optoelec-
tronic integrated circuits, and optical modules. He is
currently a Senior Research Engineer and Supervisor
with NTT Photonics Laboratories, NTT Corporation,
Kanagawa, Japan.
Dr. Akatsu is a member of the IEEE Lasers and
Electro-Optics Society.