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  • Ece2003: Digital Logic Design: Lab Da-2

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    Tanya Gupta
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    This document describes a lab experiment on digital logic design involving full subtractors and 2's complement subtraction. It includes the schematic, truth table, and outputs for a 3-bit full subtractor and 2's complement subtractor circuit. The student learned how full adders can be used to implement subtraction circuits and verified the output using truth tables. Full and 2's complement subtractors are important building blocks for more complex digital logic circuits.

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    This document describes a lab experiment on digital logic design involving full subtractors and 2's complement subtraction. It includes the schematic, truth table, and outputs for a 3-bit full subtractor and 2's complement subtractor circuit. The student learned how full adders can be used to implement subtraction circuits and verified the output using truth tables. Full and 2's complement subtractors are important building blocks for more complex digital logic circuits.

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    6 views11 pages

    Ece2003: Digital Logic Design: Lab Da-2

    Uploaded by

    Tanya Gupta
    This document describes a lab experiment on digital logic design involving full subtractors and 2's complement subtraction. It includes the schematic, truth table, and outputs for a 3-bit full subtractor and 2's complement subtractor circuit. The student learned how full adders can be used to implement subtraction circuits and verified the output using truth tables. Full and 2's complement subtractors are important building blocks for more complex digital logic circuits.

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    of 11

    ECE2003: DIGITAL LOGIC DESIGN

    LAB DA-2

    Name-Tanya Gupta
    Reg No- 20BEC0740
    Full subtractor
    Logic circuit for Full Subtractor

    SCHEMATIC
    1st OUTPUT

    V(a) =1 V(b)=1 V(c)=1 V(diff)=1 V(borrow)=1

    2nd OUTPUT

    V(a) =1 V(b)=1 V(c)=0 V(diff)=0 V(borrow)=0


    3rd OUTPUT

    V(a) =0 V(b)=1 V(c)=0 V(diff)=1 V(borrow)=1


    2’s complement Subtractor

    THEORY
    TRUTH TABLE

    A0 B0 A1 B1 A2 B2 S2 S1 S0

    0 0 0 0 0 0 0 0 0

    1 0 0 0 0 0 0 0 1

    0 1 0 0 0 0 1 1 1

    1 1 0 0 0 0 0 0 0

    0 0 1 0 0 0 0 1 0

    1 0 1 0 0 0 0 1 1

    0 1 1 0 0 0 0 0 1

    1 1 1 0 0 0 0 1 0

    0 0 0 1 0 0 1 1 0

    1 0 0 1 0 0 1 1 1

    0 1 0 1 0 0 1 0 1

    1 1 0 1 0 0 1 1 0

    0 0 1 1 0 0 0 0 0

    1 0 1 1 0 0 0 0 1

    0 1 1 1 0 0 1 1 1

    1 1 1 1 0 0 0 0 0

    0 0 0 0 1 0 1 0 0

    1 0 0 0 1 0 1 0 1

    0 1 0 0 1 0 0 1 1

    1 1 0 0 1 0 1 0 0

    0 0 1 0 1 0 1 1 0

    1 0 1 0 1 0 1 1 1

    0 1 1 0 1 0 1 0 1

    1 1 1 0 1 0 1 1 0

    0 0 0 1 1 0 0 1 0

    1 0 0 1 1 0 0 1 1

    0 1 0 1 1 0 0 0 1

    1 1 0 1 1 0 0 1 0

    0 0 1 1 1 0 1 0 0
    1 0 1 1 1 0 1 0 1

    0 1 1 1 1 0 0 1 1

    1 1 1 1 1 0 1 0 0

    0 0 0 0 0 1 1 0 0

    1 0 0 0 0 1 1 0 1

    0 1 0 0 0 1 0 1 1

    1 1 0 0 0 1 1 0 0

    0 0 1 0 0 1 1 1 0

    1 0 1 0 0 1 1 1 1

    0 1 1 0 0 1 1 0 1

    1 1 1 0 0 1 1 1 0

    0 0 0 1 0 1 0 1 0

    1 0 0 1 0 1 0 1 1

    0 1 0 1 0 1 0 0 1

    1 1 0 1 0 1 0 1 0

    0 0 1 1 0 1 1 0 0

    1 0 1 1 0 1 1 0 1

    0 1 1 1 0 1 0 1 1

    1 1 1 1 0 1 1 0 0

    0 0 0 0 1 1 0 0 0

    1 0 0 0 1 1 0 0 1

    0 1 0 0 1 1 1 1 1

    1 1 0 0 1 1 0 0 0

    0 0 1 0 1 1 0 1 0

    1 0 1 0 1 1 0 1 1

    0 1 1 0 1 1 0 0 1

    1 1 1 0 1 1 0 1 0

    0 0 0 1 1 1 1 1 0
    1 0 0 1 1 1 1 1 1

    0 1 0 1 1 1 1 0 1

    1 1 0 1 1 1 1 1 0

    0 0 1 1 1 1 0 0 0

    1 0 1 1 1 1 0 0 1

    0 1 1 1 1 1 1 1 1

    1 1 1 1 1 1 0 0 0

    SCHEMATIC
    1st OUTPUT

    V(ao)=1 V(bo)=1 V(a1)=0 V(b1)=0 V(a2)=0 V(b2)=1 V(so)=0 V(s1)=0 V(s2)=0

    2nd OUTPUT

    V(ao)=1 V(bo)=0 V(a1)=1 V(b1)=1 V(a2)=1 V(b2)=0 V(so)=1 V(s1)=0 V(s2)=1


    3rd OUTPUT

    V(ao)=1 V(bo)=1 V(a1)=0 V(b1)=0 V(a2)=1 V(b2)=0 V(so)=0 V(s1)=0 V(s2)=1

    INFERENCE

    • We have learnt the working of Full Subtractor and 2’S compliment subtractor. We learnt how to
    use full adder to design and implement different circuits.Expressions for output can be made via
    kmaps.

    • These are combinational logic circuits that perform binary subtractions . We also verified output
    via truth tables. These subtractor circuits are building blocks for more complex and advanced
    circuits.

    • The 2’S compliment subtractor for n bit values can be made using n full adders. The 2’S
    compliment subtractor performs subtraction by 2’s compliment method for 3 bit values.

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