Microsyst Technol (2010) 16:863–870
DOI 10.1007/s00542-010-1035-7
TECHNICAL PAPER
Shallow and deep dry etching of silicon using ICP cryogenic
reactive ion etching process
Ü. Sökmen • A. Stranz • S. Fündling •
S. Merzsch • R. Neumann • H.-H. Wehmann •
E. Peiner • A. Waag
Received: 31 July 2009 / Accepted: 19 January 2010 / Published online: 5 February 2010

Springer-Verlag 2010
Abstract We achieved to etch nanostructures as well as
structures with high aspect ratios in silicon using an
inductively coupled plasma cryogenic deep reactive ion
etching process. We etched cantilevers, submicron diame-
ter pillars, membranes and deep structures in silicon with
etch rates between 13 nm/min and 4 lm/min. These
structures find applications as templates for metal organic
vapour phase epitaxial growth of GaN-based nanostruc-
tures for optoelectronic devices or they are the basic con-
stituents of a nanoparticle balance in the subnanogram
range and of a thermoelectric generator.
1 Introduction
The latest developments in the ‘‘nano-world’’ move the
geometry of structures in Nano- and Micro-Electro-
Mechanical-Systems (NMEMS), which are very often
based on silicon, to ever decreasing dimensions and,
beyond this, more attention is put on the etch profile con-
trol. Thus, the requirements for an etching system are the
following:
• During the etching of nanostructures in silicon the
underetching should be minimized. Low underetching
means high stability and functionality for the nano-
structures in silicon.
Ü. Sökmen (&)
A. Stranz
S. Fündling
S. Merzsch

R. Neumann
H.-H. Wehmann
E. Peiner
A. Waag
Institute of Semiconductor Technology, Braunschweig
University of Technology, Hans-Sommer-Str. 66,
38106 Brunswick, Germany
e-mail: u.soekmen@tu-bs.de
• In addition, the smoothness of the surfaces is also a
critical parameter.
• For shallow etching a very low etch rate is required in
order to control the etch depth, otherwise fast respond-
ing—partly mechanical—components, e.g. source
power, pumps, mass flow controllers, etc., must be
used in order to manage the etch depth.
• For deep etching it is necessary to have high etch rates.
• Using a soft mask even for deep etching will be an
advantage. A soft mask reduces the number of process
steps necessary during the lithography.
All these requirements are fulfilled by inductively
coupled plasma (ICP) cryogenic dry etching of silicon.
Due to the possibility of independent adjusting of ion
density and ion energy not only very low etch rates but
also high etch rates can be achieved using ICP. In contrast
to the Bosch process ICP cryogenic dry etching is a clean
process due to gaseous etch products and passivation
layers that desorb completely during warming up from the
etch temperature to room temperature. The ICP cryogenic
dry etching process of silicon uses two gases, i.e. SF6 and
O2, simultaneously in order to etch cryogenically cooled
silicon substrates. Etching and passivation processes take
place at the same time. We applied this ICP cryogenic dry
etching process to realize nanostructures in silicon, like
submicron pores, nanocantilevers and submicron diameter
pillars with a few micrometer lengths which were defined
by lithography—either conventional photolithography or
e-beam lithography. Patterns of submicron diameter pil-
lars can be used as a growth template for GaN-based
optoelectronic devices. In addition, since they are very
elastic and robust silicon submicron diameter pillars
are designed as lowly heat conducting constituents of
thermoelectric modules. Long and very thin silicon
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cantilevers could also be etched by using the ICP
cryogenic dry etching process. Very deep etching on
larger areas for the creation of membranes is also possi-
ble. Therefore, silicon cantilevers can be realized by dry
etching a membrane from the backside followed by a
cantilever release etch from the front side. In the fol-
lowing sections, we will explain the ICP-deep reactive ion
etching (DRIE) cryogenic dry etching of submicron pores
and cantilevers, submicron diameter pillars and cantilevers
for mass sensing resonators. It is also possible to etch
different structures in bulk silicon other than these men-
tioned structures. Such structures can be used for different
micro- and even nanomechanical applications.
2 Experimental set-up
An SI500C cryogenic dry etcher from Sentech Instru-
ments was used for the ICP cryogenic dry etching pro-
cess. The ion energy and the ion density can be adjusted
independently. The ICP source has a power of up to
1,200 W and the lower electrode can be powered up to
300 W. The ICP source (13.56 MHz) is separated from
the turbo-pumped reactor with an Al2O3-plate, under
which a quartz plate is placed with a few millimeters
gap. The wafer carrier is a plane aluminum plate without
holes. The samples of any size up to 800 wafers are fixed
on it by a thermally conductive paste. This guarantees a
good thermal contact to the Al plate which in turn is
cooled/heated by a He gas foil. This is encapsulated
between the wafer carrier and the electrode which is
temperature-controlled by N2, either as liquid, cold gas
or gas at room temperature and electrical heating. Thus,
during normal operation there will be no He inside the
reactor and the stoichiometry of the gas phase will not be
disturbed. The carrier itself is loaded horizontally by
means of a load-lock system. The mass flow controllers
for SF6 and O2 allow us to use these gases at maximum
flow rates of 129 and 49 sccm, respectively. Throughout
the experiments we used the maximum flow rate of
129 sccm for SF6 and a total pressure of 1.5 Pa. For
oxygen we adjusted the flow rate in small steps, because
the oxygen content influences the cryogenic etch process
severally. Samples of any size below 1 and 2 in. wafers
were normally used for our experiments. We also etched
4 in. wafers. As mask material we used photoresist.
A metal or an oxide mask is not needed because of the
high selectivity of the etching process between photore-
sist and silicon. The depth measurements were done
using a Dektak 3030 profilometer. For imaging we used
a Leica Cambridge S 360 scanning electron microscope
(SEM).
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Microsyst Technol (2010) 16:863–870
3 Results and discussion
3.1 Dry etching of submicron pores and cantilevers
Dry etching of nanostructures requires precise control of
the etch profile. The tolerances for the underetching should
be hold strictly in order not to deteriorate the function of
the structures. The etch rates should be also in submicron-
per-minute range in order to etch submicron depths. The
lowest etch rate that we achieved by reducing the ion
energy and the ion density is about 13 nm/min at cryogenic
temperatures. For this process we have the following rec-
ipe: ICP-source power of 100 W, bias voltage of –1 V,
temperature of –75C and O2 flow of 9 sccm. The etch
profile can be controlled in order to create either perpen-
dicular sidewalls or a cavity, i.e. isotropic profiles. By
increasing the oxygen flow or reducing the temperature we
make the passivation layer, i.e. SiOxFy, thicker and harder
and thus we get positive etch profiles. However, by
reducing the oxygen flow or increasing the temperature we
make the passivation layer thinner and softer and thus we
get negative etch profiles. At room temperature we get
isotropic profiles with etch rates two or three times higher
than 13 nm/min.
3.2 Dry etching of submicron diameter pillars
Dry etching of submicron diameter pillars is different from
dry etching of submicron cantilevers and pores. The sub-
micron diameter pillars have a height of a few micrometers
and thus a high aspect ratio. Therefore, the etch rate should
be high avoiding at the same time underetching. In order to
increase the etch rate, we increased the ion energy and the
ion density. For this process we have the following recipe:
ICP-source power of 500 W, bias voltage of –12 V, tem-
perature of –95C and O2 flow of 9 sccm. We achieved an
etch rate of 2.8–4.0 lm/min. We can also control the etch
profile of the pillars in order to have either perpendicularly,
positively or negatively profiled sidewalls. Increasing the
oxygen content or reducing the temperature will tend the
profile to be positive and reduce also the etch rate.
Reducing the oxygen content or increasing the temperature
will tend the profile to be negative and increase also the
etch rate. Silicon nanowires show strongly reduced thermal
conductivity and can thus be used for thermoelectrics based
on silicon (Hochbaum et al. 2008). Silicon pillars can also
be used as template for GaN-growth in metal organic
vapour phase epitaxial (MOVPE). Due to the reduced
growth area, the growth of GaN will end up with lower
crystal defects (Fündling et al. 2009). Figure 1 shows
submicron diameter pillars with a height of few microm-
eters. The achievable aspect ratio is about 20.
Microsyst Technol (2010) 16:863–870
Fig. 1 a Submicron diameter silicon conical pillars with a diameter
of 200 nm at the top, a spacing of 2 lm and a height of 7.3 lm.
b Submicron diameter silicon cylindrical pillars with a diameter of
700 nm at the top, a spacing of 2 lm and a height of 5 lm
The aspect ratio of the pillars depends not only on their
diameter and height but also on the spacing between the
pillars. Our etching results reveal that if the spacing
between the pillars smaller than the diameter of the pillars
the aspect ratio will decrease due to reduced etch rate. In
this case, the etch profile will be positive with increasing
height. At the point, at which the positive etch profiles
touch each other, the etching of the pillars will stop. If the
spacing between the pillars is very large then the problem
with the loading effect emerges. Due to the loading effect
the etch profiles will be negative. In order to avoid the
loading effect the oxygen content should be increased. By
increasing the oxygen content the passivation layer pro-
tecting the sidewalls will be harder and avoid the loading
effect. In Fig. 2a the pillars have a spacing of 10 lm and a
diagonal spacing of 5 lm. The etch profile begins with
perpendicular sidewalls. By increasing the height of the
865
Fig. 2 a Conical silicon pillars with a top diameter of 5 lm, a
spacing of 10 lm and a height of 80 lm. b Cylindrical silicon pillars
with a diameter of 1.6 lm, a spacing of 12 lm and a height of 27 lm
pillars the etch profile turns to be positive. Nearly in the
last one-fourth of the height the facets touch each other and
the etching stops between the pillars but it survives only on
the large spacing regions, e.g. on the edges of the pillar
arrays. In Fig. 2b the pillars have a spacing of 12 lm and
also a large diagonal spacing of 12 lm. Therefore, a small
loading effect was observed on the etch profile. The etch-
ing survived due to negative profiles and hence the pillars
have a higher aspect ratio.
Actually, only the top of the silicon pillars is used as the
base area during the GaN-growth, therefore the sidewall
profile does not have a crucial role for dry etching. How-
ever, for the thermoelectric generator applications the
sidewall profile plays a great role for the phonon transport.
Therefore, pillars with perpendicular sidewalls, which can
later be thinned by thermal oxidation, are preferred for the
thermoelectric generator applications.
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3.3 Application of silicon pillars in nano-
and microtechnology
Silicon pillars are robust and elastic structures. They break
off only after a strong buckling. Bending the tip of a pillar
down to the bottom will not lead to failure of the pillar, if it
has a high aspect ratio. By bending of the pillars with low
aspect ratios the loaded force will exceed the Young
modulus of elastic silicon and leads to fracture. Figure 3
shows pillars buckled or bended down to the bottom
without fracture. Such submicron diameter pillars can be
used as a potential material for the production of a nano-
particle balance. For instance, silicon pillars having a
diameter of about 400 nm and a height of about 5 lm have
a resonance frequency of about 10 MHz. For the excitation
of the pillars a piezo stack can be used (Tanner et al. 2007).
Loading a mass on the silicon pillars leads to a shift in the
resonance frequency. This shift is correlated to the loaded
Fig. 3 Buckling (a) and bending (b) of a silicon pillar using a
nanoprobe in our scanning electron microscope
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Microsyst Technol (2010) 16:863–870
mass. The mass detection with such pillars is in the
subnanogram range.
Another application of submicron diameter silicon
pillars is thermoelectric modules. Thermoelectric genera-
tors have the ability to convert the thermal energy directly
into electrical energy without using moving parts. In
nature, if a material is a good electrical conductor, it is
also a good thermal conductor. However, the thermo-
electric materials should transport only the electrical
carriers but not the thermal carriers. Therefore, thermo-
electric systems are under development in order to reduce
thermal conductivity while retaining high electrical con-
ductivity. Conventional thermoelectric materials consist
of, e. g. complex ceramics like Ca3Co4O9 (Noudem et al.
2008) and (Zn1-yMg)1-xAlxO (Katsuyama et al. 2002),
whose production is very difficult. Furthermore, the raw
materials are normally rare in the nature. A conventional
material like silicon would be a remedy for this problem.
Reducing the geometrical dimensions of a silicon struc-
ture changes its thermoelectrical properties. It was shown
that the aspect ratio of silicon pillars has a great effect on
the transport of the electrical and thermal carriers.
Increasing the aspect ratio reduces the thermal conduc-
tivity drastically and increases the transport of the elec-
trical carriers (Hochbaum et al. 2008; Boukai et al. 2008).
A thermoelectric generator consists of two parts, i.e. a
thermoelectric material sandwiched between two plates
enduring elevated temperatures. Sapphire can be used as a
plate for high temperature applications. The silicon pillars
should be connected electrically in series and thermally in
parallel in order to increase the output voltage. In order to
attach silicon pillars to the sapphire plate a metal layer
should be deposited on top of the silicon pillars. The
efficiency of the thermoelectric generator depends mostly
also on this joining process, therefore the attachment
should be done properly in order to increase the effi-
ciency. A joining technique, which has been developed at
our institute and is called Low Temperature Joining
Technique, can be used to join the silicon pillars to the
sapphire (Mertens 2004). Silver powder was used between
the sapphire plate and the silicon pillars for our joining
process. The sapphire plate and the silicon pillars were
pressed to each other at low temperature. As a result, the
sapphire plate was joined to one side of the silver layer
and on the other side the silicon pillars were joined by
means of dipping of their tips into the silver layer (Fig. 4)
(Stranz et al. 2008).
A third example to the application of silicon pillars is
the Metal Organic Chemical Vapor Deposition (MOCVD)
growth of GaN nanoLEDs (Fündling et al. 2009). The
growth of GaN on the whole surface of a silicon wafer
leads to a high density of crystallographic defects, which
affects the optoelectronic properties of GaN. However, it is
Microsyst Technol (2010) 16:863–870
Fig. 4 Into silver layer dipped silicon pillars for the application of
thermoelectric generator. Only the tips of the pillars are dipped into
the silver layer during the joining process based on the Low
Temperature Joining Technique
possible to reduce these defects by growing only on con-
fined surface areas. The top surfaces of the silicon pillars
can be used as areas for the growth of GaN. As mentioned
above, silicon pillars are robust and elastic. In addition,
they can endure elevated temperatures without melting
down, i.e. keeping the temperature far below the melting
temperature of silicon, during the growth of GaN. These
advantages of the silicon pillars enable using of silicon as
substrate material instead of sapphire for the GaN growth.
In addition, the GaN layer does not require to be structured
due to the ease of structuring of silicon substrates before
the growth of GaN. These advantages of silicon reduce the
costs of the nano-LEDs production. Figure 5 shows GaN
grown on silicon pillars.
Fig. 5 GaN grown on silicon pillars. The diameter and the height of
the pillars can be varied
867
3.4 Dry etching of cantilevers
The production of cantilevers consists of two processes,
which are back release and front release from silicon
substrate in order to get suspended structures, i.e. cantile-
vers. By back release silicon will be thinned down from the
backside by creating a membrane. By front release the
silicon membrane will be etched through. The front release
of the cantilevers requires perpendicular and smooth
sidewalls in order to keep the dimensions as designed. By
using the ICP-DRIE cryogenic dry etching process canti-
levers with perpendicular and smooth sidewalls can be
etched. We do the back release at -75C and the front
release at -95C. For the front release we have an etch rate
of 3 lm/min. In case of using silicon on insulator (SOI),
before the patterning of the front side with photoresist for
the front release, we remove the oxide layer on the back-
side with HF-dip, i.e. hydrofluoric acid, after the backside
etching down to the oxide layer. After removing the oxide
layer we cover the backside with a thin photoresist film.
The aim in this procedure is to avoid the underetching at
the bottom of the cantilevers. The oxide layer behaves like
an ion scattering center due to its hardness. However, using
photoresist film instead of oxide layer will avoid the
scattering of the ions to the sidewalls. Moreover, the thin
photoresist film avoids the radical attacks to the backside
surface. Otherwise, the radicals will etch the backside
surface. This backside etching leads to an increase in the
temperature of the cantilever. A high temperature deteri-
orates the passivation layer on the sidewalls of the canti-
levers, which leads to begin of the underetching. Another
way to avoid the underetching is to reduce the etch surface
on the front side. Narrow silicon strips around the canti-
lever reduces the attack of the radicals on the backside
surfaces. We etched cantilevers, which require the back
release and the front release, with lengths varying from few
hundreds of micrometers to few millimeters, with widths
varying from few tens of micrometers to few hundreds of
micrometers and with thicknesses varying from few
micrometers to about one hundred micrometers. For the
nanocantilevers we do not do the backside etching, after
the front release we do only HF-dip to remove the oxide
layer in the SOI-wafer under the cantilevers. Due to the
lengths of few tens of nanometers of the cantilevers, the tip
deflection of the cantilevers will not exceed the thickness
of the oxide layer. Hence, there is no sticking to the bottom
during the deflection. The dimensions of a cantilever
should be calculated according to avoid buckling. We
etched cantilevers with a thickness down to 7 lm and a
length of 1 mm, however, with these dimensions the can-
tilevers cannot stay straight. Figure 6 shows an array of
cantilevers on a great membrane area etched from the
backside and the front side.
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Fig. 6 a An array of cantilevers created by back release and front
release applying the ICP-DRIE cryogenic dry etching process.
b Cantilever from this array having the following dimensions:
thickness 70 lm, width 200 lm, length 5 mm and depth of membrane
opening 300 lm
3.5 Dry etching of deep anisotropic structures
The ICP cryogenic dry etching process enables etching of
very deep structures in silicon with perpendicular smooth
surfaces. Compared to wet etching, dry etching does not
depend on the crystallographic planes. Therefore, it is
possible to etch structures with perpendicular sidewalls
without depending on the crystallographic planes. By
reducing the process temperature to very low temperatures,
the dry etching will depend on the crystallographic planes.
The ICP cryogenic dry etching process allows to get a high
selectivity between the photoresist and the silicon. As
photoresist we used S1818 and AZ6632. Using these
photoresists we have a selectivity of 1:100 (photore-
sist:silicon) at -75C. It can also increase to 1:200
depending on the lithography process and the etch tem-
perature. Therefore, a very thin photoresist can also be used
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Microsyst Technol (2010) 16:863–870
Fig. 7 The etch behavior of silicon depending on the etch temper-
ature by using the ICP-DRIE cryogenic dry etching process
in order to etch very deep in silicon. This brings the
advantage of time saving during lithography compared to
processing of a metal mask or an oxide mask.
For deep etching of anisotropic structures we used the
same process parameters as by etching of cantilevers (ICP-
source power of 500 W, bias of –12 V, temperature of
–95C and O2 flow of 9 sccm). The process temperature for
anisotropic etching is not limited to –95C. It is between
–75C and –140C (Fig. 7). At temperatures higher than
–75C the formation of the passivation layer, i.e. SiOxFy,
on the silicon surfaces is disabled. Therefore, -75C is the
highest temperature for our ICP cryogenic dry etching
process. At temperatures between –95C and –140C we
have etching depended on the crystallographic planes.
However, at –95C we can also get perpendicular sidewalls
if we etch not very deep in silicon. At temperatures lower
than –140C the SF6 will begin to condense on the silicon
surface. Therefore, the process temperature should be
higher than -140C. The underetching will be reduced by
reducing the etch temperature between –75C and –95C,
because at lower temperatures the hardness and the thick-
ness of the passivation layer increase.
Another way to reduce the underetching is to adjust the
ion energy. By changing the bias voltage the ion energy
can be adjusted independently from the ion density. The
ICP reactors have the ability to work with low energies
within only few electron voltages (eV). This is an advan-
tage at etching tiny shallow structures with a soft mask.
Using this advantage, low energetic plasma can be used in
order to etch perpendicular smooth sidewalls because low
energetic plasma will not destroy the passivation layer on
the silicon surfaces. However very low ion energy leads to
formation of silicon spikes, i.e. black silicon, due to inad-
equate removal of the passivation layer on the bottom
surfaces (Fig. 8). The ion density is changed by varying the
Microsyst Technol (2010) 16:863–870 869

Fig. 8 The schematic view (not to scale) of the etch behavior of

silicon depending on the ion energy by using the ICP-DRIE cryogenic
dry etching process. a Formation of black silicon due to very low ion
energy, b perpendicular etch profile due to low ion energy,
c underetching and negative etch profile due to high ion energy

ICP-source power. By increasing the ICP-source power the

dissociation of the etching gas will increase, which leads to
generation of more reactive ions in the plasma thus the etch
rate will increase. Low process pressures reduce also the
underetching by reducing the collisions of the ions in the
plasma, thus the number of the directional ions will
increase.
Compared to the SF6 content, the oxygen content is a
critical parameter by cryogenic dry etching. Minute chan-
ges in the oxygen content change also the passivation layer
thickness. Low oxygen content leads to a thin passivation
layer and high oxygen content leads to a thick passivation
layer. The oxygen content changes also the fluorine content
in the plasma by delivering a fluorine atom from the
fluorine containing gas. A thick passivation layer will lead
first to a positive sidewall profile and then to the formation
of silicon spikes, i.e. black silicon, on the surface. Black
silicon has the disadvantage by stopping the etching pro-
cess. By adjusting the main process parameters like the
oxygen content, the process pressure, the process temper-
ature, the bias voltage and the ion density we can etch very
deep structures having smooth and perpendicular sidewalls.
Figure 9 depicts a very deep structure of 120 lm in silicon
with great openings and also a deep etched silicon profile
with narrow structures having a depth of 60 lm. At –75C
we have etch rates up 4 lm/min.
4 Conclusion
We could etch pores, pillars, cantilevers, membrane and
deep structures in silicon by using the ICP-cryogenic dry
etching process. For etching of submicron pores and
Fig. 9 a A very deep etched silicon structure with great etch surface
(depth: 120 lm, mask: oxide). b A deep etched silicon profile with
narrow structures (depth: 60 lm, mask: oxide)
nanocantilevers we developed a very low etch rate of
13 nm/min. The etch rate for the pillars having diameters
of few hundreds of nanometers and height of few
micrometers varies from 2.8 to 4 lm/min. The silicon
pillars can be used as basic elements of GaN nano-LEDs,
of nanoparticle balances and of thermoelectric generators.
For joining a nanopillar array to a sapphire plate, e.g. for a
thermoelectric generator, a low temperature joining process
was developed. We substitute the wet etching with the dry
etching for the membrane fabrication. The membrane
etching has an etch rate of 4 lm/min. The front release of
the cantilevers covered with a thin photoresist film from the
backside has an etch rate of 3 lm/min. With a well
adjusted set of parameters we can etch very deep in bulk
silicon with smooth and perpendicular sidewalls.
Acknowledgments The authors thank the PTB Germany for the
e-lithography of the submicron diameter pillar masks, Sentech
Instruments for the mask design of Fig. 9b, D. Rümmler and N.
Al Mustafa for the technical support. This project is supported in part
by DFG (German Research Foundation).

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