435 Final Project

Analog VLSI Circuit Design

Introduction: R-2R 7-bit Digital to Analog

Converter
For this project, I worked to create a 7-bit DAC. I designed a R-2R DAC using a version similar
to the one that was presented to lecture in class.

Part 1: Schematic
1.1: Schematic Design
The idea of this DAC is to create a resistive network with a ration of 2-to-1. This was
done using 1k and 2k resistors. A set of these represent a bit so 7 sets were used for the 7-bit
DAC. The bit furthest to the left D0 is my Least Significant Bit (LSB).This has the 1k resistor
grounded to the left and to the right it is the next bit. The 7th bit is my Most Significant Bit
(MSB). This is connected to a 5T Operational Amplifier that was previously created in the lab.

Figure1.0 R-2R schematic

Part 1.2: Schematic Test bench
For the test bench ,I created a symbol of the schematic and used a vpulse symbol with a 0-2V
range. I delayed the output of each bit so that I could implement this architecture without using
any switches.

Figure 1.1: schematic test bench

Part 2: Layout
To successfully realize my layout I used subcomponents that were specifically created. These
components are the 1K resistor, the 2k resistor and the OP-amp. These components are
pictured below
1K resistor: Layout & Extracted

Figure 2.0: 1k resistor

2k Resistor: Layout & Extracted

Figure 2.1: 2k resistor

5T_OP AMP: Layout & Schematic

Figure 2.2: 5T_OP_AMP schematic

Figure 2.3: 5T_OP_AMP layout
Figure 2.4: R-2R Layout

Part 3: Tests
To verify my design I first verified that my design passes the LVS test. After that was ensured, I
performed a transient simulation and observed the output to ensure the DAc performed as
intended.

Figure 3.0: LVS result

Figure 3.1 R-2R transient ADEL input

Figure 3.2 R-2R TB output1

Figure 3.3 R-2RTB output2

Conclusion:
For this lab, I was able to successfully implement the 7-bit R-2R DAC. I created the output of
my test bench to be displayed so that each period of an LSB is doubled from least significant to
most significant. I was able to get my layout and schematic to match after struggling a bit. I
chose to implement the application without using switches. This simplified the design and I was
still able to observe the outputs I wanted despite some fluctuations on the output. I didn’t
calculate some of the electrical performance characteristics like the ENOB, the INL, the SFDR
and the THD.