Di Meng & Alain Njipwo

EE 330 Final Project: Physically Unclonable Function

Introduction
For the final project, we have chosen to implement a version of the Physically Unclonable
Function(PUF) Circuit. This can be used to help solve the counterfeiting problem that is occuring
in the semiconductor industry. Our circuit can be coupled to a silicon without affecting it and use
the chip's analog signature as it becomes powered on to serve as the chip’s unique identifier
and authentication parameter. This project will be realised in the 0.18u CMOS process. We
made a couple of assumptions for this implementation. First, the signature of a specific chip
would be in a 32bit format. Second, since we are not bringing this circuit to fabrication and
testing it on actual chips we replicated real world scenarios by using the repeated random
sampling provided by the Monte Carlo testing techniques in the Cadence software.

Overview
Physical unclonable function (PUF) can be considered a “digital fingerprint”, They are creating
unique variations which could occur randomly while people manufacturing semiconductor
devices. The PUF circuit can be used to authenticate silicon chips to prevent the simple
components being sold illegally in the semiconductor industry.

PUF is useful because this small circuit could be added into chips without affecting them, it is
very efficient to identify the semiconductor components. A unique ID for each IC chip will be
created after adding a PUF in this chip. The chance of any two chips having the same ID will be
around zero. In brief, PUF technique is very effective and safe.

There are many types of PUF, for example, Oxide Rupture PUF, Optical PUF, Coating PUF,
Delay PUF, SRAM PUF and so on. The performance of PUFs could be affected by
environmental variations such as supply voltage and temperature.
The hardware properties of a PUF (specification parameters) could include Temperature, Vdd,
Vss, Clk, Select, output, besides Mean value, error rate, variance value, etc.. are also could be
considered.

Design
For the project we are not actually using a chip to obtain it’s physical signature so we
needed to obtain data enlieux of an actual chip’s signature, store the data in a register.
Implement our circuit and run the chip’s signature to authenticate and prove the chip is correct
and our circuit is working as expected. Various components were needed throughout the
project.
To create a complex and top level design, we needed to recreate some of the lower level
components that we used in the lab so that they can be in the GF130nm process instead of the
TSMC180 process.

Inverter
The first component to be recreated was the inverter. This time we used the transistors
Pfet and an Nfet cascaded with a shared input pin Vin. The Pfet connected to Vdd, the Nfet
connected to Vss and the output where they join as shown in figure 1.0. A symbol of the inverter
was created for our next level design. Pfet on the top and Nfet on the bottom, 4 pins were set for
Vdd, Vss, Vin, Out.

Figure 1.0:Schematic of the Inverter

 Figure 1.1: Symbol of Inverter

Fundamental Component
After building inverters, we basically tried to create the fundamental components for our PUF.
We used two inverters with their outputs fed back to each other. Inverter A and inverter B are
connected to the same Vdd and Gnd, and connect the input of inverter A to the output of
inverter B, connect the input of inverter B to inverter A and also set it as a output of this entire
component. Finally, we put 3 pins for Vdd, Gnd and Out. A symbol of this component was
created in the same cell.

Figure 2.0: fundamental component of PUFs

 Figure 2.1:Symbol of fundamental component

32 bit PUF.
Furthermore, we create the 32 - bits PUFs by using the basic component which we have
created, 32 components were used, all the Vdd were connected to the same pin, we also do the
similar connection for ground connection gnd. Besides, all output were set to one pin, in this
way, we have 32 pins for output. A symbol of it was created for our future design.
Figure 3.0: schematic view of a 32-bit PUFs

Figure 3.1: Symbol of 32bit-PUF

32-bit Parallel Input Serial Output Register
After we have done the PUF, we need to build a 32 bits parallel input serial output (piso) register
as the power cycles through all 32 PUFs, they will each initialize to either a 0 or a 1. The parallel
input serial output registers are needed to intake those values, store them and shift them after
every clock cycle.
The register is built by using a D flip-flops to store the output of a single puf and coupled 32
copies of it to store all the 32 outputs from the pufs. The D-Flip Flop itself is comprised of 5
copies of the inverters that we previously created. 4 Pfets ,4 Nfets along with an input, an output
and a clock signal as shown in figure 4.0 below. We proceeded to create a symbol to implement
in the next schematic

Figure 4.0: Schematic view of D- Flip Flop

 Figure 4.1: Symbol of D- Flip Flop

Mux: 2-1
To have the ability to select between two distinct values we needed to created a 2-to-1 mux.
This was achieved by using 2 Pfets, 2Nfets, and inverter. The Inputs A ,B and select S are taken
as pins. The output Y is set as an output pin. We proceed to create a symbol
Figure 5.0: Schematic view of 2-1 Mux

Figure 5.1: Symbol of 2-1 Mux

The final step for the design is to put our 32 - bits PUF and 32 bits register together, The first
output of our PUF goes to the first 2-1 Mux input, and the other input of the first Mux is
connected to a ground. The output of the first D - flip flop is connected to the input of the second
2-1 Mux and the other input of our second 2-1 Mux is connected to the second output of our
PUF. This effectively cascades the results from one register to other. We did similar connection
for the other 30 registers and 2-1 muxes . At the end, the output of the last D- Flip Flop is the
only output of our design. Besides, we connected all Clk, Vdd, and Select to 3 pins. We
proceeded to create a symbol as shown in figure 6.1 that can be used in a test bench to verify
out results.

Figure 6.0: 32-bit puf with all the D flip-flop, 2-1 mux connected
 Figure 6.1: Symbol of final design

Simulations
Throughout our project, we did not independently test the lower level components like
the 2-1 mux, single bit D flip-flop, inverter as we felt we had a good grasp of their architecture
and would test them individually if their implementation at a higher level failed.
When we finished the design of PUF, we used a vpwl source to vdd from the analoglib library as
an input. We gave it the following parameters. Time from 0 to 5 us, and voltage from 0V to 1.6 V.
 Figure 7: 32 bits PUF_ Testbench

For the test, we launched ADE XL and create a view. We created a test from here, loaded the
saved state, the 32 outputs were selected on the design. After that, chose the Monte Carlo
method to simulate and induce randomness in the system. We used the option of Sampling to
plot the MC voltage / current waveforms.

We did couples of test, and collected 3 waveforms from different ramp times 500ns, 1us and
5us to show that the signature of our chip( the 32-bit puf in our case ) can be read and does not
change.
As shown in figure 8, we have all 32 bit inputs bits as signal bits.
 Figure 8 : 32 bits PUF adexl

After we run the Monte Carlo simulation, we get the following graph. The
simulation is ran for a time of 1us and for a voltage from 0V to 1.6 V we can see from the graph,
all the 32 bits from the left side get graphs. They either chose a value of 0 or 1 when the voltage
is applied. This is what creates the unique signature for this chip. For our PUF. The signature we
obtained is
Bits : 0|10 11 12 13 14 15 16 17 18 19 1 20 21 22 23 24 25 26 27 28 29 2 30 31 3 4 5 6 7 8 9
Value: 1 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 1 0 0
 Figure 9 : Time 1uS

As we run the circuit again for a different ramp-up time of 500nS, we observe the same
signature as in 1uS even after the voltage stabilizers.

Figure 10 : Time 500nS

The final test period of our PUF was when it was ran for 5uS. We again observed the same
output enumerated above. Again confirming that the signature of our PUF is unique, does not
change with time and can be used as an identifying characteristic.

Figure 11 : 5us

Our PUF could be confirmed that it works. We also do the test bench for our shift register, we
did 4 bit shift register first. We needed to ensure that the values are being shifted. We
implemented a 4 bit register. Connected the input A of the first 2-1 mux to a vdc source of 1V to
emulate taking the input value of 1. We set every other input value to zero in theory after
running the clock for 4 cycles in the 4 bit register, our value should be cascaded each cycle and
displayed to the output.
 Figure 12 : 4-bit shift register test

In this test bench, we use a pulse voltage for the Clk, Vdd, Select. we set one of inputs of the
first and the third 2-1 Mux to 1.6 V voltage. We mentioned in the schematic, after 4 cycles, the
value A set to 1V that was set as an input should be cascaded and displayed as the output.We
get the waveform confirming that this is in fact the case and our implementation logic for the
register works. This test also serves as an indicator that the lower components like the D
flip-flop, the inverter and the 2-1 mux all work as intended.
 Figure 13 : 4-bit shift register test

Having verified the register works as intended ,we built or the 32 bits shift register. We connect
the clk, select to a source, and give a DC voltage to the Vdd. we also connect couples of the
input to a DC voltage and the rest of are connected to Gnd.

Figure 14: 32-bit Parallel Input Serial Output shift register

The symbol for our 32-bit register was created and used in the test bench below. We again
arbitrarily connected some values to a vdc source of 1V and others to 0V by grounding them.
This emulated taking the input of either 0 or 1 bit.

Figure 14: 32-bit shift register test bench setup

After running the simulation, we can see that our 32-bit test register works as intended as the
values a shifted and serially outputted every cycle so the signature of the chip can be read and
stored.

Figure 15 : 32-bit shift register output

Figure 16: Overall design

DRC AND LVS reports

We could not run a DRC report as we do not have a library for the that can synthesize
our verilog code with the RTL compiler as the GM130nm did not have one.

Conclusion
We have built a 32 bit PUF that latches onto D flip-flops. This takes in 32 bit values and serially
outputs them so that so to minimize the space usage with 1 output gate instead of 32. We have
used Monte Carlo testing to show that our chip’s signature doesn’t change simulated by the
different run times of 1uS, 500nS and 5uS. We have built a 32-bit1 PUF that works as intended