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Service Manual: Viewsonic
Service Manual: Viewsonic
ViewSonic VG511s/VG512s
Model No. VLCDS27955-3W/4W
15” Color TFT LCD Display
ViewSonic 381 Brea Canyon Road, Walnut, California 91789 USA - (800) 888-8583
Copyright
Copyright ¤ 2004 by ViewSonic Corporation. All rights reserved. No part of this publication may be
reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or
computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical,
manual or otherwise, without the prior written permission of ViewSonic Corporation.
Disclaimer
ViewSonic makes no representations or warranties, either expressed or implied, with respect to the
contents hereof and specifically disclaims any warranty of merchantability or fitness for any particular
purpose. Further, ViewSonic reserves the right to revise this publication and to make changes from time
to time in the contents hereof without obligation of ViewSonic to notify any person of such revision or
changes.
Trademarks
Revision History
2. Specification 2
4. Circuit Description 7
5. Adjusting Procedure 8
6. Trouble Shooting Flow Chart 9
Prior to using this manual, please ensure that you have carefully followed all the procedures outlined in the user manual
for this product.
When cleaning, use only a neutral detergent cleaner with a soft damp cloth. Do not spray with liquid or aerosol cleaners.
Do not expose this display to direct sunlight or heat. Hot air may cause damage to the cabinet and other parts.
Adequate ventilation must be maintained to ensure reliable and continued operation and to protect the display from
overheating. Do not block ventilation slots and openings with objects or install the display in a place where
ventilation may be hindered.
Do not install this display near a motor or transformer where strong magnetism is generated. Images on the display
will become distorted and the color irregular.
Do not allow metal pieces or objects of any kind fall into the display from ventilation holes.
Slots and openings in the cabinet and the back or bottom are provided for ventilation, to ensure reliable operation of
the product and to protect it from overheating, those openings muse not be blocked or covered.
The openings should never be blocked by placing the product on a bed, sofa, rug, or other similar surface.
This product should never be placed near or over a radiator or heat register.
This product should not be placed in a built-in installation unless proper ventilation is provided.
This section describes the pin assignment of the LCD’s video connector.
It is called 15 Pin Mini D-sub Connector.
NOTE:
chroma Patten 42
WORKING THEOREM
A. DC-DC CONVERTER
This brick converts the 12V input voltage to 5V for panel use and 3.3V for controller use.
It consists of a PWM IC (AP1501), flywheel Diode (D1), buck choke (L2), and capacitor (C70,71).
Self protection features include a two stage frequency reducing current limit for the output
switch and an over temperature shutdown for complete protection under fault condition.
B. A/D converter
The MST 9030A is a highly integrated TFT LCD controller chip with the latest MST advanced imageprocessing technology
and an integrated ADC/PLL. The MST 9030A has advanced programmable non-linear parametric
cubic based scaling engine with proprietary sharpness adjustment and text enhancement. MST9030A supports both analog
and digital interfaced inputs with an internal ADC/PLL.
The MST9030A has robust handling of a wide variety of TFT LCD panels and strong support of standard
or non-standard input timings.
. Integrated high speed triple 8-bit ADC/PLL support up to 140MHz for XGA-75Hz
. Advanced image processing with proprietary non linear parametric cubic based scaling engineSupport dual interface
with an integrated ADC/PLL
. Robust auto configuration for input mode detection and clock frequency and phase recovery for standard or
nonstandard input timing
. Support video processing with on-chip 2D de-interlacing and color space conversion
. Support programmable Gamma Correction
. GPIO pins for flexible system design
D. MCU:
The MTV312MV64AJ micro-controller is an 8051 CPU core embedded device specially tailored to LCD monitor
applications. It include an 8051 CPU core, 1024-byte SRAM, 14 built-in PWM DACs, VESA DDC interface,
4 channel 6bit A/D converter, a 64 K-byte internal program Flash-ROM .
First, power off the monitor, un-plug the AC cord and be sure the signal cable is
connected(D-sub connected) , then press “2” key at the same time and plug the AC cord to factory.
START
Picture Yes
A
visible?
No
Off Backlight On
on?
(1)Panel no power
Check DC power (2)Panel cable not connected
12V,5V,3.3V,2.5V (3)H/V sync process to panel
,MCU 5V
Check MCU OK
(1)Check Scaler H/V sync correct?
crystal (2)Measure at Scaler side
Check Scaler
Check MCU or
Reprogram MCU
(1)Scaler no power
(2)Scaler changed no OSC
Check Inverter
Backlight off
No Stable Yes No Yes
picture & C after one
second
size correct
No
No
Panel power abnormal
(1)Check OSD
Picture Yes information if mode
over-scaler error
(2)H/V sync input
tolerance too big
Scaler O/P CKT not assembled ok
No
No
No
Incorrect panel type or cable
No
(1)MCU not put well
(2)Crystal bad
Crystal no Yes (3)Cap of crystal
OSC too big/small
No
Yes MCU 5V
=4.75~5.25V
No
No
No
Yes
If input over Not allowed
MCU 5+0.25V
No
MCU bad
Yes Yes
Shadowing Segment for
specific color
No
Check VGA cable
No
(1)Too long?
(2)Quality no good?
Scaler O/P short or
open
Remove adapter
12V ok ? Measure adapter only
Yes
Yes
Remove No Adapter ok
L11/L15/L16/L25 5V ok ?
No
Yes
Change adapter
No Yes
5V ok ? 3.3V/2.5V Yes
ok ?
Measure +12V to
GND
No
+12V->5V +5V short to
regulator CKT no GND or 3.3V MCU 3.3V bad
work
3.3V/2.5V short
to GND
PC 5V/DC 3.3V
CKT not correct
ViewSonic Corporation
Model VG510b/s
DDC (U5) X2
EEPROM U7 OSC
24C21 12MHz
CN2
MCU TO PANEL
U8 MTV312 X1
EEPROM OSC
24C16 12MHz JP1
TO
INVERTER
FROM
QCNWS0905-8028-
A/D ADAPTOR
QCNWS0906-8026A 12V
QCODS1695T8--
CON1 CON1
SW BOARD INVERTER
CON2 RUNTP5475T8---B CON3
DPWBN5570T8----
15” LCD C
PANEL O
N
2 VCC3.3
104
114
126
117
61
35
45
51
11
23
80
92
20
83
95
U1 VCC3.3 VPO
PA[0..7] PA[0..7]
AVDD_DVI
AVDD_PLL
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
AVDD_MPLL
AVDD
VDDC
VDDC
VDDC
VDDC
L1
PA[8..15] PA[8..15] 0805
1
59 106 PA0 C1 C2 C3 C4 C5 C6 C7 C8
4 RIN RIN0 RA0
58 107 PA1 PA[16..23] PA[16..23]
4 GNDR RIN0M RA1
56 108 PA2 10uF/16V 0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF
4 GIN GIN0 RA2
55 109 PA3
2
4 GNDG GIN0M RA3
57 110 PA4
4 SOG SOGIN0 RA4
54 111 PA5 PB[0..7] PB[0..7]
PA[8..15]
4 BIN BIN0 RA5
53 112 PA6
4 GNDB BIN0M RA6
37 113 PA7 PB[8..15] PB[8..15]
4 HSYNC HSYNC0 RA7
4 VSYNC 38 VSYNC0
R1 NC 29 PB[16..23] PB[16..23]
3,4 DDC_CLK DDC1_CLK/GPO8
R2 NC 28 96 PA8
3,4 DDC_DAT DDC1_DAT/GPO7 GA0
PA[16..23]
97 PA9
GA1 PA10 VAA2 VPLL
GA2 98
99 PA11 PC[0..3] PC[0..3]
GA3 PA12 L2A
5 R+ 40 R+ GA4 100 2 VAA2
41 101 PA13 0805
5 R- R- GA5
1
43 102 PA14 C9 C10
5 G+ G+ GA6
44 103 PA15
5 G- G- GA7
46 10uF/16V 0.1uF
5 B+ B+
47
2
5 B- B-
PB[0..7]
48 84 PA16
5 CLK+ CK+ BA0
49 85 PA17
5 CLK- CK- BA1
R3 390/1% 50 86 PA18
VDVI REXT BA2
62 87 PA19
C11A RMID BA3 PA20
BA4 88
C12 0.1uF 63 89 PA21
0.1uF REFP BA5 PA22
BA6 90
R4 0 R5 0 64 91 PA23
PB[8..15]
AVSS BA7
79
MST9030/9035 VAA3 VDVI
NC/GPO0 PB0
78 NC/GPO1 RB0 16
77 17 PB1 L3
NC/GPO2 RB1 2 VAA3
PB[16..23]
76 18 PB2 0805
NC/GPO3 RB2
1
75 19 PB3 C13 C14 C15
NC/GPO4 RB3
PC[0..3]
74 24 PB4 VAA1 VAD
NC/OINV RB4 PB5 10uF/16V 0.1uF0.1uF
73 NC/EINV RB5 25
72 26 PB6 L4
2
NC/OSP RB6 2 VAA1
71 27 PB7 0805
NC/ESP RB7
1
C16 C17 C18
3 CSZ 65 CS
67 6 PB8 10uF/16V 0.1uF0.1uF
3 SCL SCL GB0
66 7 PB9
2
3 SDA SDA GB1
R6 100 32 8 PB10
3 HWRESET HWRESETZ GB2
68 9 PB11
3 INT INT GB3
R7 NC/100 30 12 PB12
3 EEPROM_CLK DDCROM_CLK/GPO6 GB4
R8 NC/100 31 13 PB13
3 EEPROM_DAT DDCROM_DAT/GPO5 GB5
14 PB14
GB6 PB15
GB7 15
2 AdjBACKLITE 69 PWM0
6 A_VOL 70 PWM1
122 PB16
BB0 PB17
BB1 123
C19 22pF 33 124 PB18
XIN BB2 PB19 VCC2.5 VDD
BB3 125
Y1 128 PB20
14.318MHZ BB4 PB21 L5
BB5 1 2 VCC2.5
4 PB22 0805
BB6
1
34 5 PB23 C23 C24 C25 C20 C21
C22 22pF XOUT BB7
10uF/16V 0.1uF0.1uF0.1uF0.1uF
C26 0.1uF 3 120 R132 BEAD(0603) PC0
2
BYPASS OCLK PC1
LDE 121
2 118 PC2 VAA4 VDPLL
AVSS_MPLL
AVSS_MPLL LHSYNC
AVSS_PLL
PC3
AVSS_DVI
AVSS_DVI
LVSYNC 119
L7
2 VAA4
GNDC
GNDC
GNDC
GNDC
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
C27 0805
AVSS
1
C28 C29
NC
10uF/16V 0.1uF
105
115
127
116
60
36
52
39
42
10
22
81
93
21
82
94
2
Title
VG511s/512s
Size Document Number Rev
ViewSonic Corporation Confidential - Do Not Copy VG511s Custom TOP B
25 VG512s Date: Friday, October 17, 2003 Sheet 1 of 7
+12V U4
AC1501-50
VCPU
JP2 DC JACK VIN 4 L2A1 100UH
L8 BEAD(1812) FEEDBACK VCC5V
F1
1 1 2 1 VIN L25 BEAD(0805) L9 BEAD(0805)/NC
C30 C31 C32 C33 3A L2 100UH
VCC5V
ON/OFF
OUTPUT 2
1
C38 C36 L11 BEAD(0805) VCC3.3 VAA1
3
2
GND
1000p 0.1u 180p0.1u C11 U3
100u/16v 470u/16v 3 4
IN VO
1
0.1u R9 VIN C37
1
C39 C39A 0 OHM C40 1 2 C41
5
GND VO
1
D1 L12 NC(1206) C42 100u/16V
470u/16V 0.1u 470u/16v 1084-33CM 47u/16V
2
47u/16V
2
SK24 L13 NC(1206)
2
L14 BEAD(1812) R10 R11 VCC2.5
2
0 OHM NC U4A
L15 BEAD(1206) 3 4
IN VO
1
1 2 C43
L16 BEAD(1206) GND VO
1
C44 1084-25CM 47u/16V
2
47u/16V
2
VAA2 VAA3
JP1
1
C45
2 Q1
L17 BEAD(1206) 100u/16V
1 SI9433DY
2
D 8
1
C46 C47
VIN 2 6 C48 R12
100u/16v S D 100u/16v 680
L19 BEAD(1812) 1 5 0.1u
2
S D
G
C50 24K C51
0.1u
470u/16v 0.1U
4
2
VCC5V
1
R14 10K C52
VCC5V
R15
R16 NC 4.7K 47u/16V
2
5 VCC5V
2 Q2
4 R18 1K R17 1K R19
3 1
NC 3 10K
2
1
R20 NC C POWER GROUND SHOULD CONNECT TO DIGITAL GROUND BY ONE WAY
R21 2K 2 VLCD
CON1 B E 1 Q3
0 OHM 3
Q4 2N3904
2
R22 1 R23 4.7K 2
onBACKLITE 3
R24 C53 2N3904 Q5 U5
to Inverter
1
1
3 3 onPanel 1
NC Q6
2 3 3 IN VO 4
1u 1 R26 4.7K R25 2N3904
1
AdjBACKLITE 1
3 4.7K 1 2
GND VO
1
R27 C54
1
2N3904 NC 1084-33CM C55
10u/16V
47u/16V
2
Audio GND and Power GND are
isolated, not completely
separated
Title
4 TX VCPU VCPU
3 RX VCPU
2
1 R153 0/NC
NC/4K7
3
CON2 LED1 R28 2K 1 Q7
C56 2 MMBT3906
1
R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 MMBT3906 3
From 6pin change to 4pin LED2 R45 2K 1 Q8
10u/16V 2
R46 820
2
4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 R47 820
U6
4
10u/16V C59 C57
1
C58 22pF 11 17 SDA 1
VDD
VDD3
10u/16V C60 .1u X2 P1.0
P1.1 18 SCL 1
1
11.0592MHZ Y2 R48 20
D3 1N4148 P1.2 CSZ 1
21
2
P1.3 HWRESET 1
2 1 1M 22
P1.4 onPanel 2
12 23 LED1
2 C61 22pF X1 P1.5
24 LED2 R49 C62
R50 8.2K P1.6
7 RST P1.7 25 AUDIO_PWR 6
NC/10K NC/47nF CON3
R51 100 RX 29 3 R52 100
1,4 DDC_CLK HSCL/P3.0/RX DA0/P5.0 1
R53 100 TX 28 2 R54 100
1,4 DDC_DAT HSDA/P3.1/TX DA1/P5.1 2
19 1 R55 100
1 INT P3.2/INT0 DA2/P5.2 3
ISDA 13 42 R56 100
ISCL ISDA/P3.4/T0 DA3/P5.3 R57 100 4
14 ISCL/P3.5/T1 DA4/P5.4 41 5
40 R58 100
DA5/P5.5 R59 100 6
36 VBLANK/P4.0 DA6/P5.6 34 7
6 A_STBY 37 HBLANK/P4.1 8
15 26 R60 100
4 ST_DET1 STOUT/P4.2 AD1/P6.1 9
AD0/P6.0 27 10
R61 R62 43 16
HSYNC AD2/P6.2/HLFHI onBACKLITE 2 11
44 VSYNC AD3/P6.3 9
R64 R65 R66 35 30 R150 1K
DA7/HCLAMP DA10/P6.4 HPSENSE 6
VCPU 39 31
HLFHO/DA8 DA11/P6.5 ST_DET2 5
4K7 4K7 38 32
VCPU C63 C64 HALFV/DA9 DA12/P6.6
DA13/P6.7 33
1
4K7 4K7 4K7 5 D4 D5 D6 D7 D8 D9 D10 D11
NC
VSS
100p 100p R133 R134 6
R69 R70 NC R67 R148 R149 R151
MTV312M(PLCC44)
10
R71 R72 5.6V 5.6V 5.6V 5.6V 5.6V 5.6V 5.6V 5.6V
47K 47K
2
100 100 4K7 4K7 0/NC 47K
VCPU
VCPU 4K7 4K7
U7 Let MCU more stable
8 1 VCPU
C66 VCC A0
7 WP A1 2
10u/16V C65 R73 6 3
SCL A2
1
5 SDA GND 4
.1u
0 24LC16/DIP
2
1 EEPROM_DAT
1 EEPROM_CLK DIP/SMD
共Layout
option for
scaler DDC
Title
VG511s/512s
Size Document Number Rev
B MPU -
Date: Friday, October 17, 2003 Sheet of
NC
75 R83 100 C76 .047u
GNDB 1
1
1
D12 D13 D14
1
5.6V 5.6V 5.6V D15 D16 D17
2 VCC5V
1
C77 C78 C79 C80
2
HSYNC 1
0 OHM
C81 NC
R86 2.2K
R89 10K
R91 47K
R90 PC5V
100 VGA_CON R92 100
ST_DET1 3
R93
NC
R94 10K
R95 10K
D20
1
VCC5V
D18 D19 2
C83 C84 U8
5.6V 5.6V 1 8 DDC_5V 1
33P 33P A0 VCC
2 A1 WP 7
3 6 3 PC5V
2
A2 SCL
1
4 5 C85
GND SDA
24C21 C86 10u/16V DAN202U Title
VG511s/512s
2
.1u
Size Document Number Rev
B VGA B
Date: Friday, October 17, 2003 Sheet of
3
R 25
26 R98 10K
G D21
B 27
RGB GND 29
28 R99 10K DAN202U
HSYNC
VSYNC 8
SYNC GND 15
6 DCLK_DDC R100 100
1
DDC SCL DDAT_DDC
DDC SDA 7
14 R101 100
+5V
HPD 16
R102 10K
1/3shield 11
3 R103 1K
2/4shield ST_DET2 3
0/5shield 19
22 R138
clk shield
1
18 C87 C88 R104
DAT0+ D22 D23 D24 D25 U9
DAT0- 17
10 1 8 10K .1u 10u/16V
DAT1+ 5.6V 5.6V 5.6V 5.6V NC VCC 3.9K
9 2 7
2
DAT1- NC VCLK
DAT2+ 2 3 NC SCL 6
1 4 5
2
2
DAT2- GND SDA R139 NC
DAT3+ 13
12 24C21
DAT3-
DAT4+ 5
DAT4- 4
DAT5+ 21 B+ 1
DAT5- 20 B- 1
clk+ 23 G+ 1
clk- 24 G- 1
R+ 1
R- 1
DVI CON
CLK+ 1
CLK- 1
1
1
D26 D27 D28 D29 D30 D31 D32 D33
VCC5V
BAV99 BAV99 BAV99 BAV99 BAV99 BAV99 BAV99 BAV99
2
3
C89
.1u
Title
VG511s/512s
Size Document Number Rev
B DVI_D Input B
Date: Friday, October 17, 2003 Sheet of
FB3 0(0805)
FB4 0(0805)
FB5 0(0805)
GND_AUDIO
Change Package
AUDIO_VIN
R108 1K R105 24K L23 BEAD(DIP)
VCC5V
Q9 R141 0/NC
2
C91 10uF C113 L24 BEAD(1812)
1 R109 4.7K
A_VOL 1
3
1u MMBT3904
C92 0.1uF C
R142 B E
GND_AUDIO
GND_AUDIO U10 SI9435DY
U11 3K JP2A VIN
C119 100uF FB9 8
12 1 D
11 FB10 2
10 3 7 D S 3
C90
9 C95 1uF 4
8 6 D S 2
AAGND 0.1u
7 C96 1uF
6 5 D S 1
R143 10K
5 A_STBY 3
C120 100uF FB11
4 C93 R111
3 GND_AUDIO
G
FB12
2 0.1u 24K
1
4
R144 R145 R146 C114 C115 R147 C121
AN7522 0
2K 2K 1nF 1nF 100K 1uF/0805 20K FB6 102(0603)
R116 AAINL1 R114
VCC5V
20K FB7 102(0603) 4.7K
R121 AAINR1
R118
C116C117 Q10
GND_AUDIO 10K MMBT3904L
1nF 2
AUDIO_VIN R140 NC 1
Q11 3
CN1 PC_Audio R1232K
HPSENSE 3
8 MMBT3904L 2
GND_AUDIO R125 4.7K 1
3 AUDIO_PWR
7 3
2 R127
GND_AUDIO
3 2K/NC
C118
C101 R152 4
470uF/DIP 0.01uF
2K 5
1
1
1 D34 D35 GND_AUDIO GND_AUDIO
GND_AUDIO
GND_AUDIO
GND_AUDIO FB8 102(0603) 3.9V 3.9V
2
GND_AUDIO
2
D36 D37
3.9V 3.9V
1
Title
GND_AUDIO
GND_AUDIO VG511s/512s
Size Document Number Rev
B Audio B
Date: Friday, October 17, 2003 Sheet of
1
PB8 RN9 7 8 33 CP9 7 8 40 3
PB9 OE C108 NC C106 3
5 6 5 6 41 VCC 4 4
PB10 3 4 PBO10 3 4 22PF 42 0.1UF PAO7 5
PB11 PBO11 VCC PAO6 5
1 2 1 2 43 6
2
PB12 RN10 7 33 PBO12 CP10 7 VCC PAO5 6
8 8 44 NC 7 7
PB13 PBO13 0.1u PAO4
PB14
5
3
6
4 PBO14
5
3
6
4 22PF
45 NC PAO3
8
9
8
9
HANNSTAR J2
PB[16..23] PB15 1 2 PBO15 1 2 PAO2 10
PB[16..23] CON6 10
PB16 RN11 7 8 33 STV2 CP11 7 8 GND 11
PB17 CPV PAO15 11
5 6 5 6 1 GND 12 12
PB18 3 4 PBO18 3 4 22PF PAO7 2 PAO14 13
PB19 PBO19 PAO6 BE5 PAO13 13
1 2 1 2 3 BE4 14 14
PB20 RN12 7 8 33 PBO20 CP12 7 8 PAO5 4 PAO12 15
PB21 PBO21 PAO4 BE3 PAO11 15
5 6 5 6 5 BE2 16 16
PB22 3 4 PBO22 3 4 22PF 6 PAO10 17
PB23 PBO23 PAO3 GND 17
1 2 1 2 7 BE1 18 18
PAO2 8 PAO23 19
BE0 PAO22 19
9 NC 20 20
10 PAO21 21
PC[0..3] NC PAO20 21
PC[0..3] GND 11 GND 22 22
PAO15 12 PAO19 23
PC0 R128 33 PCO0 PAO14 GE5 PAO18 23
13 GE4 24 24
PC1 R129 33 PCO1 PAO13 14 25
PC2 R130 33 PCO2 PAO12 GE3 PCO1 25
15 GE2 26 26
PC3 R131 33 PCO3 16 27
PAO11 GND 27
17 GE1 28 28
C109C110C111 C112 PAO10 18 29
GE0 29
19 NC 30 30
20 NC 31 31
21 GND 32 32
33PF33PF33PF33PF PAO23 22 33
PAO22 RE5 33
23 RE4 34 34
PAO21 24 35
PAO20 RE3 35
25 RE2 36 36
PAO19
26
27
GND
RE1
HANNSTAR J1 37
38
37
38
PAO18 28 39
RE0 39
29 NC 40 40
A 30 NC
GND
GND Title
VG511s/512sb
Size Document Number Rev
Custom Panel Output B
Date: Friday, October 17, 2003 Sheet of
Main Board
Thank you in advance for your feedback on our Service Manual,which allows continuous improvement
of our products. We would appreciate your completion of the Assessment Matrix below, for return to
ViewSonic Corporation.
Assessment
A.What do you think about the content after reading VG511s, VG512s Service Manual?
U nit Ex cellent G ood Fair Bad
1. Precautions And Safety Notices
2. Specification
3. Front Panel Function Control Description
4. Circuit Description
5. Adjusting Procedure
6. Trouble Shooting Flow Chart
7. Recommended Spare Parts List
8. Exploded Diagram and Spare Parts List
9. Block Diagram
10. Schematic Diagrams
11. PCB Layout Diagrams
C.Do you have any other opinion or suggestion about this service manual?