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Design Engineering High-Speed Reconfigurable FIR Filter using Russian Peasant

Multiplierwith Sklansky and Han Carlson Adders

Research Proposal · February 2022

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 ISSN: 0011-9342 | Year 2021
Design Engineering Issue: 9 | Pages: 16818-16837

High-Speed Reconfigurable FIR Filter using

Russian Peasant Multiplierwith Sklansky
and Han Carlson Adders
Dr.V.Parthasaradi1, Assistant Professor,
1
Department of Electronics and Communication Engineering,E.G.S Pillay Engineering
College(Autonomous),Nagapattinam.
1
parthasaradi@egspec.org
Dr. A. Sundar Raj2, Associate Professor,
2
Department of Electronics and Communication Engineering,E.G.S Pillay Engineering
College(Autonomous),Nagapattinam.
2
sundarraj.a@egspec.org
Dr. M. Chinnadurai3, Professor& Head,
3
Department of Computer Science and Engineering, E.G.S Pillay Engineering College
(Autonomous), Nagapattinam.
3
mchinnadurai@egspec.org

Abstract:

Reconfigurable FIR filters are typical digital filters that are utilized in multi-standard wireless
communications and digital signal processing. The direct form of the FIR filter, which consumes
more power and area in DSP applications.For this issue,Multiplier Control Signal
Decision(MCSD) window schemes areintegrated withthe FIR filter to dynamically alter the
filter’s order. The traditional reconfigurable FIR filter by using the Russian Peasant Multiplier
willutilize more delay and area because of low adder performance which is applied in the
multiplicationunit. In this study, the design of a modified reconfigurable FIR filter is to minimize
the power, time, and area. In the Russian Peasant Multiplication approach, a Wallace adder is
substituted by carry select adder, along with Sklansky and Han Carlson adders, in the proposed
modified FIR filter.As a result, as compared to the standard Reconfigurable FIR framework with
the Russian Peasant Multiplication technique, a modified FIR filter will consume low delay,
power, and area.

Keywords:FIR filter,MCSD scheme, Modified FIR filter, Han Carlson,Sklansky adder, Russian
peasantmultiplier

1. INTRODUCTION

In the realworld,an analogsignal should be processed hence the information in them

isanalyzed,orconverted to another form, and displayed,which is implemented by a system called

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Digital Signal Processing (DSP). DSPis performing animportant role in modern technological
advancements likevoice prediction,echo cancellation,noise cancellation,etc. So, for reaching
acceptable and quick solutions,filtering methodsshould be implemented for these issues than
common DSP methods. Generally, the filtering operation is widely applied in DSP. A filter is a
system of signal selection,and from a noisy signal which mainly composes of disturbances, a
filteris applied to remove desired signal [1].Thusfor the process of filtering,the FIR filter is
utilized because of its stability measures. Finite Impulse Response (FIR) Filter is an impulse
response in a definite time. The greater numbers of itsapplications are seen in the area of image,
andsignal processing, biomedical signalprocessing, speech processing,etc. To construct effective
stable filters,the outperform features of the FIRfilter are mainly utilized.And, these
characteristics also contain unconditionalstability and linear phase, absence of overflow
oscillations, implementation ease, more computing efficiency, and capability for implementing
filters with co-efficient below 1. In terms of time, FIR filters will either be discrete or
continuous.The FIR filter's design process is based on the estimation of the ideal filter and it is
implemented in software.Windowing methods are the fundamentaltechniques to form
thesefilters. Thus, the mainmotiveof FIR filters is to remove theundesired distortion and noise to
retain theseeffective signals [2]. To make the FIR filter effective for the major applications of
signal processing,prime factors like anti-aliasing, pre-processing,bandselection, low pass
filtering, and interpolation are used. FIR filter is choosed as the best option,to create a filter
without noise since the bits do not need to be rounded or truncated. For the practical approach to
image processing, an FIR filter will be a better solution.Theyare digitally applied in either
hardware or software.
The FIR filter is represented in Equation (1):
X(k) = ∑K−1
h=0 (n(h)Y(K − h)) (1)

Where X(k) indicates the filter output, Yindicates the input data, nindicates the coefficients of
the filter and K is the number of coefficients of the filter. To makea digital FIR filter,the number
ofmultipliers and adders are Kand (K-1)neededrespectively. An FIR Filter general structure
isdisplayed in Figure.1.

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Fig.1 FIR Filter – General Structure

Figure 1 contains (K-1) amount of Multipliers, Kamount of adders,and delay elementsseries.
Thus, FIR filters are largely utilized as a useful tool in applications of multimedia and digital
signal processing (DSP). The two prime factors calledreconfigurability and low complexity are
required. The main factor of complexity of filter is based on the adders executed in a unit of
multiplication. And also, FIR filter reconfigurabilitywill realize the filter's performance while
determining the filter's order.
In several applications, to obtain the great suppression of spectral and reductionof noise, an FIR
filter along with a moderately largeamount of tabs are needed [3]. Several prior efforts are taken
for optimizing the filter’scoefficientsby maintaining the filter’s order. In those methods,
decreasing the amount of subtract/adder or shift and add unit is alsothe mainaim for purpose of
research. Though,the disadvantage in those methodsis that the coefficients are notchanged, while
the architecture of the filter is designed.Thus, these methods are not used in programmable
coefficients. The order of the filter is dynamically altered, as per the stopband energy of the
signal which is given as input. But, the methodwill affect the adaptation time of filter order
because of the calculation of energy in the feedback process [4].Whilefilters are the main
determinants for power consumption and system performance, thus there is a greater emphasis
on designing a filter structureto optimizepower and area utilization [5]. Thus, the paper focusesto
design an FIR filter,and it includes a summary of efforts tooptimize power, delay, and
areautilization of anFIR filter.
2. RELATED WORKS

An existing method proposes a new FIR filter known as dual-mode deadbeat H2 FIR
(DMDH2FF) [6] filter for estimating state in a system of discrete linear time-invariant
over extrinsic disturbances. To reduce the subjectof H2 norm to the condition of a deadbeat in

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the channel of disturbance-to-estimate, the derivation of DMDH2FF is madeand it also manages

the size of the horizon in two modes of operation. The DMDH2FF contains good robustness
across temporary designand uncertainty while comparing with a traditional H2 FIR filter. The
DMDH2FF performanceis revealed by a simulation of an engine called F-404 turbofan.
AnotherFIR Filter model called 16-Tap [7] is implementedby applyingan improved algorithm
called Booth recoding and it is performedalong with booth multiplier namely Radix-4. The
proposed architecture of multiplier will minimize the delay of propagation in digital circuits and
also aids to decrease the number of steps during multiplication. Field Programmable Gate Array
(FPGA) synthesis equipment will generate the result of implementation and evaluation is done
depending on that performance. While comparingan FIR filter to a conventional multiplier, the
proposed filter results indicate that good performance is attainedin resource utilization, power,
and area. In this FIR filter, capacity and power are condensed to 22.20% and 52.27 %
individually while compared withconventional FIR filters.
For generatinga partial product, depending on a Vedic Mathematics called UrdhvaTiryagbhyam
sutra,an 8-bit multiplier has been proposed in this literature [8]. A carry skip approach is used in
the Vedic multiplier, for recognizingthe inclusion of partial product. For making a design of an
8-bit multiplier, 4 × 4 sizesof 4 Vedic multipliers are used. UrdhvaTiryagbhyamand Carry skip
approaches are applied for this model. The multiplier has been designed,for the inclusion of
partial products. The modification of logic levels of Ripple Carry Adder (RCA)is carried outfor
computing thisoutput of the Vedic multiplier. Powerful ECG noise elimination is done by
applying this FIR filter. And also, used in the field of biomedical and healthcare applications.
A kinematic technique is proposed[9] for continuously interpolating commands of G01in
\industrial 5-axis machine devices.The adoption of FIR filters is made to generate the trajectory
of jerk-limited and time-optimal of linear parts. The rotary and translational motion is filtered
over the machine and workpiece coordinate structure, respectively. A principle of scaling is
constructed to make synchronize the rotary and translational motions w.r.to an FIR filter’stime
duration, and simultaneously, to reduce the cycle time. For both tangential and axial kinematic
constraints, a new correction and prediction pattern is also proposed.Therefore, both tracking
performances and machining quality are achieved better.

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Another method focused on [10] accelerating the process of adaptation based on the
decorrelationapproachin an FIR filter. Initially, the equation which is updatedis dissociated into
decorrelationof spatial and temporal. And, using a decomposing techniqueof eigenvalue,their
respective conditions of convergence are systematically studied. Simulations are carried out on
both the real world and synthetic data. The factors comprisingmany iteration and channels,
selection of window size and filter order, and computational time are elaborately discussed and
compared.
The simple and effective digital filter’s design is proposed depending on the farrow structureand
also it is designed with hybrid optimization namely Brain Storm-Artificial Bee Colony (BSABC)
approach [11]. The algorithm will workdepending on the minimal objective function which is
based on the overall amount of the hardware elements especially subtractors/addersutilized for
the frequency response and filter design. And also,works in a way that the filter quality is
maintainedwhile using fewer hardware elements. The optimal tuning is simulated by applying
the proposed technique and analyzedto highlight the effective approach. The analysis progressis
made in the amount of components utilized in the magnitude,fitness, and design.
A new application of the homotopyapproachis proposed to design seismic digital FIR filters
forseismic migrationpurposes [12]. The problemof the FIR filter's design is resolved by
applyingthe continuation method of scalar homotopyas the equation of the filter system is
overdetermined. Additionally, the design method is changedto satisfy the scalar homotopy
approach's consistency condition. Being a newimplementation to design filters, the scalar
homotopymethod needsmore time to run when compared to othertechniques such as L1-norm and
Weighted Least Squares (WLSQ) methods. Simultaneously, the homotopyapproach is
convergent and also does not need the Jacobian matrixinversion, which is themost
importantbenefit for practical design.
Another new objective function called normalized error fitnessand a robust hybrid techniqueis
proposed for seeking the coefficients of ideal filter and for giving sharp margin frequency
response while the filtering process is in action [13]. The most well-known particle swarm
optimization (PSO)and differential evolution (DE)algorithm are combined effectively to form the
hybrid DE-PSO technique for increasing the ability ofexploitation and exploration. By using 12

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different functions of benchmark, the hybrid technique is validated. The method's performance is
compared to that of thestandard DE, PSO,Parks–McClellan,and genetic algorithm.
The Fin field-effect transistors (FINFET)areused as an alternative for the challenges ofcontinue
scaling. As procedure schemes of nanometerare advanced, the chip density and operation
frequency are augmented, by the power consumption in portable gadgets that will be animportant
concern for the battery which is operated. Though for non-portabledevices, the power
consumption is significant because ofincreased cooling & cost of packaging, and the possible
issue of reliability. Then, in a design of the system on chip, caches will employ a significant
number of area in a system of DSP, that leads to an increase in powerleakage. Because of many
gates, the structure of FINFETs will have good electrostatic control acrosseffects of short
channel, thus it will minimize power leakage at the regime of nano. Thus, FIR filter and cache
memory are designed using FINFETs at a strategy of 22-nanometer by using HSPICE [14].
To linear time-changing pairwise Markov models (PMM), a new estimation method is proposed
in the literature[15], i.e. robust to a parameter of system uncertainties that will occur in real-
world applications. A state estimation issue known as finite-horizon is solved,todealwitherrors of
mismodeling and noiseignorance. The resulting unbiased FIR filter for PMM (PMM-UFIR) is
initially derived asa batch and for the cause of complexity reduction,it is transformed to a form
of recursive Kalman.
Another method to apply the digital fractional delay, a simple, efficient, and accurate design of
the FIR filter is presented [16].The design methoddepends on the expansion formula of the
MacLaurin series which is usedin a function to attain a closed structureFIR filter estimation of
the digital fractional delay operator. Thus, thederived formula is related to the Grünwald-
Letnikov formula of the absoluteanalog fractional differentiator.
An existing method introduces anFIR filter architecture of Vedic Design - Carry Lookahead
Adder [17] to execute the operation of FIR filter with a de-noising application of Electro
Cardiogram (ECG) signal. By utilizing the program of MATLAB, the input signal called ECG is
read and to this input signal,Additive White Gaussian Noise (AWGN) is appended. The process
of denoising is applied in Verilog, then the output is written in text file format.In MATLAB, the
binary text rates are read,mainly to de-noise the signal. Using Verilog code, the performance of
ASIC(power, delay, and area) and the performance of FPGA( flip flop, LUT, frequency, and

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slices) are evaluated. For the implementation of ASIC, 45 nm and 180 nm technology are applied
and Virtex-5, Virtex-6, and Virtex-4 devices are applied to calculate the performancefor
FPGAimplementation.
Anothermethod proposes FIR filter design using Vedic multiplier of Wave pipelinedand adder
[18] from the study of various multipliers and adders. The method demonstrates the
UrdhvaTriyagbhyam–Vedic approach’seffectiveness for multiplication, which will strike a
greater difference in the real-timeoperation. Thus, the method alsoreduces the FIR filter’spath
delay and setup time violation using sensors of a pad. Then,the proposed filter is synthesized,
simulated,and power consumption is calculatedusing Xilinx, Altera Quartus II, and the ISE
simulator.
A scalable architecture is presented to effectively compute adaptive FIR filters by utilizing
analgorithm called least mean square (LMS) [19]. This isattained by removingpaths that are
critical because they willmake an impact on the scalability of parallel architectures. A number of
bit-length and taps can be used to define scalability.For computing the high-order FIR filter, the
major demanding function is multiplication. Therefore, efforts are made to produce a compact
neural multiplier by enhancing the design and hardware application of thepresent multiplier.
When compared toan existing multiplier, the proposed multiplier needs26% clock cycles,30%
area resources, 40% neurons, and 50% synapses. Additionally, the time multiplexing method is
employed to increase the proposed multiplier utilizationby performing adaptive process and filter
process because in both processesmultiplication is made.
An effective FIR filter is designed with a technique of meta-heuristic based on a game theory
approach which will afford a compression ratio of compromising data for common input figures
[20-25]. Compression ratio and Mean Square Error, two impressive quality indicators, will verify
the anticipated method consequences in medical applications.Since it provides extraordinary
outcomes for MRI images and Ultrasound compression, thus gives a way for trans receiving
information with minimal space.
Anothermethod explainsstochasticbeamsearchwhich isutilizedasapopulation-based design
process,that optimizes its individuals using a Branch and Bound (B&B) search [26-31]. These
filters containtwodrawbacks;theyareonlyeffectivetotheShortWord‐Length (SWL)inputs,and the
feasiblefrequencyresponsesarelimitedforsmoothtransitions.

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3. PROPOSED WORK

The FIR filter operation iswidely applied in Digital Signal Processing.The output of the FIR
filter is the weighted sum of the current and prior input sample’s finite number namely
convolution. Some of the benefits of the FIR filter areinherent stability,linear phase
characteristics,and does not need any feedback.In general, the power utilizationof an FIR filter is
proportionalto the computationamount. Thus, to decrease the powerutilization, the proposed FIR
filter structurewill cancelredundant multiplications.The structure is reconfigurable since it
dynamically alters the filter’sorderby considering the amplitude of filter coefficients and data
samples. The filter performance is maintained by performing the product of the data sample and
filter coefficient as little as the quantization error.

Fig.2Reconfigurable FIR Filter Architecture

Figure.2depicts the reconfigurable FIR filterarchitecture. It contains three sectionsnamely
Multiplier Control Signal Decision window (MCSD),Amplitude Detector (AD), and control
signal generator. Depending on the amplitude, few of the multipliers are switched off, thusthe
architecture will reduce the power utilization. Especially, the dynamic power is minimizeddue to
the activity of switching of interior node capacitance which will directly contribute to the overall
dynamic power utilization of a CMOS gate.
While multipliers are turned off,depending on the data sample and filter coefficientamplitudes,
the proposed reconfigurable framework will dynamically alter the order of the filter. For the
cancellation of multiplication, the criteriaappliedis for both data sample and filter coefficient

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amplitude is less which isa predetermined value of threshold or not. To check these criteria a
combinational logic circuit known as Amplitude Detector is utilized. When the incoming data
sample x (n)amplitude is lower than the threshold, then the AD output (ad_out) will become “1”.
Whenapplying this logic, the problem that arises is that the data sample amplitude will abruptly
change for each cycle, thus the multipliers will be on and off continuously. Therefore,there will
be increases in the activity of switching and then the dynamic power also increases. For this
problem of switching, MCSD is applied here.

MCSD is utilized to decrease the switching activityfrequency. In the MCSD window, a control
signal generator is used to reduce the problem of switching.The generatorcontains an interior
counter which will count the consecutive incoming samples,while it is lower than a
threshold,then the multiplier is turned off. Thus, when the counter finds thatsuccessive incoming
samples are slighter than the threshold, the ctrl signal will alter to ‘1’,indicating that consecutive
lower amplitude of input samples are identified and multipliers are prepared to turn off. The ctrl
signal controls the insertion of one more bit in the dotted line of Figure 1.The input sample is
multiplied with coefficient by using a multiplier.The filter operation is shown in Figure 1, but a
variant configuration is provided for minimizing the power, delay, and area consumption.Figure
1 executes the filter operation but a various configuration is revealed for decreasing the delay
power, and areaconsumption.Thus, when the data sample and filter coefficient amplitude is
lower than the value of the threshold, i.ethe signal is set to “1”, then the multiplier is turned off
by anordinary logic circuit, and also the output isset to zero.

Conventional Russian peasant multiplier:

A traditional Russian Peasant Multiplierframework composes of 2:1 multiplexers &adder units,

and shifters. It is anordinaryframeworkthatutilizes less delay and area for multiplication
computation. While compared to othermultipliers, itgives less area, time, and power product.
Figure 3depictsthe 8-bit Russian Peasant Multiplier framework.

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Fig.38-bit Russian Peasant Multiplier Architecture

Simultaneously, from the 8-bit Russian Peasant Multiplier,the 16-bit multiplier is extended.
Multiplexers and Shifters in Figure 2 are applied to execute the operation of partial product
which will utilize less power and area than other multipliers namely Vedic. An adder called carry
save is used for partial product addition which is displayed as Wallace adder. Next,to minimize
delay and area, an adder called carry select along with Sklansky adder is utilized in the
architecture of the Russian Peasant Multiplier instead of Wallace adder. To decrease the
switching activity, the control signal generating circuits are utilized in the MCSD window.

Proposed Russian peasant multiplier with Sklanskyand Han Carlson adder:

The Reconfigurable FIR filter is largely appliedinseveral wirelesscommunication and DSP

applications. The reconfiguration approach is used forvalues of fixed coefficient and
programming coefficient. But in a unit of multiplication,the reconfigurable FIR filter complexity
isfound. Russian Peasant multiplierwill perform multiplications in the traditional reconfigurable
FIR filter. In the multiplier of Russianpeasant architectures, two shiftertypesnamely ‘R’ and

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‘L’indicated as a rightshifter and left shifter are utilizedrespectively. Tochoosevalid bits as

products of partial, it performs operations of shifting,and also consecutive 2:1 multiplexers are
utilized. Every LSB of the rightshifter is utilized as the selection signal for everymultiplexer.
Then, the products of partial are added by using adder namely carry save which contains Ripple
CAdder (RCA) and also a number of 1 bit unit of full adders.The unit of adderin Russian Peasant
Multiplication will result in large area and delay. A carry save adder is substituted by a carry
select adder along with Sklanskyand Han Carlsonadder, to minimize the delay and area of the
Multiplication.Dual RCAs are used in carry select adder to perform operation of addition.
Normally RCAwill utilizemore delay and area because of carrypropagation. Dual
RCAsaresubstituted by 1 RCA and 1 BExcess1 converter which istermedas SQRTCSLA,mainly
to decrease the delay.
The upper portionof RCA issubstituted by Sklansky adder,to further decrease the delay in CSLA.
Sklansky adder is the speedy parallel adders to perform operation of addition with lower
delay.The architectureof Multiplier with carry select adder by applyingSklansky adder is
displayed in Figure4.

Fig.4Architecture of carry select adder withSklansky adder

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Thus, along with Sklansky, another parallel prefix adder called Han Carlson is used in our
proposed Reconfigurable FIR filter, to consumethe lowerarea. Parallel Prefix Adders are known
as high-speed adders.The parallel prefix addition consists of 3 module stages namelypre-
processing, post-processing, and carry generation. The calculations in every stage are:
Pre-processing:
Pa= AaxorBa
Ga = Aa and Ba
Carry generation:
P(a:l) =P(a:b) and P(b-1:l)
G(a:l) =G(a:b) or (G(b-1:l) and P(a:b))
Post processing:
Sa=Pa and Ca
Ca+1= (Pa.C0) +Ga
Han Carlson adder also works with a similar speed of adder called Kogge stone but covers less
area than Kogge Stone. Figure 5 shows the tree structure of Han Carlson. Its framework is
obtained from the 2phases of Brent Kung adder and 3phases of Kogge stone adder.

Fig.5 8 Bit Han-Carlson Adder - Tree Structure

It begins with Brent Kung followed by three phases of Kogge stone and then is terminated with
an adder of Brent Kung. The calculation of prefix of an odd number is made with Brent Kung
Adder. The Han Carlson propagation delay is given by log2n. Therefore, theproposed method
usesSklansky and Han Carlson in a technique of Russian Peasant Multiplication, and

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createsefficient output while compared with other addersdue to its faster operation,consumes
lessdelay and area.
4. RESULTS AND DISCUSSION

Simulation for existing ripple carry adder and multiplier, carry save adder and multiplier, and
proposed carry select adder and multiplier using Sklanskyand Han Carlson was implemented
with ModelSimin aXilinx ISE 14.3.
The performance of power and delay for 16-bit, 24-bit, and 32-bitbased on carry save adder,
ripple carry adder, and carry select adder using Sklansky and Han Carlsonarecompared and
analyzedin Table 1, 2, and 3.

Table 1 - 16 bit Adder Design

Power Delay PDP (x10- No of No of

S No Name of the adder 15
(µ.watt) (n sec) ) LUTs Slices
1 Ripple Carry Adder 2.768 1.735 4.8025 26 18
2 Carry Save adder 2.634 1.024 2.6972 28 20
Carry Select Adder using
3 2.497 0.7681 1.9179 26 18
sklansky adder
Carry Select Adder using
4 2.164 0.621 1.3438 27 19
Han Carlson Adder

Table 2 - 24 bit Adder Design

Power Delay PDP (x10- No of No of

S No Name of the adder 15
(µ.watt) (n sec) ) LUTs Slices
1 Ripple Carry Adder 4.845 2.527 12.2433 40 28
2 Carry Save adder 4.728 1.846 8.7279 43 30
Carry Select Adder using
3 4.476 1.349 6.0381 39 27
Sklansky adder
Carry Select Adder using
4 4.092 0.943 3.8588 40 29
Han Carlson Adder

Table 3 - 32 bit Adder Design

Power Delay PDP (x10- No of No of

S No Name of the adder 15
(µ.watt) (n sec) ) LUTs Slices
1 Ripple Carry Adder 6.384 3.157 20.1543 54 38
2 Carry Save adder 6.158 2.568 15.8137 57 40

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Carry Select Adder using

3 5.904 1.867 11.0228 54 37
Sklansky adder
Carry Select Adder using
4 5.684 1.253 7.1221 56 39
Han Carlson Adder

Tables 1, 2, and 3 show that the CSAusingSklanskyand CSA using Han Carlson adder will
utilize less power, delay,and PDP whilecompared to the ripple carry and carry save adder.Figure
6depicts the ModelSim snapshots of a conventional and proposed adder.

Fig. 6Adder Results

The performance of power and delay for 16-bit, 24-bit, and 32-bit based on multiplier with ripple
carry adder, carry save adder, and Russian Peasant Multiplier with carry select adder using
Sklansky, and Han Carlsonare compared and analyzed in Table 4, 5, and 6.

Table 4 - 16 bit Multiplier Design

Power Delay PDP (x10- No of No of

S No Multiplier 15
(µ.watt) (n sec) ) LUTs Slices
Ripple Carry Adder
1 12.542 3.765 47.2206 92 61
based multiplier
Carry Save adder based
2 12.479 3.846 47.9942 97 68
multiplier
CSA-Sklansky adder
3 based Russian Peasant 11.657 3.257 37.9668 92 65
Multiplier
CSA-Han Carlson Adder
4 based Russian Peasant 11.248 2.834 31.8768 94 67
Multiplier

Table 5 - 24 bit Multiplier Design

Power Delay PDP (x10- No of No of

S No Multiplier 15
(µ.watt) (n sec) ) LUTs Slices
Ripple Carry Adder
1 14.976 4.861 72.7983 40 97
based multiplier
2 Carry Save adder based 14.742 4.573 67.4152 43 103

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multiplier
CSA-Sklansky adder
3 based Russian Peasant 14.037 4.0279 56.5396 39 96
Multiplier
CSA-Han Carlson Adder
4 based Russian Peasant 13.895 3.917 54.4267 43 99
Multiplier

Table 6 - 32 bit Multiplier Design

Power Delay No of No of
S No Multiplier PDP(x10-15)
(µ.watt) (n sec) LUTs Slices
Ripple Carry Adder
1 16.976 6.24 105.9302 182 132
based multiplier
Carry Save adder based
2 16.614 5.863 97.4079 191 137
multiplier
CSA-Sklansky adder
3 based Russian Peasant 15.834 5.271 83.4610 185 130
Multiplier
CSA-Han Carlson Adder
4 based Russian Peasant 15.451 4.937 76.2816 187 134
Multiplier

When comparing witha different existing adder and also with Russian Peasant Multiplier, there
will be a reduction in power, delay, and PDP, when CSA withSklanskyand CSA withHan
Carlson adder is integratedwith Russian Peasant Multiplier than the traditional Russian Peasant
Multiplier.
It indicates that consumption of power and delay is better whileapplying the Sklanskyand Han
Carlsonadder for doing addition operationsin a multiplier.Figure 7 depicts the ModelSim
snapshots of a conventional and proposed multiplier.

Fig.7Multiplier Results

The evaluation matrices are measured to identify the FIR filter design efficiencynamelyDelay,
Power, and PDP in table 7.

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Table 7 –FIR Filter design

Power Delay No of No of
S No Name of the adder PDP(x10-15)
(µ.watt) (n sec) LUTs Slices
1 RCA based FIR Filter 437.238 8.749 3825.3953 182 132
Carry Save adder based FIR
2 421.87 7.982 3367.3663 191 137
Filter
CSA-Sklansky adder -
3 Russian Peasant Multiplier 397.476 6.374 2533.5120 185 130
based FIR Filter
CSA-Han Carlson adder -
4 Russian Peasant Multiplier 387.784 5.349 2074.2566 187 134
based FIR Filter

The result depicts that the proposed high-speed adders which are based on FIR filter design will
givegood performance rather than standard FIR filter. It displays that FIR filter-based Sklansky
and FIR filter-based Sklansky Han Carlson adder saves PDP lesser while compared to RCA and Carry
Save-based FIR filter. Figure 8 and 9 depicts power and delay of FIR filters.

Power

440
430
420
410
400
390
380
370 Power
360
RCA based FIR Carry Save adder Proposed CSA-
Filter based FIR Filter Sklansky and Han
Carlson adder -
Russian Peasant
Multiplier based
FIR Filter

Fig. 8 Power consumption

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Delay

9
8
7
6
5
4
3
2
1 Delay
0
RCA based FIR Carry Save adder Proposed CSA-
Filter based FIR Filter Sklansky and Han
Carlson adder -
Russian Peasant
Multiplier based
FIR Filter

Fig. 9 Propagation Delay

It can be observed that the proposed filterconsumesless area, power, and delay when compared to
the traditional FIR filters.Hence, the proposed performance of the Russian Peasant multiplier is
integrated with a reconfigurable FIR filter. The results are evaluated in Verilog HDL (Hardware
Description Language). The simulation functionality is calculated using ModelSim and the
consumption of power and delay for the filters are calculated by processing in Xilinx ISE 14.3.

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Fig.10 FIR Filter Results

Figure 10depicts the result of the simulation fora reconfigurable FIR filter with the Russian
Peasant Multiplier.From thiscalculation,it is clear that the modified reconfigurable FIR filter is
useful for the application of signal processing while compared to the conventional FIR filter.
5. CONCLUSION
In this work, a high-speedRussian Peasant Multiplier is altered by substituting the carry select
along with Sklanskyand Han Carlsonadder rather than carry save adder utilized in a multiplier.
The proposed Russian Peasant Multiplier will offersarea, power, and delay reduction when
compared to the traditional Russian Peasant Multiplier. Thus, themodified Russian Peasant
Multiplier is integratedwith a reconfigurable FIR filter. Comparison is made between the
traditional and proposed reconfigurable FIR filter along with the Russian Peasant Multiplier. The
result demonstrates that the proposed modified reconfigurable FIR filter will provide less area,
power, and delayreduction without lowering the performance of the filter than the conventional
FIR filter. In future work, the proposed modified FIR filter is utilized in wireless communication
and also in the application of image processing.

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