Gayatri 17AJ1D4303 PDF Document

THERMAL STRESSES RELIEF CARRIER-BASED PWM
STRATEGY FOR SINGLE PHASE MULTILEVEL INVERTERS
A Project report submitted to Jawaharlal Nehru Technological University, Kakinada in partial

fulfilment of the requirements for the award of the Degree of
MASTER OF TECHNOLOGY
IN
POWER ELECTRONICS
By
B H V N S R GAYATHRI SAI
17AJ1D4303
Under the guidance of
MS. B JYOSHNA
Assistant Professor
AMRITA SAI INSTITUTE OF SCIENCE AND TECHNOLOGY

(Affiliated to Jawaharlal Nehru technological university Kakinada)
Amrita Sai Nagar, Paritala, Krishna Dist – 521 180
2017 – 2019
AMRITA SAI INSTITUTE OF SCIENCE AND TECHNOLOGY
(Affiliated to Jawaharlal Nehru Technological University, Kakinada)
Paritala, Kanchikacherla (Md), Krishna (Dist) – 521 180
DEPARTMENT OF
ELECTRICAL AND ELECTRONICS ENGINEERING
CERTIFICATE
Certified that this is a bonafide record of the Thesis work entitled,

“THERMAL STRESSES RELIEF CARRIER-BASED PWM STRATEGY
FOR SINGLE PHASE MULTILEVEL INVERTERS’’ , done by BH. V N S
R GAYATRI SAI bearing H.T. No: 17AJ1D4303 submitted to the faculty of
Electrical & Electronics Engineering, in partial fulfilment of the requirements
for the Degree of MASTER OF TECHNOLOGY with specialization in POWER
ELECTRONICS from JAWAHARLAL Nehru Technological University Kakinada.
Supervisor Head of department
B. JYOSHNA Mr.CH. CHINNA VEERAIAH M.Tech, LMISTE

Assistant Professor Assistant Professor &
ACKNOWLEDGEMENT
I would like to express my sincere thanks to B. JYOSHNA, Assistant Professor ,

Department of Electrical and Electronics Engineering, for her kind co-operation and
encouragement, which helped me in completion of this project. It would have been very difficult
to complete this project without the enthusiastic support, insight and advice given by her.
I would like to extend my heartful gratitude to MR.CHINNA VEERIAH, Head of the

Department of Electrical and Electronics Engineering, Amrita Sai Institute of Technology and
Science, who has persistently and determinedly guided us during the whole course of this project.
My sincere regards to DR.M.SASIDHAR, The Principal, Amrita Sai Institute of

Technology and Science for providing necessary research facilities for carrying out the project.
I sincerely thank to all the staff of the Department of Electrical and Electronics
Engineering, Amrita Sai Institute of Technology and Science, Paritala for their co-operation
received.
I wish to thank all the well-wishers for their constant source of encouragement and moral
support during the course of this work. I would like to express my gratitude to all those who gave
me the possibility to complete this project.
BH. V N S R GAYATRI SAI
17AJ1D4303
DECLARATION
I declare that the project report entitled “THERMAL STRESSES

RELIEF CARRIER-BASED PWM STRATEGY FOR SINGLE PHASE
MULTILEVEL INVERTERS” recorded in this report does not form part of any
other thesis on which a degree has been awarded earlier. I further declare that this
main project report is based on my work carried out at the “AMRITA SAI
INSTITUTE OF TECHNOLOGY AND SCIENCE”, Paritala in the M.Tech course.
Reported by
BH. V N S R GAYATRI SAI
17AJ1D4303
INDEX
Title Page no
List of Tables
List of Figures
Abstract 1
Chapter -1 :-Introduction 2
1.1:-Research Back Ground 2
1.2.high Frequency Ac Power Distribution System 4
1.3 Ac power Requirements 7
1.4 Effect of High Frequencies 8
1.5 Technique for reducing AC Resistence 9
1.6.Techniques for reducing Redaction Loss 9
1.7 Mathematics of AC Voltages 11
1.8.Why Cascaded H bridge multilevel inviter 14
1.9 Dissertation out line 17
Chapter -2 Multilevel inverter structures 18
2.1 Introduction 18
2.2 Diode Clamped Multilevel inverter 18
2.3 Operation of DCMLI 20
2.4 Features of Diode Clamped MLI 21
2.5 Advantages and Disadvantages of DCMLI 23
2.6 Conclusion 23
2.7 Flying Capacitor Structure 24
2.8 Operation on FCMLI 24
2.9 Features of FCMLI 25
2.10 Advantages and Disadvantages of FCMLI 26
2.11 Cascaded Multilevel Inverter 27
2.12 Operation of CMLI 28
2.13 Features of CMLI 28
2.14 Advantages and Disadvantages of CMLI 29
2.15 Conclusion 29
Chapter -3 Modulation strategies 30
3.1 Modulation Strategies 30
3.2 Pulse width modulation 31
3.3. Space vector PWM 32
Chapter -4 Multilevel inverters 38
4.1. Transformer less Multilevel inverters 38
4.2 Operation of Proposed cascaded five level MLI 40
4.3 Proposed PWM Strategy with generalized strategy 45
for minimization of the leakage current
4.4 Integration of MPPT for praposed five level CMLI 48

Chapter -5 TSR Life time extension 49
5.1 Introduction 49
5.2 thermal Stresses & Life time extension 52
5.3 Single Phase five level inviter Operation 54

5.4 the proposed Strategy 58
Chapter -6 Simulation / MAT lab results 61
Chapter -7 Conclusion 64
Future Scope 65
References 66
LIST OF TABLES
Table No. Name of Tables page No.
2.1 switching stages in one leg of three level diode clamped inverters 19
2.2 Switching stages in one leg of the five level diode clamped inverter 21
3.2 over view of the various is given 33
5.1 Table -1 switch combinations for different levels of five level inverter 59
LIST OF FIGURES
Fig No. Figure Names Page No.
1.1 High Voltage Transmission Lines 5

1.2 Sine wave one cycle (360) 11
2.1 One phase leg of an inverter 18
2.2. Topology of diode clamped inverter 19
2.3 Out put Topology in three level diode
clamped inverter 19
2.4 Capacitor clamped multilevel inveter
Circuit topologies 24
2.5 Single phase structures of cascaded inverter 27
2.6 Three phase Seven Level cascaded multilevel
Inverter 28
3.1 PWM with bipolar Switching pattern 31
3.2 Space vector diagram for a three-level converter 33
3.3 Overview of hexagons 34
3.4 Duty Cycle calculation outside the six inner
Hexagons 35
3.5 Cycle calculation out side the six inner
Hexagons 35
3.6 switching Pattern for space vector modulation 36
4.1 Proposed five-level grid-connected CMLI with
PV and parasitic elements 42
4.2 Proposed five level cascaded MLI for out put
Voltage Level 43
4.3 Gate Pulse for the switches corresponding to
Inverter output voltages 45
4.4 Generalized 2n+1 topology drivered from
Proposed five level CMLI 46
4.5 The wave form of out put voltage vuv for the
Proposed pwm technique 47
4.6 The wave from Generaled modified v reference
Modified. 48
5.1 A schematic diagram of PWM control full bridge
n-level t-type inverter 50
5.2 Various model of Power semiconductor
Device 55
5.3 schematic diagram of Thermal Stress relief 56
5.4 Single Phase full Bridge T-type inverter system 56
5.5 Carrier based PWM single Phase five level
Inverter 57
5.6 Output Voltage inverter at Regions 57
5.7 Gating Pulses for IGVT switches in regions
R 2 S sequences. 60
THERMAL STRESSES RELIEF CARRIER BASED PWM STRATEGY FOR SINGLE PHASE MULTILEVEL INVERTERS
ABSTRACT
Enhancing power cycling capability of power semiconductor devices is highly
demanded in order to increase the long term reliability of multilevel inverters. Ageing of
power switches and their cooling systems leads to their accelerated damage due to excess
power losses and junction temperatures. Therefore, thermal stresses relief (TSR) is the most
effective solution for lifetime extension of power semiconductor devices. This paper presents
a new thermal stresses relief carrier-based pulse width modulation (TSRPWM) strategy for
extending the lifetime of semiconductor switches in single-phase multilevel inverters. The
proposed strategy benefits the inherent redundancy among switching states in multilevel
inverters to optimally relieve the thermally stressed device. The proposed algorithm maintains
the inverter operation without increased stresses on healthy switches and without reduction of
the output power ratings. In addition, the proposed algorithm preserves voltage balance of the
DC-link capacitors. The proposed strategy is validated on single phase five level T-type
inverter system with considering different locations of thermal stresses detection.
Experimental prototype of the selected case study is built to verify the results. Moreover,
comparisons with the most featured strategies in literature are given in detail.
Index Terms—Lifetime extension, long term reliability, multilevel inverter, pulse width
modulation (PWM), thermal stresses relief.
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, ASIST 1

CHAPTER-1
INTRODUCTION
1.1 Research Background
Power electronic converters, especially dc/ac PWM inverters have been extending their
range of use in industry because they provide reduced energy consumption, better system
efficiency, improved quality of product, good maintenance, and so on.
For a medium voltage grid, it is troublesome to connect only one power semiconductor
switches directly As a result, a multilevel power converter structure has been introduced as an
alternative in high power and medium voltage situations such as laminators, mills, conveyors,
pumps, fans, blowers, compressors, and so on. As a cost effective solution, multilevel
converter not only achieves high power ratings, but also enables the use of low power
application in renewable energy sources such as photovoltaic, wind, and fuel cells which can
be easily interfaced to a multilevel converter system for a high power application. The most
common initial application of multilevel converters has been in traction, both in locomotives
and track-side static converters. More recent applications have been for power system
converters for VAR compensation and stability enhancement, active filtering, high-voltage
motor drive high-voltage dc transmission, and most recently for medium voltage induction
motor variable speed drives. Many multilevel converter applications focus on industrial
medium-voltage motor drives, utility interface for renewable energy systems, flexible AC
transmission system (FACTS) , and traction drive systems.
The inverters in such application areas as stated above should be able to handle high
voltage and large power. For this reason, two-level high-voltage and large-power inverters
have been designed with series connection of switching power devices such as gate-turn-off
thyristors (GTOs), integrated gate commutated transistors (IGCTs), and integrated gate bipolar
transistors (IGBTs), because the series connection allows reaching much higher voltages.
However, the series connection of switching power devices has big problems ,namely, non-
equal distribution of applied device voltage across series-connected devices that may make the
applied voltage of individual devices much higher than blocking voltage of the devices during
transient and steady-state switching operation of devices.
As alternatives to effectively solve the above-mentioned problems, several circuit

topologies of multilevel inverter and converter have been researched and utilized. The output
voltage of the multilevel inverter has many levels synthesized from several DC voltage
sources. The quality of the output voltage is improved as the number of voltage levels
increases, so the quantity of output filters can be decreased.
The concept of multilevel converters has been introduced since 1975. The cascade
multilevel inverter was first proposed in 1975. Separate DC-sourced full-bridge cells are
placed in series to synthesize a staircase AC output voltage. The term multilevel began with
the three-level converter. Subsequently, several multilevel converter topologies have been
developed. In 1981, diode-clamped multilevel inverter also called the Neutral-Point Clamped
(NPC) inverter schemes were proposed. In 1992, capacitor-clamped (or flying capacitor)
multilevel inverters, and in 1996, cascaded multilevel inverters were proposed.
A multilevel converter has several advantages over a conventional two-level converter that
uses high switching frequency pulse width modulation (PWM). The attractive features of a
multilevel converter can be briefly summarized as follows.
1. Staircase waveform quality: Multilevel converters not only can generate the output
voltages with very low distortion, but also can reduce the dv/dt stresses; therefore
electromagnetic compatibility (EMC) problems can be reduced.
2. Common-mode (CM) voltage: Multilevel converters produce smaller CM voltage;

therefore, the stress in the bearings of a motor connected to a multilevel motor drive can be

reduced. Furthermore, CM voltage can be eliminated by using advanced modulation

strategies such as that proposed.
3. Input current: Multilevel converters can draw input current with low distortion.
4. Switching frequency: Multilevel converters can operate at both fundamental switching

frequency and high switching frequency PWM.
It should be noted that lower switching frequency usually means lower switching loss and
higher efficiency. Multilevel converters do have some disadvantages. One particular
disadvantage is the greater number of power semiconductor switches needed. Although lower
voltage rated switches can be utilized in a multilevel converter, each switch requires a related
gate drive circuit. This may cause the overall system to be more expensive and complex.
Abundant modulation techniques and control paradigms have been developed for multilevel
converters such as sinusoidal pulse width modulation (SPWM), selective harmonic
elimination (SHE-PWM), space vector modulation (SVM), and others. In this thesis sinusoidal
pulse width modulation (SPWM) is used.
1.2 High-Frequency AC Power Distribution System
The reason that electric power is distributed as alternating current is that AC voltage
may be increased or decreased with a transformer. This allows the power to be transmitted
through power lines efficiently at high voltage, which reduces the power lost as heat due
to resistance of the wire, and the voltage to be reduced to safe levels for use by the customer.
Use of a higher voltage leads to significantly more efficient transmission of power. The power
losses ( ) in a conductor are a product of the square of the current (I) and the resistance (R)
of the conductor, described by the formula
….(1.1)
This means that when transmitting a fixed power on a given wire, if the current is
doubled, the power loss will be four times greater.

The power transmitted is equal to the product of the current and the voltage (assuming
no phase difference); that is,
…(1.2)
Thus, the same amount of power can be transmitted with a lower current by increasing
the voltage. It is therefore advantageous when transmitting large amounts of power to
distribute the power with high voltages (often hundreds of kilovolts).
Figure 1.1 High voltage transmission lines
High voltage transmission lines deliver power from electric generation plants over long
distances using alternating current. These lines are located in eastern Utah. However, high
voltages also have disadvantages, the main one being the increased insulation required, and
generally increased difficulty in their safe handling. In a power plant, power is generated at a
convenient voltage for the design of a generator, and then stepped up to a high voltage for
transmission. Near the loads, the transmission voltage is stepped down to the voltages used by
equipment. Consumer voltages vary depending on the country and size of load, but generally
motors and lighting are built to use up to a few hundred volts between phases.
The utilization voltage delivered to equipment such as lighting and motor loads is
standardized, with an allowable range of voltage over which equipment is expected to operate.
Standard power utilization voltages and percentage tolerance vary in the different mains power
systems found in the world.

Modern high-voltage direct-current (HVDC) electric power transmission systems

contrast with the more common alternating-current systems as a means for the efficient bulk
transmission of electrical power over long distances. HVDC systems, however, tend to be
more expensive and less efficient over shorter distances than transformers. Transmission with
high voltage direct current was not feasible when Edison, Westinghouse and Tesla were
designing their power systems, since there was then no way to economically convert AC
power to DC and back again at the necessary voltages.
In practice, Three-phase electrical generation is very common. The simplest case is

three separate coils in the generator stator that are physically offset by an angle of 120° to each
other. Three current waveforms are produced that are equal in magnitude and 120° out of
phase to each other. If coils are added opposite to these (60° spacing), they generate the same
phases with reverse polarity and so can be simply wired together.
Higher "pole orders" are commonly used. For example, a 12-pole machine would have
36 coils (10° spacing). The advantage is that lower speeds can be used. For example, a 2-pole
machine running at 3600 rpm and a 12-pole machine running at 600 rpm produce the same
frequency. This is much more practical for larger machines.
If the load on a three-phase system is balanced equally among the phases, no current
flows through the neutral point. Even in the worst-case unbalanced (linear) load, the neutral
current will not exceed the highest of the phase currents.
Non-linear loads (e.g., computers) may require an oversized neutral bus and neutral
conductor in the upstream distribution panel to handle harmonics. Harmonics can cause
neutral conductor current levels to exceed that of one or all phase conductors.
For three-phase at utilization voltages a four-wire system is often used. When stepping
down three-phase, a transformer with a Delta (3-wire) primary and a Star (4-wire, center-
earthed) secondary is often used so there is no need for a neutral on the supply side.
For smaller customers (just how small varies by country and age of the installation)
only a single phase and the neutral or two phases and the neutral are taken to the property. For
larger installations all three phases and the neutral are taken to the main distribution panel.

Three-wire single-phase systems, with a single center-tapped transformer giving two

live conductors, is a common distribution scheme for residential and small commercial
buildings in North America. This arrangement is sometimes incorrectly referred to as "two
phase".
A similar method is used for a different reason on construction sites in the UK. Small
power tools and lighting are supposed to be supplied by a local center-tapped transformer with
a voltage of 55 V between each power conductor and earth.
This significantly reduces the risk of electric shock in the event that one of the live
conductors becomes exposed through an equipment fault whilst still allowing a reasonable
voltage of 110 V between the two conductors for running the tools.
A third wire, called the bond (or earth) wire, is often connected between non-current-
carrying metal enclosures and earth ground. This conductor provides protection from electric
shock due to accidental contact of circuit conductors with the metal chassis of portable
appliances and tools. Bonding all non-current-carrying metal parts into one complete system
ensures there is always a low electrical impedance path to ground sufficient to carry
any fault current for as long as it takes for the system to clear the fault.
This low impedance path allows the maximum amount of fault current, causing the
over current protection device (breakers, fuses) to trip or burn out as quickly as possible,
bringing the electrical system to a safe state. All bond wires are bonded to ground at the main
service panel, as is the Neutral/Identified conductor if present.
1.3 AC Power Frequencies
The frequency of the electrical system varies by country and sometimes within a
country; most electric power is generated at either 50 or 60 hertz. Some countries have a
mixture of 50 Hz and 60 Hz supplies, notably electricity power transmission in Japan.
A low frequency eases the design of electric motors, particularly for hoisting, crushing and
rolling applications, and commentator-type traction motors for applications such asrailways.

However, low frequency also causes noticeable flicker in arc lamps and incandescent light
bulbs. The use of lower frequencies also provided the advantage of lower impedance losses,
which are proportional to frequency.
The original Niagara Falls generators were built to produce 25 Hz power, as a

compromise between low frequency for traction and heavy induction motors, while still
allowing incandescent lighting to operate (although with noticeable flicker).
Most of the 25 Hz residential and commercial customers for Niagara Falls power were
converted to 60 Hz by the late 1950s, although some[25 Hz industrial customers still existed as
of the start of the 21st century. 16.7 Hz power (formerly 16 2/3 Hz) is still used in some
European rail systems, such as in Austria, Germany, Norway, Sweden and Switzerland.
Off-shore, military, textile industry, marine, aircraft, and spacecraft applications

sometimes use 400 Hz, for benefits of reduced weight of apparatus or higher motor speeds.
Computer mainframe systems are often powered by 415 Hz, using customer-supplied
35 or 70 KVA motor-generator sets.[3] Smaller mainframes may have an internal 415 Hz M-G
set. In any case, the input to the M-G set is the local customary voltage and frequency,
variously 200 (Japan), 208, 240 (North America), 380, 400 or 415 (Europe) volts, and
variously 50 or 60 Hz.
1.4 Effects of High Frequencies
A direct current flows uniformly throughout the cross-section of a uniform wire. An

alternating current of any frequency is forced away from the wire's center, toward its outer
surface. This is because the acceleration of an electric charge in an alternating current
produces waves of electromagnetic radiation that cancel the propagation of electricity toward
the centre of materials with high conductivity. This phenomenon is called skin effect.
At very high frequencies the current no longer flows in the wire, but effectively
flows on the surface of the wire, within a thickness of a few skin depths. The skin depth is the
thickness at which the current density is reduced by 63%. Even at relatively low frequencies
used for power transmission (50–60 Hz), non-uniform distribution of current still occurs in

sufficiently thick conductors. For example, the skin depth of a copper conductor is
approximately 8.57 mm at 60 Hz, so high current conductors are usually hollow to reduce
their mass and cost.
Since the current tends to flow in the periphery of conductors, the effective cross-
section of the conductor is reduced. This increases the effective AC resistance of the
conductor, since resistance is inversely proportional to the cross-sectional area. The AC
resistance often is many times higher than the DC resistance, causing a much higher energy
loss due to ohmic heating (also called I2R loss).
1.5 Techniques for reducing AC resistances
For low to medium frequencies, conductors can be divided into stranded wires, each
insulated from one other, and the relative positions of individual strands specially arranged
within the conductor bundle. Wire constructed using this technique is called Litz wire. This
measure helps to partially mitigate skin effect by forcing more equal current throughout the
total cross section of the stranded conductors. Litz wire is used for making high-Q inductors,
reducing losses in flexible conductors carrying very high currents at lower frequencies, and in
the windings of devices carrying higher radio frequency current (up to hundreds of kilohertz),
such as switch-mode power supplies and radio frequency transformers.
1.6 Techniques for Reducing Radiation loss
As written above, an alternating current is made of electric charge under

periodic acceleration, which causes radiation of electromagnetic waves. Energy that is radiated
is lost. Depending on the frequency, different techniques are used to minimize the loss due to
radiation.
a) Twisted pairs
At frequencies up to about 1 GHz, pairs of wires are twisted together in a cable,

forming a twisted pair. This reduces losses from electromagnetic radiation and inductive
coupling. A twisted pair must be used with a balanced signalling system, so that the two wires

carry equal but opposite currents. Each wire in a twisted pair radiates a signal, but it is
effectively cancelled by radiation from the other wire, resulting in almost no radiation loss.
b) Coaxial cables
Coaxial cables are commonly used at audio frequencies and above for convenience. A
coaxial cable has a conductive wire inside a conductive tube, separated by a dielectric layer.
The current flowing on the inner conductor is equal and opposite to the current flowing on the
inner surface of the tube. The electromagnetic field is thus completely contained within the
tube, and (ideally) no energy is lost to radiation or coupling outside the tube. Coaxial cables
have acceptably small losses for frequencies up to about 5 GHz. For microwave frequencies
greater than 5 GHz, the losses (due mainly to the electrical resistance of the central conductor)
become too large, making waveguides a more efficient medium for transmitting energy.
Coaxial cables with an air rather than solid dielectric are preferred as they transmit power with
lower loss.
c) Waveguides
Waveguides are similar to coax cables, as both consist of tubes, with the biggest
difference being that the waveguide has no inner conductor. Waveguides can have any
arbitrary cross section, but rectangular cross sections are the most common. Because
waveguides do not have an inner conductor to carry a return current, waveguides cannot
deliver energy by means of an electric current, but rather by means of
a guided electromagnetic field.
Although surface currents do flow on the inner walls of the waveguides, those surface
currents do not carry power. Power is carried by the guided electromagnetic fields. The
surface currents are set up by the guided electromagnetic fields and have the effect of keeping
the fields inside the waveguide and preventing leakage of the fields to the space outside the
waveguide.

Waveguides have dimensions comparable to the wavelength of the alternating current to be

transmitted, so they are only feasible at microwave frequencies. In addition to this mechanical
feasibility, electrical resistance of the non-ideal metals forming the walls of the waveguide
cause dissipation of power (surface currents flowing on lossy conductors dissipate power). At
higher frequencies, the power lost to this dissipation becomes unacceptably large.
d) Fiber optics
At frequencies greater than 200 GHz, waveguide dimensions become impractically

small, and the ohmic losses in the waveguide walls become large. Instead, fiber optics, which
are a form of dielectric waveguides, can be used. For such frequencies, the concepts of
voltages and currents are no longer used.
1.7 Mathematics of AC Voltages
Figure 1.2: Sine wave one cycle (360)

A sine wave, over one cycle (360°). The dashed line represents the root mean
square (RMS) value at about 0.707
Alternating currents are accompanied (or caused) by alternating voltages. An AC

voltage v can be described mathematically as a function of time by the following equation:
(1.3)

where
1. is the peak voltage (unit: volt),

2. is the angular frequency (unit: radians per second)
3. The angular frequency is related to the physical frequency, (unit = hertz), which
represents the number of cycles per second, by the equation .
4. is the time (unit: second).
5. The peak-to-peak value of an AC voltage is defined as the difference between its
positive peak and its negative peak. Since the maximum value of is +1 and the
minimum value is −1, an AC voltage swings between and . The
peak-to-peak voltage, usually written as or , is
therefore .
a) Power
The relationship between voltage and the power delivered is
…. (1.4)
Where represents a load resistance.
Rather than using instantaneous power, , it is more practical to use a time averaged power
(where the averaging is performed over any integer number of cycles). Therefore, AC voltage
is often expressed as a root mean square (RMS) value, written as , because
(1.5)
b) Power oscillation
(1.6)
(1.7)

(1.8)
By the following trigonometric identity, the power oscillation is double frequency of

the voltage.
(1.9)
c) Root mean square
For a sinusoidal voltage:
(1.10)
The factor is called the crest factor, which varies for different waveforms.
For a triangle waveform centered about zero
(1.11)
For a square waveform centered about zero
(1.12)
For an arbitrary periodic waveform of period :

(1.13)
Example
To illustrate these concepts, consider a 230 V AC mains supply used in many countries around
the world. It is so called because its root mean square value is 230 V. This means that the
time-averaged power delivered is equivalent to the power delivered by a DC voltage of 230 V.
To determine the peak voltage (amplitude), we can rearrange the above equation to: For 230 V
AC, the peak voltage is therefore , which is about 325 V.
1.8 Why Cascaded H-bridge multilevel inverter?
Cascaded H-Bridge (CHB) configuration has recently become very popular in high-
power AC supplies and adjustable-speed drive applications. A cascade multilevel inverter
consists of a series of H-bridge (single-phase full bridge) inverter units in each of its three
phases. Each H-bridge unit has its own dc source, which for an induction motor would be a
battery unit, fuel cell or solar cell. Each SDC (separate D.C. source) is associated with a
single-phase full-bridge inverter. The ac terminal voltages of different level inverters are
connected in series. Through different combinations of the four switches, S1-S4, each
converter level can generate three different voltage outputs, +Vdc, -Vdcand zero. The AC
outputs of different full-bridge converters in the same phase are connected in series such that
the synthesized voltage waveform is the sum of the individual converter outputs. Note that the
number of output-phase voltage levels is defined in a different way from those of the two
previous converters (i.e. diode clamped and flying capacitor). In this topology, the number of
output-phase voltage levels is defined by m= 2N+1, where N is the number of DC sources. A
seven-level cascaded converter, for example, consists of three DC sources and three full
bridge converters. Minimum harmonic distortion can be obtained by controlling the
conducting angles at different converter levels. Each H- bridge unit generates a quasi-square
waveform by phase shifting its positive and negative phase legs‟ switching timings. Each

switching device always conducts for 180° (or half cycle) regardless of the pulse width of the
quasi-square wave.
The combination of the 180° conducting method and the pattern-swapping scheme make
the cascade inverter‟s voltage and current stresses the same and battery voltage balanced.
Identical H-bridge inverter units can be utilized, thus improving modularity and
manufacturability and greatly reducing production costs. Battery-fed cascade inverter
prototype driving an induction motor at 50% and 80% rated speed both the voltage and current
are almost sinusoidal. Electromagnetic interference (EMI) and common mode voltage are also
much less than what would result from a PWM inverter because of the inherently low dv/dt
and sinusoidal voltage output.
The main advantages of using the cascade inverter in an induction motor include:
1. It makes induction motor more accessible/safer and open wiring possible for most of an
induction motor power system.
2. Traditional 230 V or 460 V motors can be used, thus higher efficiency is expected as
compared to low voltage motors.
3. No EMI problem or common-mode voltage/current problem exists.
4. Low voltage switching devices can be used.
5. No charge unbalance problem exists in both charge mode and drive mode.
Cascade inverters are ideal for an induction motor that has many separate dc sources
(batteries) available for the individual H-bridges, these inverters are not an option for series
hybrid induction motors because cascade inverters cannot be easily connected back-to-back.
For series-configured induction motors where an onboard combustion engine generates ac
power via an alternator or generator, a multilevel back-to-back diode clamped converter drive
can best interface with the source of ac power and yet still easily meet the high power and/or
high voltage requirements of the induction motor.
Induction motors generally have an ac voltage source from an alternator or combustion-engine
generator. A rectifier converts this ac voltage to dc for the electric energy storage devices on

board – batteries or ultra capacitors. An inverter converts the dc voltage to variable voltage
variable frequency ac in order to drive the main induction motor.
The multilevel converter can act as an inverter in drive mode when energy is being
sent to the motor that drives the wheels and as a rectifier during regenerative braking or during
charge mode when the vehicle is plugged into an external ac source.
The reduction in dv/dt can prevent motor windings and bearings from failure. The staircase
output voltage waveform approaches a sine wave, thus having no common-mode voltage and
no voltage surge to the motor windings.
A cascaded multilevel inverter is discussed to eliminate the excessively large number of
1. bulky transformers required by conventional multi pulse inverters,
2. clamping diodes required by multilevel diode-clamped inverters, and
3. flying capacitors required by multilevel flying-capacitor inverters.
Also, it has the following features:

1. It is much more suitable to high-voltage, high-power applications than the conventional
inverters.
2. It switches each device only once per line cycle and generates a multistep staircase voltage
waveform approaching a pure sinusoidal output voltage by increasing the number of levels.
3. Since the inverter structure itself consists of a cascade connection of many single-phase,
full-bridge inverter (FBI) units and each bridge is fed with a separate DC source, it does
not require voltage balance (sharing) circuits or voltage matching of the switching devices.
4. Packaging layout is much easier because of the simplicity of structure and lower
component count.
5. Soft-switching can be used in this structure to avoid bulky and lossy resistor-capacitor-
diode snubbers.
These advantages are our motivation to work on the harmonic analysis of cascaded three-level,
five-level & seven-level induction motor drives.

1.9 Dissertation Outline

This dissertation intends to analyze the performance and effectiveness of the CMC-based
Induction motor drives and it is divided into the following five chapters.
Chapter 1 discusses about the high frequencies ac power systems and discuss about the
advantages and disadvantages of cascaded multilevel inverter.
Chapter 2discuss about the different types of multilevel inverters and advantages and dis
advantages of multilevel inverters.
Chapter 3 discuses different aspects of modulation techniques which are required or desirable
for multilevel converters. Sine-triangle carrier modulation is identified as the most promising
technique to pursue for both technical and pedagogical reasons. Natural and uniform sampled
sine-triangle modulation are examined and contrasted in detail.
Chapter 4 discuss about the system description of cascaded multilevel inverter with switched
capacitor
Chapter 5 draws results and conclusion for this dissertation and proposes future work.
CHAPTER-2
MULTILEVEL INVERTER STRUCTURES

2.1 Introduction
A voltage level of three is considered to be the smallest number in multilevel converter

topologies. Due to the bi-directional switches, the multilevel VSC can work in both rectifier
and
Inverter modes. Three different major multilevel converter structures have been applied in
industrial applications: cascaded H-bridges converter with separate dc sources, diode clamped,
and flying capacitors. In a multilevel VSI, the dc-link voltage Vdc is obtained from any
equipment which can yield stable dc source. Each capacitor voltage Vc is given by Vc=Vdc/
(n-1), where n denotes the number of level. Two-level inverter generates an output voltage
with two levels with respect to the negative terminal of the capacitor, while the three-level
inverter generates three voltages, and so on.
Figure 2.1 One phase leg of an inverter with (a) two levels, (b) three levels, and (c) n
levels.
2.2 Diode-Clamped Multilevel Inverter
The most commonly used multilevel topology is the diode clamped inverter, in which
the diode is used as the clamping device to clamp the dc bus voltage so as to achieve steps in
the output voltage. A three-level diode clamped inverter consists of two pairs of switches and
two diodes. The DC bus voltage is split into three voltage levels by using two series
connections of DC capacitors, C1 and C2.

Table 2.1 Switching states in one leg of the three-level diode clamped inverter
Figure 2.2 Topology of the diode-clamped inverter (a) three-level inverter, (b) five-level
inverter.
Figure 2.3 Output voltage in three-level diode- clamped inverter (a) leg voltage (b)
output phase voltage

Figure 2.3 shows the phase voltage and line voltage of the three-level inverter in the
balanced condition. The line voltage Vab consists of a phase-leg a voltage and a phase-leg b
voltage. The resulting line voltage is a 5-level staircase waveform for three-level inverter and
9-level staircase waveform for a five-level inverter. This means that an N-level diode-clamped
inverter has an N-level output phase voltage and a (2N-1)-level output line voltage.
In general the voltage across each capacitor for an N level diode clamped inverter at
steady state is Vdc/ (N-1). Although each active switching device is required to block only a
voltage level of Vdc, the clamping diodes require different ratings for reverse voltage blocking.
In general for an N level diode clamped inverter, for each leg 2* (N-1) switching devices, (N-1)
* (N-2) clamping diodes and (N-1) dc link capacitors are required. By increasing the number
of voltage levels the quality of the output voltage is improved and the voltage waveform
becomes closer to sinusoidal waveform. However, capacitor voltage balancing will be the
critical issue in high level inverters. When N is sufficiently high, the number of diodes and the
number of switching devices will increase and make the system impracticable to implement. If
the inverter runs under pulse width modulation (PWM), the diode reverse recovery of these
clamping diodes becomes the major design challenge.
2.3 Operation of DCMLI
For dc-bus voltage Vdc, the voltage across each capacitor is Vdc/2 and each device
voltage stress will be limited to one capacitor voltage level Vdc/2 through clamping diodes.
To explain how the staircase voltage is synthesized, the neutral point n is considered as the
output phase voltage reference point. There are three switch combinations to synthesize three-
level voltages across a and n. To explain how the staircase voltage is synthesized, the neutral
point n is considered as the output phase voltage reference point.
1) Voltage level Van= Vdc/2, turn on the switches S1and S2.
2) Voltage level Van= 0, turn on the switches S2 and S1′ .
3) Voltage level Van= - Vdc/2 turn on the switches S1′,S2′.

Table 2.2 Switching states in one leg of the five-level diode clamped inverter
There are five switch combinations to synthesize five level voltages across a and n.
1) Voltage level Van= Vdc; turn on all upper switches S1 , S2 , S3 and S4.
2) Voltage level Van= Vdc/2, turn on the switches S2, S3, S4 and S1′.
3) Voltage level Van= 0, turn on the switches S3, S4, S1′ and S2′.
4) Voltage level Van= - Vdc/2 turn on the switches S4, S1′, S2′, S3′.
5) Voltage level Van= - Vdc; turn on all lower switches S1′, S2′ ,S3′ and S4′.
2.4 Features of Diode clamped MLI
2.4.1 High-Voltage Rating Required for Blocking Diodes
Although each active switching device is only required to block a voltage level of Vdc/
(m - l), the clamping diodes need to have different voltage ratings for reverse voltage blocking.
Using D1′ of Figure (5-level diode clamped inverter) as an example, when all lower devices,
S1′-S4′ are turned on, D1′ needs to block three capacitor voltages, or 3Vdc/4. Similarly, D2
and D2′ need to block 2Vdc/4, and D3 needs to block 3Vdc/4. Assuming that each blocking
diode voltage rating is the same as the active device voltage rating, the number of diodes
required for each phase will be (m - 1) x (m - 2).

This number represents a quadratic increase in m. When m is sufficiently high, the

number of diodes required will make the system impractical to implement.
2.4.2 Unequal Device Rating
It can be seen that switch S1 conducts only during Vao = Vdc, while switch S4
conducts over the entire cycle except during Vao = 0. Such an unequal conduction duty
requires different current ratings for switching devices. When the inverter design is to use the
average duty for all devices, the outer switches may be oversized, and the inner switches may
be undersized. If the design is to suit the worst case, then each phase will have 2 x (m - 2)
outer devices oversized between converters through transformers.
2.4.3 Capacitor Voltage Unbalance
In most applications, a power converter needs to transfer real power from ac to dc

(rectifier operation) or dc to ac (inverter operation). When operating at unity power factor, the
charging time for rectifier operation (or discharging time for inverter operation) for each
capacitor is different. Such a capacitor charging profile repeats every half cycle, and the result
is unbalanced capacitor voltages between different levels. The voltage unbalance problem in a
multilevel converter can be solved by several approaches, such as replacing capacitors by a
controlled constant dc voltage source such as pulse-width modulation (PWM) voltage
regulators or batteries. With the high power nature of utility power systems, the converter
switching frequency must be kept to a minimum to avoid switching losses and electromagnetic
interference (EMI) problems. When operating at zero power factor, however, the capacitor
voltages can be balanced by equal charge and discharge in one-half cycle. This indicates that
the converter can transfer pure reactive power without the voltage unbalance problem.

2.5 Advantages and Disadvantages of DCMLI.
Advantages:
1. The capacitors can be pre-charged as a group, when the number of levels is high enough,
harmonic content will be low enough to avoid the need for filters
2. Efficiency is high for fundamental frequency switching.
Disadvantages:
1. Real power flow is difficult for a single inverter because the intermediate dc levels will tend
to overcharge or discharge without precise monitoring and control.
2. The number of clamping diodes required is quadratically related to the number of levels,
which can be cumbersome for units with a high number of levels.
2.6 Conclusion
The diode-clamped inverter provides multiple voltage levels through connection of the
phases to a series of capacitors. The concept can be extended to any number of levels by
increasing the number of capacitors. The additional level was the neutral point of the dc bus,
so the terminology neutral point clamped (NPC) inverter was introduced. However, with an
even number of voltage levels, the neutral point is not accessible, and the term multiple point
clamped (MPC) is sometimes applied. Due to capacitor voltage balancing issues, the diode-
clamped inverter implementation has been limited to three level. Because of industrial
developments the three level inverter is now used.
2.7 Flying Capacitor Structure

Figure 2.4 Capacitor-clamped multilevel inverter circuit topologies, (a) 3-level inverter
(b) 5- level inverter.
The capacitor clamped inverter alternatively known as flying capacitor was proposed
by Maynard and Foch in 1992. The structure of this inverter is similar to that of the diode-
clamped inverter except that instead of using clamping diodes, the inverter uses capacitors in
their place.
The flying capacitor involves series connection of capacitor clamped switching cells. This
topology has a ladder structure of dc side capacitors, where the voltage on each capacitor
differs from that of the next capacitor. The voltage increment between two adjacent capacitor
legs gives the size of the voltage steps in the output waveform. Figure2.4 shows the three-level
and five-level capacitor clamped inverters respectively.
2.8 Operation of FCMLI
In the operation of flying capacitor multi-level inverter, each phase node (a, b, or c)
can be connected to any node in the capacitor bank (V3, V2, V1). Connection of the a-phase to
positive node V3 occurs when S1 and S2 are turned on and to the neutral point voltage when
S2 and S1′ are turned on. The negative node V1 is connected when S1′ and S2′are turned on.
The clamped capacitor C1 is charged when S1 and S1′ are turned on and is discharged when

S2 and S2′ are turned on. Provided that the voltage rating of each capacitor used is the same as
that of the main power switch, an N level converter will require a total of (N-1) * (N-2) / 2
clamping capacitors per phase in addition to the (N-1) main dc bus capacitors. Using Figure
2.4(b) as the example, the voltage of the five-level phase-leg „a‟ output with respect to the
neutral point n (i.e.Van), can be synthesized by the following switch combinations.
1) Voltage level Van= Vdc/2, turn on all upper switches S1 - S4 .
2) Voltage level Van= Vdc/4, there are three combinations.
a) Turn on switches S1 , S2 , S3 and S1′.(Van= Vdc/2 of upper C4‟s - Vdc/4 of C1‟s).
b) Turn on switches S2 , S3 , S4 and S4′.(Van= 3Vdc/4 of upper C3‟s - Vdc/2 of C4‟s).
c) Turn on switches S1 , S3 , S4 and S3′. (Van= Vdc/2 of upper C4‟s - 3Vdc/4 or C3‟s +
Vdc/2 of upper C2„)
3) Voltage level Van= 0, turn on upper switches S3 , S4 , and lower switch S1′, S2′.
4) Voltage level Van= -Vdc/4, turn on upper switch S1 and lower switches S1′, S2′and S3′.
5) Voltage level Van= -Vdc/2, turn on all lower switches S1′, S2′, S3′ and S4′.
2.9 Features of FCMLI
The major problem in this inverter is the requirement of a large number of storage
capacitors. Provided that the voltage rating of each capacitor used is the same as that of the
main power switch, an m-level converter will require a total of (m - 1) x (m - 2)/2 auxiliary
capacitors per phase leg in addition to (m - 1) main dc bus capacitors. With the assumption
that all capacitors have the same voltage rating, an m-level diode-clamp inverter only requires
(m - 1) capacitors. In order to balance the capacitor charge and discharge, one may employ
two or more switch combinations for middle voltage levels (i.e., 3Vdc/4. Vdc/2, and Vdc/4) in
one or several fundamental cycles.

2.10 Advantages and Disadvantages of (FCMLI)
Advantages
1. Added clamping diodes are not needed.
2. It has switching redundancy within the phase, which can be used to balance the flying
capacitors so that only one dc source is needed.
3. The large number of capacitors enables the inverter to ride through short duration
outages and deep voltage sags.
Disadvantages
1. Control is complicated to track the voltage levels for all of the capacitors.
2. Pre-charging all of the capacitors to the same voltage level and startup are complex.
3. Switching utilization and efficiency are poor for real power transmission.
2.11 Cascaded Multilevel Inverter
One more alternative for a multilevel inverter is the cascaded multilevel inverter or
series H-bridge inverter. The series H-bridge inverter appeared in 1975. The CMI synthesizes
its output nearly sinusoidal voltage waveforms by combining many isolated voltage levels. By
adding more H-bridge converters, the amount of Var can simply increased without redesign
the power stage, and build-in redundancy against individual H-bridge converter failure can be
realized. A series of single-phase full bridges makes up a phase for the inverter. A three-phase
CMI topology is essentially composed of three identical phase legs of the series-chain of H-
bridge converters, which can possibly generate different output voltage waveforms and offers
the potential for AC system phase-balancing.
Figure 2.5 Single phase structures of Cascaded inverter (a) 3-level, (b) 5-level, (c) 7-level
This feature is impossible in other VSC topologies utilizing a common DC link. Since
this topology consists of series power conversion cells, the voltage and power level may be
easily scaled. The dc link supply for each full bridge converter is provided separately, and this
is typically achieved using diode rectifiers fed from isolated secondary windings of a three-
phase transformer. Phase-shifted transformers can supply the cells in medium-voltage systems
in order to provide high power quality at the utility connection.
2.12 Operation of CMLI
The converter topology is based on the series connection of single-phase inverters with
separate dc sources. Figure 2.5 shows the power circuit for one phase leg of a three-level ,

five-level and seven-level cascaded inverter. In a 3-level cascaded inverter each single-phase
full-bridge inverter generates three voltages at the output: +Vdc, 0, -Vdc (zero, positive dc
voltage, and negative dc voltage). This is made possible by connecting the capacitors
sequentially to the ac side via the power switches. The resulting output ac voltage swings from
-Vdc to +Vdc with three levels, -2Vdc to +2Vdc with five-level and -3Vdc to +3Vdc with
seven-level inverter. The staircase waveform is nearly sinusoidal, even without filtering. For a
three-phase system, the output voltage of the three cascaded converters can be connected in
either wye (Y) or delta (Δ) configurations.
Figure 2.6 Three-phase 7-level cascaded multilevel inverter (Y-configuration)
2.13 Features of CMLI
For real power conversions, (ac to dc and dc to ac), the cascaded-inverter needs separate
dc sources. The structure of separate dc sources is well suited for various renewable energy
sources such as fuel cell, photovoltaic, and biomass, etc. Connecting separated dc sources
between two converters in a back-to-back fashion is not possible because a short circuit will
be introduced when two back-to-back converters are not switching synchronously.
2.14 Advantages and Disadvantages of CMLI

Advantages
1. The regulation of the DC buses is simple.
2. Modularity of control can be achieved. Unlike the diode clamped and capacitor
clamped inverter where the individual phase legs must be modulated by a central
controller, the full-bridge inverters of a cascaded structure can be modulated separately.
3. Requires the least number of components among all multilevel converters to achieve
the same number of voltage levels.
Disadvantages
1. Communication between the full-bridges is required to achieve the synchronization of
reference and the carrier waveforms.
2. Needs separate dc sources for real power conversions, and thus its applications are
somewhat limited
2.15 Conclusion
The aim of this chapter has been to demonstrate the multilevel converter topologies.
Each has its own mixture of advantages and disadvantages and for any one particular
application, one topology will be more appropriate than the others. Often, topologies are
chosen based on what has gone before, even if that topology may not be the best choice for the
application. The advantages of the body of research and familiarity within the engineering
community may out weight other technical disadvantages.
CHAPTER-3
MODULATION STRATEGIES

3.1 Introduction
Pulse Width Modulation (PWM) techniques for two level inverters have been studied
extensively during the past decades. Many different PWM methods have been developed to
achieve the following aims; wide linear modulation range, reduced switching loss, lesser total
harmonic distortion in the spectrum of switching waveform, easy implementation, less
memory space and computation time on implementing in digital processors for the proposed
work. The two most widely used PWM schemes for multi-level inverters are the carrier based
PWM techniques and the space vector based PWM techniques.
These modulation techniques are extensively studied and compared for the
performance parameters with two level inverters. The SPWM schemes are more flexible and
simple to implement, but the maximum peak of the fundamental component in the output
voltage is limited to 50% of the DC link voltage and the extension of the SPWM schemes into
over-modulation range is difficult. A space phasor based PWM scheme for multi-level
inverters use only the instantaneous amplitudes of reference phase voltages. The SVPWM
scheme 20 presented for multi-level inverters can also work in the over-modulation range,
using only the instantaneous amplitudes of reference phase voltages. In high power and high
voltage applications, the two level inverters, however, have some limitations in operating at
high frequency mainly due to switching losses, dv/dt and di/dt stresses in power
semiconductor devices and constraint of the semiconductor power device ratings. For high
voltage applications two or more power devices can be connected in series to achieve the
desired voltage ratings and in parallel to achieve the current ratings. Multilevel inverters can
increase the power by (m-1) times than that of two level inverter through the series connection
of power semiconductor devices.
This research focuses on the different control strategies and a suitable modulation
strategy is selected based on the outputs obtained through the simulations on the MATLAB
SIMULINK software environment.
3.2 Pulse-Width Modulation

Pulse width modulation is a method of controlling the output voltage of an inverter. In

this method a control signal is compared with a repetitive signal, typical a triangular signal. To
make the converter work in an inverter mode the control signal should have a sinusoidal shape.
This control signal can vary a bit and this will be discussed in. At a constant switching
frequency the time period of the triangular signal is also constant since this signal gives the
switching frequency.
…… (3.1)
The frequency of the control signal gives the frequency of the desired fundamental output
voltage. For a two-level converter there are two switches in one bridge leg and the upper
switch will be on when the control signal is greater than the triangular signal. If unipolar
switching is chosen the lower switch will be off when the upper is on, which means that it will
be off when the control signal is greater than the triangular signal. Switch number 2 will be on
when the control signal is lower than the triangular and hence the upper switch will be off.
This is shown in the Figure below.
Figure 3.1 PWM with bipolar switching pattern
The amplitude ratio is given as ..….. (3.2)

This ratio tells the value of the amplitude of the bridge leg voltage compared to UDC/2.
This parameter is a part of the control signals which are given in the equation below.
…… (3.3)
The other parameter that is important to be defined is the ratio between the frequency of the
control signal and the triangular signal.
…… (3.4)
It is common to divide the modulation strategies into two strategies and which one that is
preferred is depending on mf. In it is recommended to use synchronous modulation if mf is
lower or equal to 21 and asynchronous modulation if mf is above this value. The definition of
synchronous modulation is that mf is an integer, which gives that the control signal is sampled
at the same angles every fundamental period. With asynchronous modulation this should not
cause problems as long as mf is large. The application studied in this report is to be used in the
medium voltage range and the switching frequency will be in the area from 300 – 1100 Hz,
which indicates that synchronous modulation should be used. Having a low switching
frequency will increase the amplitude of the lower harmonics. This occurs because the
harmonic distortion has the greatest values around mf, 2mf, 3mf and so on, and since the
switching frequency is reduced mf is also reduced.
3.3 Space Vector PWM
Space vector PWM is a popular modulation method for converters, due to its low
harmonics and increased linear range up to a ma equal to 1.1547. The theory of space vector is
that phase A, B and C has a permanent position to each other in the vector space, phase shifted
with 120 degrees. This can be seen in Figure 3.1. Ua, Ub and Uc are varying as in equation
(3.10). For a two-level converter there exist eight switching states.

The reference voltage is defined as
……… (3.5)
A zero vector is when all the bridge legs are connected to the same point and all of the
line-to-line voltages are zero. The six non-zero vectors have all the same amplitude, but
different angles.. A three-level converter has 27 vectors that can be used to create the desired
voltage, with 19 different states, which can be seen in Figure 2.2.1.
Figure 3.2 Space vector diagram for a three-level converter
There are four different groups the vectors can be divided into, and within each group the
magnitude of the vectors are the same.
The overview of the vectors is given in Table 3.2
The vectors are the following

….... (3.6)
Where UDC is the DC-link voltage. There are a lot of vectors to choose among for a
three-level converter, and the normal way of solving this is to choose the three vector states
closest to the reference vector when using Space Vector modulation. The reason for this is that
the harmonic distortion will be the lowest with this choice. By doing this, the vector space can
be divided into 24 different sectors.
Figure 3.3 Overview of hexagons.
Here the vector space is divided into six new hexagons as shown in the Figure below.
When the correct sector has been found, the duty cycles of the vectors have to be calculated.
Finding the duty cycles for a three-level converter is more complicated than for a two-level.
As long as the reference vector stays within the six inner sectors, the duty cycles can be
calculated the same way as for a two-level, which is shown in Figure 3.3.

Figure 3.4 Duty cycle calculations for the six inner hexagons
Uloc Ua 200 201 222 111 000 211 100 210 221 110 212 101 Uref ref ζ 1 2 3 4 5 6
Figure 3.5 Duty cycle calculations outside the six inner hexagons
The equations are shown as the following
…… (3.7)
Tx is the duty cycle for the vector lagging the reference vector, while ty is the duty
cycle for the vector leading the reference vector. T0 is the duty cycle for the zero vectors. If
the reference vector is outside the six inner hexagons then one common method calculation the

on-times is making a local reference vector as shown in Figure3.4. The on-times will den be as
shown below
…..(3.13)
This is described more in detail. The switching pattern should be designed in a way
which minimizes the number of switching transitions. In this report the aim has not been to
minimize the number of switching transitions, but to be able to balance the DC-bus. Hence
there are several switching patterns that can be used. There are in total 7 vectors available if
the reference vector is inside the first sector among the six inner hexagons.
Figure 3.6 switching pattern for space vector modulation
This Figure is showing half of the switching sequences for a reference vector staying
inside sector 1 among the six inner hexagons. It is starting off with vector 000 and moving on
to 100 and so on, such that there is one switching transition between every new vector, for
instance not to use the order 000, 200, 100 and 210. With this switching pattern all the vectors
are being used, and the possibility of using the vector redundancy is maximized. At least
should either 000 or 222 be removed since they give the same state. Hence other methods
should be considered such that the switching losses may be reduced. The method that would
require the least amount of commutations having the reference vector inside sector 1 could be

222, 221, 211, 221 and 222 which is defined as modified space vector modulation according
to , while the classical method is 222, 221, 211, 111, 211, 221 and 222. Even though the
modified version has less switching transitions, it is concluded in that the method produces
more harmonics in the lower modulation area compared to classical space vector modulation,
and thus the classical version is preferred. The very clear disadvantage with this switching
scheme is that there is no possibility of DC-bus balancing. If it should be used with only one
DC-source then other vectors must be used in order to have some redundancy. In it is
suggested that there are two switching patterns that could be used alternatively. First 111, 211,
221 and 222, and the second alternative is 111, 110, 100 and 000.. Hence this last alternative
could be used if the correct conditions are present. If not, then at least one vector pair should
be used during one switching period. Then the switching pattern with the classical method
would look like 222, 221, 211, 111 and 110. This switching pattern improves the balancing
possibilities, but if the balancing algorithm should be optimized the switching pattern in
Figure3.5 has to be used, but 222 should be skipped.

CHAPTER-4
MULTILEVEL INVERTERS
4.1 INTRODUCTION
TRANSFORMERLESS Multi-Level Inverter (MLI) topologies are gaining importance

due to their advantages such as high efficiency, low switch count, low weight and reduced size.
However, removal of the transformer eliminates the galvanic isolation between the PV array
and the output load. Removal of galvanic isolation increases the leakage current
compromising the safety in PV systems. It has led to the development of various safety
standards for the PV systems, which restrict the value or magnitude of leakage current flow in
the PV system [1-5]. Apart from leakage current minimization, there is a continuously
increasing demand for high-quality power output to be fed into the gridfrom the PV system.
This requirement has led to the use of multi-level inverters (MLI) in the transformerless PV
systems. In literature, many topologies or configurations of MLIs [6-7] are proposed for the
minimization of leakage current for their application in the transformerless PV systems. These
configurations employ two methods for minimization of the leakage current [8]. One method
is based on maintaining the common-mode voltage (CMV) constant, while the other method is
based on the minimization of the high-frequency transitions in the terminal and common-mode
voltages.
One elegant solution based on maintaining a constant CMV is proposed by Zhang et al.
[9]. The given MLI configuration [9] consists of eight switches for the generation of three
levels in the output voltage. This topology reduces the switching losses but has the drawback
of high conduction losses during both turn-ON and zero voltage states. The given MLI
configuration has an asymmetric operation during each half-cycle of the fundamental
component of the grid voltage. The inherent asymmetry in each half-cycle causes a DC offset
in the MLI output voltage. Furthermore, the requirement of an additional number of switches
for more than three-level operation limits its application. Islam et al. [10] have proposed
another interesting transformerless PV MLI topology to reduce the leakage current by
maintaining CMV constant. This MLI topology uses six switches for the generation of three

levels in the inverter output voltage. This circuit configuration results in high switching and
conduction losses. Furthermore,
this MLI topology cannot be extended to more than three levels in the output voltage. Xiao et
al. [11] have proposed another efficient three-level MLI for the minimization of leakage
current by maintaining CMV constant. The given topology [11] has low conduction and
switching losses. However, this configuration suffers from the disadvantage of a high number
of device count. Another interesting topology with low switching losses based on constant
CMV is proposed by Jiet al. [12]. This MLI topology consists of six switches and two diodes.
Apart from resulting in high conduction losses, this topology is less amenable for an extension
to a higher number of levels in the output voltage.
Another important method to minimize the leakage current is by the elimination of high-
frequency voltage transitions in the CMV. One such interesting solution is proposed by
Buticchiet al. [13]. The authors have proposed a nine-level grid-tied PV MLI topology. This
MLI topology consists of eleven switches and four diodes. In this MLI, four switches in the
low voltage bridge are operated with high switchingfrequency, while the remaining switches
in the high voltage bridge are operated with the low switching frequency. For a proper
operation of this configuration [13], the balance of flying capacitor voltage Vfcis necessary.
Furthermore, the PV terminals in this MLI topology cannot be grounded. Based on a similar
concept, another good proposal is given by Hong et al. [14]. In this solution, the authors have
proposed single inductor dual buck full-bridge inverter for the generation of variable CMV at
low-frequency. The MLI topology requires six switches and two diodes. The switches in the
H-bridge are operated at a low switching frequency, while the bi-directional switch is operated
at a high switching frequency. However, details of extending the topology for a higher number
of levels is not explained in the paper [14].
From the above discussion, it is evident that there is a need for a generalized
transformerless PV MLI, with fewer semiconductor devices to achieve the objectives of high
efficiency and economy. It should also be ensured that the PV MLI should have its switching
and conduction losses optimized with a lower number of conducting switches during the zero
voltage state. Furthermore, the extension to the higher number of levels should be possible.
This paper proposes one such solution for the minimization of leakage current in

transformerless MLIs connected to PV systems. The pulse width modulation (PWM)

technique for the proposed MLI is also discussed in the paper. The analysis of PV terminal
and common-mode voltages using switching function is presented. This analysis leads to the
development of the proposed PWM technique, which prevents high-frequency voltage
transitions in the terminal voltage and CMV. Salient features of the proposed cascaded
multilevel inverter (CMLI) are:
1) The topology uses eight switches for the generation of five levels in the output voltage.
2) During the zero voltage state only one switch and one diode conduct.
3) In the proposed topology, four switches are operated at a low switching frequency, which
reduces the switching losses.
4) The dead band in PWM technique does not affect the common-mode voltage.
5) The proposed inverter can be easily cascaded to achieve more than five levels in the output.
Rest of the manuscript is organized into eight sections. Section II describes the
working principle and the operation for the proposed five-level grid-connected CMLI along
with the generalized structure. The details of the PWM technique employed with its
generalization for 2m+1 levels are explained in section III. Section IV gives the details of the
Maximum Power Point Tracking (MPPT) algorithm which can be applied to the proposed
five-level CMLI. This is followed by the analysis of terminal and common-mode voltages for
the proposed CMLI in section V. Section VI discusses the simulation results of the proposed
five-level grid-connected CMLI. Section VII shows the experimental results of the proposed
five-level and nine-level CMLI. Comparison of the proposed CMLI with the other existing PV
MLI topologies in the literature is presented in section VIII. The conclusions from the paper
are discussed in section IX.
4.2 OPERATION OF PROPOSED CASCADED FIVE-LEVEL MLI

The schematic circuit diagram of the proposed five-level CMLI for PV system is
shown in Fig. 4.1. The given configuration consists of two converters (Conv-1 and Conv-2).
Conv-1 is a half-bridge inverter comprising two switches Sx1 and Sx2. The Conv-2 comprises
of a highly efficient and reliable inverter configuration [15] with six switches (Sx3 to Sx8).
Among the six switches, four switches (Sx3 to Sx6) in Conv-2 constitute an H-bridge circuit.
The remaining two switches Sx7 and Sx8 in Conv-2 are bi-directional switches. The switches
in the Conv-1 are used to generate the voltage levels of VPV and VPV/2. When switch Sx1 is
turned ON, the voltage VPV is applied at the terminal n with respect to the terminal z.
Similarly, the terminal n
attains the voltage VPV/2 when switch Sx2 is turned ON. The switches Sx1 and Sx2 are
complementary in nature. The generated voltage levels at the terminal n of Conv-1 are given
as an input to the Conv-2. The Conv-2 generates the positive, negative and zero levels of
corresponding input voltage (voltage between the terminals n and z) across the load. The bi-
directional switches Sx7 and Sx8 provide the free-wheeling path during zero voltage state. The
output of the five-level CMLI is connected to the grid through an LCL filter as shown in Fig. 1
[16-18]. It consists of inverter side inductance Li, capacitance Cfand grid side inductance Lac.
The resistance Rd in the shunt branch of the filter is used as a damping resistor. The resistance
Racrefers to the grid side resistance, and the resistance Rgindicates resistance in the ground
path. The variable vac refers to instantaneous grid voltage. The variables Rpand Cprefer to the
parasitic resistance and capacitance in the PV system, respectively shown with dotted lines in
Fig. 1. The parasitic capacitance in PV system forms a resonant circuit with the filter
inductances [16]. The variables io, icand iacdenote the output current of five-level CMLI,
current flowing through shunt branch of the filter and the current flowing into the grid
respectively. The current ileakindicates the leakage current flowing from the PV array into the
ground through parasitic capacitance (see Fig. 1).
The proposed MLI topology contains four pairs of complementary switches (Sx1, Sx2),
(Sx3, Sx4), (Sx5, Sx6) and (Sx7, Sx8) in the proposed configuration. However, to minimize
the leakage current, the complementary switching is employed only for the two pairs of
switches (Sx1, Sx2) and (Sx7, Sx8).

Fig. 4.1. Proposed five-level grid-connected CMLI with PV and parasitic elements.
Avoiding complementary action for the other pairs of switches helps in isolating the
PV and the grid source during zero voltage state.
Fig. 4.2 shows the operation of the inverter in all its switching states. The inverter
output voltage vuvat different voltage levels with the corresponding switching states of all the
switches are shown in Table I. The inverter output voltage vuvattains the voltage levels +VPV
or –VPV when switch Sx1 is turned ON along with other inverter switches (Sx3, Sx6) or (Sx4,
Sx5) respectively as shown in Figs. 4.2(a) and 2(e). Similarly, the the voltage levels +VPV/2
or –VPV/2 are obtained at vuvwhen switch Sx2 is turned ON with the same switching
combinations as shown in Figs. 4.2(b) and 4.2(d). The most important feature to be noticed
during zero voltage state or free-wheeling stage is the isolation or disconnection between PV
source and the grid. The isolation between the PV source and the grid can be achieved by
turning OFF all the switches of H-bridge inverter as shown in Fig 4.2(c).
The turn-off state of four switches in H-bridge during zero voltage state results in the
isolation of PV source from the grid. The bi-directional switches Sx7 and Sx8 provide a free-
wheeling path for the inductor current during the turn-off period of a switching cycle. This
action helps in minimizing the leakage current flowing through the parasitic capacitance. As
there is no direct connection between the two sources, the PV terminal points (nodes x, y and z)
float and have undefined voltages. The float or undefined value restricts the terminal voltages

from becoming zero. Thus, high-frequency voltage transitions at the PV terminals are avoided.
In other words, the possibility of the flow of leakage current can be minimized. Also, in the
other intermediate states like switching between VPV/2 to VPV or vice-versa, again the same
principle can be used. The above action further helps in the minimization of the leakage
current in the PV system. The PWM technique for the proposed five-level CMLI is broadly
discussed in section III. The expression for the pole voltages vuz and vvzare given in (1) and (2)
respectively.
Similarly, the switch Sx1 is kept turned ON, during voltage transition between levels 0
to VPV. The inverter switch pair (Sx3, Sx6) is operated with a high switching frequency
during positive half-cycle, and it remains at the turn-OFF state during the negative half-cycle
of the inverter output voltage vuv. A similar operation is applicable to the other inverter switch
pair (Sx4, Sx5), which is operated with higher switching frequency during the negative half-
cycle.
The switches Sx7 and Sx8 are turned ON during positive and negative half cycles of the
output voltage vuvrespectively. The removal of complementary action from the pair of
switches (Sx3, Sx4) and (Sx5, Sx6) facilitates complete turn-OFF of the switches during each
half-cycle of the output voltage vuv. Thus, the proposed system has the advantage of reduced
switching losses, realizing to a highly efficient and reliable inverter configuration which may
result in higher efficiency.

Fig. 4.2. Single Phase five-level cascaded MLI for output voltage levels (a) +VPV (b) + VPV/2
(c) 0 (d) –VPV/2 (e) -VPV .
The generalized topology for 2m+1 levels can also be obtained for the proposed five-level
CMLI. The number of PV sources in CMLI is denoted by the term m. The value of m is
always an integral multiple of 2 (i.e., m =2, 4…). The extended version of the proposed CMLI
for 2m+1 levels is presented in Fig. 4. The generalized topology is obtained by cascading the
basic units consisting of half-bridge and H-bridge. The bi-directional switches are connected
in between the output terminals for the free-wheeling period. The proposed generalized 2m+1
level MLI is also compared with the half-bridge and full-bridge modular multi-level converter.
The half-bridge modular multi-level converter requires less number of switches when
compared to the proposed generalized 2m+1 level MLI. However, it is difficult to reduce or
minimize the flow of leakage current in the half- bridge modular multi-level converter. Also,
the number of electrolytic capacitors used at the input side of the half-bridge modular multi-
level converter is high compared to the proposed generalized 2m+1 level MLI. The proposed
MLI has a lesser device count when compared to the full-bridge modular multi-level converter
[19]. However, both can minimize the leakage current flowing through the PV system.

Fig. 4.3. Gate pulses for the switches corresponding to inverter output voltage.
4.3 PROPOSED PWM STRATEGY ALONG WITH GENERALIZED STRATEGY

FOR MINIMIZATION OF THE LEAKAGE CURRENT
The operation of the proposed PWM technique is explained by considering the given five-
level CMLI. The high-frequency transitions in the terminal voltages vxgand vygof five-level
CMLI are minimized using the proposed PWM technique. The suggested action can be
achieved by switching from VPV to 0 state or vice-versa instead of the switching from VPV to
VPV/2 state or vice-versa. Additionally, during the zero voltage state or free-wheeling period
of the switching cycle, the PV array is isolated from the grid. The isolation of the PV array and
the grid during zero voltage state is similar to the inverter configuration reported in [15]. The
magnitude of reference wave vmodis lowered to 50% of its original value whenever the

switching is toggled amongst the levels VPV and 0. The above action is mainly done to
accommodate the value of PV voltage VPV. The modification in the value of vmodis done
whenever the instantaneous magnitude of modulating wave vmodexceeds the value of ma/2,
where ma refers to the modulation index. By incorporating the desired modification, the
output voltage includes the zero voltage state (i.e., free-wheeling state) in all its switching
periods. The expression for modified reference waveform vref_modifiedis given in (3).
Fig.4.4. Generalized 2m+1 level MLI topology derived from proposed five-level CMLI.
where, vmod= ma sinωt gives the magnitude of vmod.
The output voltage of the proposed PWM technique for the five-level CMLI is shown in
Fig. 4.5. In Fig. 4.5 the modified reference wave is compared with the triangular carrier wave.
During the positive half-cycle of voltage vac, whenever the phase angle ωt lies in range 00 to

300 and the instantaneous magnitude of vref_modified exceeds the carrier wave, then
vuvattains the voltage level of VPV/2 otherwise, it is switched zero voltage state. Similarly,
when ωtlies in the range 300 to 1500, the inverter output voltage vuvattains the voltage level
of VPV whenever the instantaneous magnitude vref_modified exceeds the carrier wave or
attains zero value otherwise. In the same positive half-cycle, for the remaining range of ωt (i.e.,
between 1500 to 1800), vuvattains the voltage levels VPV/2 if the instantaneous magnitude of
vref_modifiedis greater than the carrier wave. A similar sequence is adopted during the
negative half-cycle of voltage vac. Thus, in the complete cycle if the magnitude of
vref_modifiedis less than the carrier wave, then vuvattains zero voltage level.
For the implementation of the proposed PWM to a 2m+1 level inverter, the waveform of
generalized modified reference wave vref_modified_genis shown in Fig. 6. The term m refers
to the number of PV sources used. Whenever the instantaneous absolute magnitude of
vmodexceeds the value j(ma/m), the magnitude of vref_modified_genbecomes k(|vmod|/m)
where j= 1, 2,… m-1, m and k = 1, 2, … m-1. The expression for the vref_modified_genis
given in (4).
Fig. 4.5. The waveform of output voltage vuvfor the proposed PWM technique.

4.4INTEGRATION OF MPPT FOR PROPOSED FIVE-LEVEL CMLI
Fig. 4.6. The waveform of generalized modified reference wave vref_modified_gen.
The well-known perturb and observe algorithm[20] is employed for the two PV sources
(considering five-level operation) individually to track Maximum Power Point (MPP). Thus,
each MPPT algorithm tracks the MPP for respective PV sources. To track the MPP, the
required information of (i) the average values of the two PV source voltages (VPV1 and VPV2
for the PV sources PV1 and PV2 respectively) and (ii) the currents (IPV1 and IPV2 for the PV
sources PV1 and PV2 respectively) are sensed and then given to their respective MPPT
algorithms. The MPPT algorithms then use the sensed values of the PV voltages and currents
for the calculation of the individual values of the modulation indices ma1 and ma2 for the two
PV sources PV1 and PV2 respectively. The outputs of two MPPT algorithms are then utilized
for the calculation of overall modulation index ma. The expression for ma is given in (5). The
calculated modulation index ma is then used by the PWM strategy as described in the above
section to generate the PWM pulses for the proposed five-level CMLI.

CHAPTER-5
5.1 INTRODUCTION
Power electronic converters play an important role in several applications for power
generation, storage, delivery and utilization as they acquire higher efficiency and performance.
However, power electronics have evinced high failure rates among system components that
put their reliability enhancement and lifetime prolongation of major concerns [1]. Power
semiconductor devices represent one of the critical elements that define the overall system
reliability and robustness [2]. According to [3], thermal stresses including high junction
temperature and large junction temperature cycling are the prime root causes of semiconductor
failures. In regards, several studies have been performed on reliability of semiconductor
devices related to thermal stresses such as failure mechanisms, lifetime models, and thermal
management techniques [4].
A generalized diagram of n-level full bridge T-type single phase inverters is shown in Fig. 5.1.
For any n-level T-type inverter, there are n-3 DC-link capacitors that create different output
voltage levels. Then, power semiconductor devices are controlled to output these voltage
levels to the load. Power semiconductor devices are usually subjected to continuous dynamic
loading that results from power and temperature cycling. These repeated loading in addition to
the large mismatch of coefficients of thermal expansion (CTE) of power semiconductor layers
cause thermo-mechanical fatigue in the form of bond wires lifting off and solder delamination
[5]. These ageing effects of power semiconductor devices gradually increase the equivalent
thermal resistance of the device, which is reported at failure to be about 20% above its normal
value. Then increased thermal stresses are expected that fasten the failure of the device. In
addition, ageing of the forced cooling system of power semiconductor devices can lead to the
same effects. Therefore, thermal stresses relief (TSR) of semiconductor devices is highly
required if increased thermal stresses have been detected in one of the power semiconductor
devices.

Several strategies of thermal stresses management and relief are provided in literature
[6]–[17]. Most of existing conventional strategies rely on derating of the output power [6] or
using costly cooling systems [7]. When the operating junction temperature of the
semiconductor device exceeds the predefined safety limit, the reference output current of the
inverter is reduced and the power losses through the affected device is reduced as a result [6].
A similar strategy for reliability improvement of PV inverters through limiting their maximum
feed power is introduced in [8]. However, in this technique, the tested inverter is not operated
with its full scale output power and the maximum power point (MPP) cannot be tracked
efficiently in renewable energy applications. On another side, the junction temperature of
semiconductor devices can be reduced by adding an additional forced cooling device between
the thermal grease of the device and the heatsink [7]. However, the added devices increase the
system cost and volume. Further, additional power is required to operate the cooling device.
Therefore, cost effective thermal stress relief methods for power semiconductor devices is
highly needed in order to minimize the wasted energy due to derating of the inverter and the
costly added cooling devices.
Fig 5. 1. A schematic diagram of PWM controlled full bridge n-level T-type inverter.

Another alternative method for thermal stresses relief of power semiconductor devices is
based on optimum design of modulation techniques of inverters. The pulse width of power
switches in interleaved converters is controlled to achieve balanced thermal stresses on IGBT
devices through percentage share of different interleaved modules [9]. However, full scale
components are needed for each interleaved module that increase dramatically the total system
cost in these methods.
The redundancies between the switching states of multilevel inverters represent

another cost effective solutions for thermal management of IGBT devices [10]. Nevertheless,
conventional neutral point clamped (NPC) inverters suffer from unequal loss distribution
among devices. Loss redistribution modulation techniques are developed to address this
problem [11]. Additionally, the active NPC inverters with modified modulation techniques are
developed to achieve losses and stresses reductions [11], [12]. However, the cost and the
number of IGBTs in active NPC inverters are high compared to conventional ones.
Discontinuous pulse width modulation (DPWM) techniques have been developed in literature
to improve the total efficiency of multilevel inverters by reducing switching transitions of
semiconductor devices [13], [14]. A DPWM method for power cycling reliability
improvement in NPC inverters is presented in [13]. However, these modulation techniques
cannot effectively provide thermal stresses relief for a particular semiconductor device if
increased thermal stresses have been detected. Furthermore, DPWM techniques provide
dissimilar thermal stresses on different system components.
The same concept with the same features is applied on space vector pulse width
modulation (SVPWM) method that is featured with more flexibility [15]. A higher efficiency
discontinuous SVPWM method is achieved through avoiding switching the leg with the
highest current [15]. Another SVPWM methods for lifetime extension of thermally-overheated
semiconductor devices are developed in [16], [17]. These methods provide thermal relief for a
particular semiconductor device without compromise of the inverter output ratings. However,
additional voltages stresses on power components are introduced to achieve voltage balance
over the DC-link capacitors. Moreover, the complexity of calculations and implementation of

SVPWM techniques increases at higher number of levels in order to define the operating
region and to calculate the dwelling times of voltage vectors.
Stimulated by the above-mentioned issues, a new carrier based thermal stresses relief PWM
(TSRPWM) strategy is proposed in this paper in order to alleviate thermally stressed
semiconductor devices in single phase multilevel inverters. The proposed algorithm provides
the benefits of: simple implementation without increased complexity at higher number of
levels; no need for output ratings compromise; cheap solution without extra system cost. In
addition, the proposed strategy ensures high performance regarding voltage balance of DC-
link capacitors of the multilevel inverter.
The paper is organized as follows: Section II explains the principles of thermal stress
relief and lifetime extension of power devices. Section III presents the operation of single
phase five level inverters. Section IV provides in details the proposed TSRPWM strategy and
its generalized implementation. The feasibility and simulation results of the proposed
TSRPWM strategy are investigated on five-level T-type inverter system in Section V. The
experimental prototype validation of the proposed strategy are given in Section VI. Section
VII provides performance criteria comparison of the proposed TSRPWM strategy with the
most featured methods in the literature. The conclusions are summarized in Section VIII.
5.2 THERMAL STRESSES AND LIFETIME EXTENSION
Several modulation techniques can be used to drive multilevel inverters, wherein power
semiconductor devices are subjected to different conduction times and switching transitions
for each particular modulation technique. Fig. 5.2(a) shows the relationship between different
models of semiconductor devices and modulation techniques. For the sake of accurate
modelling for power losses Plossthrough semiconductor devices, datasheet based losses
calculation methods are mostly preferred and the method in [18] is used in the paper. Then,
using thermal models of semiconductor devices, the operating junction temperature Tjand
junction temperature cycling ΔTjcan be obtained for the device as in (1) and (2) [19]:

where, Thdenotes to the operating heatsink temperature in Celsius, and Rth(i) and τth(i) represent
the thermal resistances and thermal time constant for ithlayer of the thermal model between the
junction and case of semiconductor device. Rth(c-h) represents the thermal resistance between
case and heatsink of the device. Whereas ton is the time of on-state of the power IGBT during
the output current fundamental period te.
The number of cycles to failure Nfrepresents a good measure for estimating the
expected lifetime for semiconductor devicesand can be modelled by the well-known Coffin-
Manson model as follows in (3) [19]:
whereα and A are constants that can be obtained from power cycling tests, Ea represents
activation energy and Kb represents Boltzmann constant. From (1), the main factors that affect
the lifetime of semiconductor devices are the thermal stresses over the device (Tjand ΔTj),
which are mainly affected by the power losses through the device on-state duration of the
output current of the inverter. The effect of thermal stress relief on the lifetime of
semiconductor devices is shown in Fig. 2(b) [20]. It is found that a small decrease of thermal
stresses leads to a great enhancement of the semiconductor device lifetime.
Fig. 5.3 shows a schematic diagram of a complete thermal relief system for IGBT device
SAxy(where x denotes to leg number 1, or 2, and y denotes the switch location 1, 2,… in the
leg) in the multilevel inverter. The thermal stresses relief (TSR) system for power
semiconductor devices has three main steps: 1) Estimating thermal stresses using thermo-
sensitive electrical parameters (TSEP) [21] for obtaining Tjand ΔTjof the device; 2) Applying
thermal stresses detection (TSD) algorithm of the device; 3) Activating thermal stresses relief

(TSR) algorithm. The recently developed thermo-sensitive electrical parameters (TSEP)

methods present a good solution to estimate the thermal stresses of semiconductor devices.
Then, the estimated Tjand ΔTjare fed to TSD system that compares the estimated Tjand
ΔTjwith the maximum operating
thermal stresses (Tj,limit, and ΔTj,limit), which are provided by devices’ manufacturers.
Finally, a flag representing thermal stresses relief enable (TSR_en(SAxy)) signal is fed to the
TSR algorithm to alleviate the thermal stresses of the affected device SAxy, where
TSR_en(SAxy) equals to 1 if TSR is required and 0 otherwise. In this paper, the problem of the
increased thermal stresses detection (TSD) has not been tackled. Additionally, it is emulated
and implemented by an external ON/OFF switch.
5.3 SINGLE PHASE FIVE LEVEL INVERTER OPERATION
Fig. 5.4 shows the power stage of single phase five level T-type inverter. Two equal DC-
link capacitors are used to generate the voltage levels, which are connected to the load through
the IGBT switches. Each leg of the inverter can generate either Vdc1, 0, or -Vdc2 with respect
to neutral point O by connecting the output to the inverter’s points P, O, or N, respectively.
Therefore, the two legs of the inverter are combined to generate five levels at the output of the
inverter that are +(Vdc1 + Vdc2), +Vdc1, 0, −Vdc2, and −(Vdc1 + Vdc2). The controller is
required to maintain voltage balance of the two DC-link capacitors (Vdc1 =Vdc2 =0.5Vdc),
and the output levels at this case will be (+Vdc, +0.5Vdc, 0, −0.5Vdc, and −Vdc).
The modulation technique is employed to generate various levels of the inverter output
voltage. Most common technique is the level shifted PWM modulation [22], where n-1
carriers are needed to generate n-levels at the output. The modulating signal and the carrier
signals for five-level inverters are shown in Fig.5.5. The gating signals for the IGBT switches
are generated by continual comparison of the modulating signal Vmwith the four carrier
signals Vcr1-Vcr4. According to the amplitude and polarity of the modulating signal Vm, the
line period of Vmis divided into six operating regions R1-R6 as clarified in Fig. 5. Two
different voltage levels are generated in each region. Fig. 5.6 shows the generated voltage

levels at each region R1-R6 of the inverter output. For instance, the voltage levels 0, and
0.5Vdc are generated in region R1 with dwelling times of t1 and t2, respectively.
Table I summarizes inverter switching combinations with their effects on the voltages of DC-
link capacitors for generating the output levels of the inverter (where ↑ represents charging
mode, ↓ represents discharging mode, and – represents no effects on capacitor voltages). It is

clear from Table I that each of +0.5Vdc, and -0.5Vdc voltage levels can be implemented by
using two different paths with different switch combinations and different effects on the
voltages of DC-link capacitors. Moreover, there are three different paths to implement zero
voltage level. Therefore, there are a degree of freedom to select different switches and
capacitors combinations to synthesize the output voltage levels, and of course extra freedom
can be obtained at higher n-levels inverters. This redundancy property can be utilized to
enhance the performance of multilevel inverters. The optimum selection of the redundant
states is employed to achieve different objectives such as voltage balance of DC-link
capacitors, reduction of THD in the outputs, reducing switching power losses, fault tolerant
operation, etc.

Fig 5. 2. Various models of power semiconductor device: (a) Relationship between

models, and (b) Nfversus Tjand ΔTj[20].
Fig 5. 3. Schematic diagram of the thermal stresses relief (TSR) system.
Fig 5. 4. Single phase full bridge T-type inverter system.

Fig 5. 5. Carrier-based PWM for single phase five level inverters.
Fig 5. 6. Output voltages of the inverter at regions: (a) R1 and R3, (b) R2, (c) R4 and R6,
and (d) R5.

5.4 THE PROPOSED STRATEGY
The aforementioned analysis of the redundancy property in multilevel inverters shows

the following degrees of freedom to optimize their performance: 1) thermal stress relief of
IGBT switches can be obtained by redistributing their power losses through proper selection
of redundant switching states; 2) the charge of DC-link capacitors can be balanced by
appropriately selecting the charge/discharge switching states. Accordingly, this paper proposes
a new lifetime extension method for alleviating thermally stressed semiconductor devices in
multilevel inverters. The proposed thermal stress relief PWM (TSRPWM) strategy is based on
carrier based PWM method. The proposed TSRPWM method can be explained as follows:
taking region R2 as an example and according to the required voltage levels in region R2 as in
Fig. 6(b) in addition to their required switch combinations as in Table I, there are two different
switching sequences in this region due to the existence of two different paths to generate
0.5Vdc voltage level. Fig. 5.7 shows the gating pulses for the two allowable switching
sequences, called Seq1, and Seq2 in region R2. It can be observed that different gating pulses
are applied in each sequence. For example, SA11 is held on in Seq1 for the switching period ts,
and it is subjected to only conduction losses as a result. Whereas in Seq2, it is switched on for
period t2 and turned off for period t1. Consequently, SA11 is subjected to conduction losses
during period t2 and switching losses due to on/off transitions. However, the total power
losses varies with different locations of the modulating signal Vmin line period and with
different modulation indices mi as well. The same analysis and observations can be done for
other switches and for other operating regions. In region R1, there are six switching sequences
can be obtained for synthesizing Vm, and different switch pulses are applied for each
switching sequence.
Therefore, if an increase of the thermal stresses in one of the IGBT devices SAxyhas
been detected (TSR_en(SAxy)=1), the proposed TSRPWM strategy is applied. Fig. 8 shows a
generalized flowchart for implementing the proposed TSRPWM strategy for n-level inverter.
Firstly, the modulating signal Vmis generated using the required modulation index (mi), and
line frequency fl. While, n-1 carrier signals Vcrare generated using the number of levels n and
the desired switching carrier frequency fc of the inverter. Secondly, the amplitude and sign of
Vmdefine the current operating region R. The desired output voltage levels is performed by
comparing the modulating signal Vmwith the n-1 carriers Vcr. Thirdly, the proposed algorithm
checks if there are any TSD in the IGBT switches (if TSR_en(SAxy)=1). Lastly, the proposed
algorithm has to properly select the redundant switching states that achieve the desired
performance and the operating mode of the inverter as it is explained in the following parts.
The inverter has two modes of operation under the proposed strategy namely: 1)
normal mode (NORM mode) of operation (if TSR_en(SAxy)=0); 2) thermal stress relief mode
(TSR mode) of operation (if TSR_en(SAxy)=1). In NORM mode, the redundant switching
states are selected so as to achieve voltage balance of DC-link capacitors. If Vdc1>Vdc2, the
switching states of C1 discharge are applied. In contrast, if Vdc2>Vdc1, the switching states
that discharge C2 are applied. In case of thermal.
TABLE I
SWITCH COMBINATIONS FOR DIFFERENT LEVELS OF FIVE LEVEL
INVERTER

Fig 5. 7. Gating pulses for IGBT switches in region R2 at: (a) Seq1, and (b) Seq2.
overstress detection TSD in one of the IGBT devices (TSR mode), the proposed algorithm
defines the m valid switching sequences in the current operating region R in the same way as
the aforementioned sequences in region R2. Afterwards, a cost function of the power losses
Ploss(SAxy) for the stressed IGBT device is implemented for all valid m switching
combinations. This calculations of Plosscan be implemented in parallel in FPGA
implementation in order to reduce the required execution time at higher n-level inverters due
to the increased number of redundant states. Lastly, the optimizer selects the optimum
switching combination of voltage levels that has the minimum power losses through the
thermally stressed device. In other regions of the line period that do not utilize the affected
device, the optimum switching sequence for achieving voltage balance of DC-link capacitors
is selected. The selected redundant switching states can provide thermal stresses relief to the
thermally-stressed IGBT devices and balance the voltages of DC-link capacitors in the same
line period. It can be realized from the implementation of the proposed TSRPWM strategy in
Fig. 5.8, its procedures are very easy and simple for hardware implantation compared to
thecomplex calculations in SVPWM techniques in [16], [17]. Moreover, the proposed
TSRPWM can achieve strong alleviation for the affected device by optimally selecting the
redundant switching states. The proposed strategy employs the redundant switching states and
hence it can preserve the same output ratings, the same number of output levels, and the same
output performance. In addition, the proposed strategy maintains the voltage balance over the
DC-link capacitors. The proposed TSRPWM method can be applied to different inverter
configurations and topologies.

CHAPTER -6
SIMULATION / MAT LAB RESULTS
Fig: 6.1 Block Diagram of XXXXXXXXXXXXXX
Fig: 6.2 Simulation Results of the proposed TSRPWM strategy TSD

Fig: 6.3 Simulation Results of the proposed TSRPWM strategy TSD in SA1
Fig: 6.4 Modulation Index M
6.5 Power Devices

6.6 Simulation Results of the Proposed TSRPWM Strategy at TSD in SA12 and mi=0.85

CHAPTER-7
CONCLUSION
This paper has proposed a new carrier-based modulation strategy, called TSRPWM, for
single phase multilevel inverters. It retains the same benefits as the conventional carrier PWM
methods, i.e., a simple and easy implementation, but presents a significantly reduced power
losses and thermal stresses of the stressed semiconductor devices. The main idea of the new
proposed strategy is adaptively selecting the redundant switching states in each switching
cycle, in order to optimize power losses through the thermally-stressed device. Therefore, both
of the junction temperature and temperature cycling of the stressed device are reduced by the
proposed strategy compared with normal mode operation of the device. The results of
simulation and experimental prototypes are conformed and verified the new proposed concept.
A generalized implementation of the proposed TSRPWM, to provide thermal stresses relief
for any of the components and for any n-level inverters, is also presented. Moreover, the
proposed strategy maintains the inverter operation with the same output ratings, and voltage
balance over DC-link capacitors. Finally, the performance of the proposed strategy is
compared with the prominent strategies in literature, and the distinction of the proposed
strategy has become clear.

FUTURE SCOPE
 Presents a significantly reduced power losses and thermal stresses of the

stressed semiconductor devices.
 It shows Adaptively selecting the redundant switching states in each switching
cycle, in order to optimize power losses through the thermally-stressed device.
 Temperature and temperature cycling of the stressed device are reduced by the
proposed strategy compared with normal mode operation of the device.
 A generalized implementation of the proposed TSRPWM, to provide thermal
stresses relief for any of the components and for any n-level inverters, is also
presented.

REFERENCES
[1] Shaoyong Yang, A. Bryant, P. Mawby, Dawei Xiang, Li Ran, and P. Tavner, “An
industry-based survey of reliability in power electronic converters,” IEEE Trans. Ind. Appl.,
vol. 47, no. 3, pp. 1441–1451, May 2011.
[2] S. E. De Leon-Aldaco, H. Calleja, and J. Aguayo Alquicira, “Reliability and mission
profiles of photovoltaic systems: a FIDES approach,” IEEE Trans. Power Electron., vol. 30,
no. 5, pp. 2578–2586, May 2015.
[3] B. Ji, X. Song, E. Sciberras, W. Cao, Y. Hu, and V. Pickert, “Multiobjective design
optimization of IGBT power modules considering power cycling and thermal cycling,” IEEE
Trans. Power Electron., vol. 30, no. 5, pp. 2493–2504, May 2015.
[4] U.-M. Choi, F. Blaabjerg, and K.-B. Lee, “Study and handling methods of power IGBT
module failures in power electronic converter systems,” IEEE Trans. Power Electron., vol. 30,
no. 5, pp. 2517–2533, May 2015.
[5] P. A. Mawby, W. Lai, H. Qin, O. Alatise, S. Xu, M. Chen, and L. Ran, “Study on the
lifetime characteristics of power modules under power cycling conditions,” IET Power
Electron., vol. 9, no. 5, pp. 1045–1052, Apr. 2016.
[6] D. A. Murdock, J. E. R. Torres, J. J. Connors, and R. D. Lorenz, “Active thermal control of
power electronic modules,” IEEE Trans. Ind. Appl., vol. 42, no. 2, pp. 552–558, Mar. 2006.
[7] C. Li, D. Jiao, J. Jia, F. Guo, and J. Wang, “Thermoelectric cooling for power electronics
circuits: modeling and active temperature control,” IEEE Trans. Ind. Appl., vol. 50, no. 6, pp.
3995–4005, Nov. 2014.
[8] Y. Yang, H. Wang, and F. Blaabjerg, “Improved reliability of single-phase PV inverters by
limiting the maximum feed-in power,” presented at the Proc. IEEE ECCE, Pittsburgh, PA,
2014, pp. 128–135.
[9] S. Dusmez and B. Akin, “An active life extension strategy for thermally aged power
switches based on pulse-width adjustment method in interleaved converters,” IEEE Trans.
Power Electron., vol. 31, no. 7, pp. 5149–5160, Jul. 2016.

[10] K. Ma and F. Blaabjerg, “Modulation methods for neutral-point-clamped wind power

converter achieving loss and thermal redistribution under low-voltage ride-through,” IEEE
Trans. Ind. Electron., vol. 61, no. 2, pp. 835–845, Feb. 2014.

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THERMAL STRESSES RELIEF CARRIER-BASED PWM

STRATEGY FOR SINGLE PHASE MULTILEVEL INVERTERS

A Project report submitted to Jawaharlal Nehru Technological University, Kakinada in partial

AMRITA SAI INSTITUTE OF SCIENCE AND TECHNOLOGY

Amrita Sai Nagar, Paritala, Krishna Dist – 521 180

Paritala, Kanchikacherla (Md), Krishna (Dist) – 521 180

Certified that this is a bonafide record of the Thesis work entitled,

Supervisor Head of department

B. JYOSHNA Mr.CH. CHINNA VEERAIAH M.Tech, LMISTE

I would like to express my sincere thanks to B. JYOSHNA, Assistant Professor ,

I would like to extend my heartful gratitude to MR.CHINNA VEERIAH, Head of the

My sincere regards to DR.M.SASIDHAR, The Principal, Amrita Sai Institute of

BH. V N S R GAYATRI SAI

I declare that the project report entitled “THERMAL STRESSES

BH. V N S R GAYATRI SAI

1.1:-Research Back Ground 2

1.2.high Frequency Ac Power Distribution System 4

1.3 Ac power Requirements 7

1.4 Effect of High Frequencies 8

1.5 Technique for reducing AC Resistence 9

1.6.Techniques for reducing Redaction Loss 9

1.7 Mathematics of AC Voltages 11

1.8.Why Cascaded H bridge multilevel inviter 14

1.9 Dissertation out line 17

Chapter -2 Multilevel inverter structures 18

2.2 Diode Clamped Multilevel inverter 18

2.3 Operation of DCMLI 20

2.4 Features of Diode Clamped MLI 21

2.5 Advantages and Disadvantages of DCMLI 23

2.8 Operation on FCMLI 24

2.9 Features of FCMLI 25

2.10 Advantages and Disadvantages of FCMLI 26

2.11 Cascaded Multilevel Inverter 27

2.12 Operation of CMLI 28

2.13 Features of CMLI 28

2.14 Advantages and Disadvantages of CMLI 29

Chapter -3 Modulation strategies 30

3.1 Modulation Strategies 30

3.2 Pulse width modulation 31

3.3. Space vector PWM 32

Chapter -4 Multilevel inverters 38

4.1. Transformer less Multilevel inverters 38

4.2 Operation of Proposed cascaded five level MLI 40

4.3 Proposed PWM Strategy with generalized strategy 45

for minimization of the leakage current

4.4 Integration of MPPT for praposed five level CMLI 48

5.2 thermal Stresses & Life time extension 52

5.3 Single Phase five level inviter Operation 54

Chapter -6 Simulation / MAT lab results 61

Table No. Name of Tables page No.

3.2 over view of the various is given 33

Fig No. Figure Names Page No.

1.1 High Voltage Transmission Lines 5

Enhancing power cycling capability of power semiconductor devices is highly

extending the lifetime of semiconductor switches in single-phase multilevel inverters. The

inverter system with considering different locations of thermal stresses detection.

modulation (PWM), thermal stresses relief.

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, ASIST 1

1.1 Research Background

As alternatives to effectively solve the above-mentioned problems, several circuit

2. Common-mode (CM) voltage: Multilevel converters produce smaller CM voltage;

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, ASIST 3