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Chapter 4 Combinational Circuit
Chapter 4 Combinational Circuit
Chapter 4 Combinational Circuit
Sileshi A.
(sileshi120@gmail.com) 2021/2022
0
Combinational Logic
• Logic circuits for digital systems may be combinational or
sequential.
• Block diagram:
Combinatorial
Logic
Circuit
Combinational
n inputs • • m outputs
• Circuits •
• •
•
Combinational logic circuits contain no memory (no ability to store
information)
2
Basic Combinational Logic Circuits
AND-OR LOGIC
Represents SOP implementation – AND gate for product term, OR gate for summing the
product terms
3
Basic Combinational Logic Circuits
AND-OR-INVERT LOGIC
Represents POS implementation – AND gate for product term, OR gate for
summing the product terms, NOT gate to complement the AND-OR circuit.
4
Basic Combinational Logic Circuits
XOR LOGIC
AB AB A B
5
Basic Combinational Logic Circuits
XOR LOGIC
A B AB (A B)(A B) A B AB A B
7
Universal Property - NAND & NOR
NAND GATE AS A UNIVERSAL LOGIC ELEMENT
NAND gate is a universal gate because it can be used to produce the NOT,
AND, OR and NOR functions.
8
Universal Property - NAND & NOR
NAND GATE AS A UNIVERSAL LOGIC ELEMENT (OR & NOR Gate)
9
Universal Property - NAND & NOR
NOR GATE AS A UNIVERSAL LOGIC ELEMENT
NOR gate is also a universal gate because it can be used to produce the NOT,
AND, OR and NAND functions.
10
Universal Property - NAND & NOR
NOR GATE AS A UNIVERSAL LOGIC ELEMENT (Cont.)
11
Universal Property - NAND & NOR
NAND LOGIC
NAND Gate can function as either a NAND or a negative-OR because by
DeMorgan’s Theorem:
AB = A + B
NAND Negative-OR
The NAND symbol and the negative-OR symbol are called dual-symbol.
12
Universal Property - NAND & NOR
NOR LOGIC
NOR Gate can function as either a NOR or a negative-AND because by
DeMorgan’s Theorem:
A+ B = A B
NOR Negative-AND
The NOR symbol and the negative-AND symbol are called dual-symbol.
13
Universal Property - NAND & NOR
Example:
Using appropriate dual symbols, redraw the logic diagram and develop the
output expression for the following circuit:
14
Universal Property - NAND & NOR
Exercise: Implement each expression with NAND logic using appropriate dual
symbols:
Combinational Logic: Analysis and Design
Analysis
● Given a circuit, find out its function
● Function may be expressed as: A
B
C
F1
?
♦ Boolean function A
B
C
♦ Truth table A
B
A
F2
C
?
Design B
C
16
Analysis Procedure
1. Label all gate outputs that are a function of input variables with arbitrary
symbols. Determine the Boolean functions for each gate output.
2. Label the gates that are a function of input variables and previously
labeled gates with other arbitrary symbols. Find the Boolean functions for
these gates.
3. Repeat the process outlined in step 2 until the outputs of the circuit are
obtained.
17
Analysis Procedure
A =0 0 0
F2
C =0
B =0 0
C =0
19
Analysis Procedure
A =0 0 0
F2
C =1
B =0 0
C =1
20
Analysis Procedure
A =0 0 0
F2
C =0
B =1 0
C =0
21
Analysis Procedure
A =0 0 1
F2
C =1
B =1 1
C =1
22
Analysis Procedure
A =1 0 0
F2
C =0
B =0 0
C =0
23
Analysis Procedure
A =1 1 1
F2
C =1
B =0 0
C =1
24
Analysis Procedure
B =1 0
C =0
25
Analysis Procedure
F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC
26
Designing procedures of Combinational circuit
27
Example 1
Design a circuit to convert a “BCD” code to “Excess 3” code
4-bits 4-bits
?
0-9 values Value+3
● Transforms BCD code for the decimal digits to Excess-3 code for the
decimal digits
● BCD code words for digits 0 through 9: 4-bit patterns 0000 to 1001,
respectively
● Excess-3 code words for digits 0 through 9: 4-bit patterns consisting of
3 (binary 0011) added to each BCD code word
● Implementation:
♦ multiple-level circuit
♦ NAND gates (including inverters)
28
Example 1 …
30
Example 1 …
A
W
B X
C Y
D
Z
31
Example 2
BCD-to-Seven-Segment Decoder
7-Segment display
BCD
code BCD to 7-
segmant
Decoder
Display
32
Design Example 2 – Assignment 2
Seven-Segment Decoder a
w x y z abcdefg
w a
0 0 0 0 1111110 b
0 0 0 1 0110000 x c f b
? d g
0 0 1 0 1101101 y e
0 0 1 1 1111001 z f
g
0 1 0 0 0110011 e c
0 1 0 1 1011011 BCD code
0 1 1 0 1011111
0 1 1 1 1110000 y d
1 0 0 0 1111111 1 1 1
1 0 0 1 1111011 1 1 1
1 0 1 0 xxxxxxx x x x x
x
1 0 1 1 xxxxxxx w 1 1 x x
1 1 0 0 xxxxxxx z
1 1 0 1 xxxxxxx
1 1 1 0 xxxxxxx a = w + y + xz + x’z’ b=...
c=...
1 1 1 1 xxxxxxx
d=...
33
Arithmetic Circuit Design
• Arithmetic Circuits
• Adder
• Subtractor
• BCD Adder
• Multiplier
34
Binary Adder
Logic Diagram
35
Binary Adder
Full Adder
A combinational circuit that adds 3 input bits to generate a Sum
bit and a Carry bit x S
y FA
z C
X Y Z C S
0 0 0 0 0 S = X’Y’Z + X’YZ’
+ XY’Z’ +XYZ
0 0 1 0 1
= (X Y) Z
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1 C = XY + YZ + XZ
C = XY + (X ⊕ Y)Z
36
Binary Adder
37
Binary Adder
x S
Full Adder y C
x S
y HA HA
z C
x
S
Think of y
Z as a C
carry in
z
38
Multi bit Adders: Parallel Adders
1 0 0 0
0101
0110
1011
39
Parallel Adders
x3x2x1x0 y3y2y1y0
c3 c2 c1 .
+ x3 x2 x1 x0
Carry + y3 y2 y1 y0
Cy Binary Adder C0 Propagate ────────
Addition Cy S3 S2 S1 S0
S3S2S1S0
x3 x2 x1 x0
y3 y2 y1 y0
0
FA FA FA FA
C4 C3 C2 C1
S3 S2 S1 S0
40
Binary Adder
x7 x6 x5 x 4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0
A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0
Cy CPA C0 Cy CPA C0 0
S3 S2 S1 S0 S3 S2 S1 S0
S7 S6 S5 S4 S3 S2 S1 S0
41
BCD Adder
When adding two BCD numbers, the maximum result that can
be obtained is:
9 + 9 = 18
● If we include a carry in bit, then the maximum result that can be
obtained is: 19 (10011)
● Both numbers 18 and 19 are invalid BCD digits. Therefore, a 6 needs to
be added to bring them to correct BCD format.
42
BCD Adder
0+9 0 0 0 0 1 0 0 1 =9 0 1 0 0 1
1+0 0 0 0 1 0 0 0 0 =1 0 0 0 0 1
1+1 0 0 0 1 0 0 0 1 =2 0 0 0 1 0
1+8 0 0 0 1 1 0 0 0 =9 0 1 0 0 1
1+9 0 0 0 1 1 0 0 1 =A 0 1 0 1 0 Invalid Code
2+0 0 0 1 0 0 0 0 0 =2 0 0 0 1 0
9+0 1 0 0 1 0 0 0 0 =9 0 1 0 0 1 0 0 0 0 1 0 0 1 =9
9+1 1 0 0 1 0 0 0 1 = 10 0 1 0 1 0 0 0 0 1 0 0 0 0 = 16
9+2 1 0 0 1 0 0 1 0 = 11 0 1 0 1 1 0 0 0 1 0 0 0 1 = 17
9+3 1 0 0 1 0 0 1 1 = 12 0 1 1 0 0 0 0 0 1 0 0 1 0 = 18
9+4 1 0 0 1 0 1 0 0 = 13 0 1 1 0 1 0 0 0 1 0 0 1 1 = 19
9+5 1 0 0 1 0 1 0 1 = 14 0 1 1 1 0 0 0 0 1 0 1 0 0 = 20
9+6 1 0 0 1 0 1 1 0 = 15 0 1 1 1 1 0 0 0 1 0 1 0 1 = 21
9+7 1 0 0 1 0 1 1 1 = 16 1 0 0 0 0 0 0 0 1 0 1 1 0 = 22
9+8 1 0 0 1 1 0 0 0 = 17 1 0 0 0 1 0 0 0 1 0 1 1 1 = 23
9+9 1 0 0 1 1 0 0 1 = 18 1 0 0 1 0 0 0 0 1 1 0 0 0 = 24
+6
44
BCD Adder
A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 0
Err = S3 S2 + S3 S1 S3 S2 S1 S0
A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 0
S3 S2 S1 S0
Cy S3 S2 S1 S0
46
Binary Subtractor
A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 1
S3 S2 S1 S0
F3 F2 F1 F0
47
Binary Adder/Subtractor
How to build a circuit that performs both addition and subtraction?
A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci
S3 S2 S1 S0
F3 F2 F1 F0
48
Binary Multiplication
B1 B0
x A1 A0
----------------
This operation is an
A0B1 A0B0 addition, requires an
A1B1 A1B0 + ADDER
----------------------------------
C3 C2 C1 C0
49
Binary Multiplication
50
Binary Multiplication
4-bit by 3-bit binary multiplier
For J multiplier bits and K
multiplicand bits we need
(J x K) AND gates and
(J − 1) K-bit adders to
produce a product of J+K bits.
51
Magnitude Comparator
Compare 4-bit number to 4-bit number
● 3 Outputs: < , = , >
The equality of each pair of bits can be expressed logically with an
exclusive-NOR function.
● Expandable to more number of bits
x A B A B
3 3 3 3 3
A3A2A1A0 B3B2B1B0
x2 A2 B2 A2 B2
Magnitude
x1 A1 B1 A1 B1 Comparator
x0 A0 B0 A0 B0
A<B A=B A>B
( A B) x3 x2 x1 x0
( A B) A3 B3 x3 A2 B2 x3 x2 A1 B1 x3 x2 x1 A0 B0
( A B) A3 B3 x3 A2 B2 x3 x2 A1 B1 x3 x2 x1 A0 B0
52
Magnitude Comparator
A3
x3
B3
A2
x2
Logic Symbol
B2
A1 (A<B)
x1
B1
A0
x0 (A>B)
B0
(A=B)
53
Magnitude Comparator
x7 x6 x5 x4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0
A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0
0 I(A>B) I(A>B)
1
Magnitude Magnitude
I(A=B) I(A=B)
I(A<B)
Comparator I(A<B)
Comparator
0
A<B A=B A>B A<B A=B A>B
54
Decoders
Decoding - the conversion of an n-bit input code to an m-bit
output code with n m 2n such that each valid code word
produces a unique output code
Circuits that perform decoding are called decoders
Decoders Extract “Information” from the code
Here, functional blocks for decoding are
● called n-to-m line decoders, where m 2n, and
● generate 2n (or fewer) SOP for the n input variables
A D0 D1
D0 5 A
1-to-2-Line Decoder 0 1 0
1 0 1 A D1 5 A
(a) (b) 55
Decoder Examples
A D0 D1
1-to-2-Line Decoder D0 5 A
0 1 0
1 0 1 A D1 5 A
(a) (b)
2-to-4-Line Decoder A0
A1 A0 D0 D1 D2 D3
A1
0 0 1 0 0 0 D0 5 A 1 A 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1 D1 5 A 1 A 0
(a)
D2 5 A 1 A 0
Note that the 2-4-line
made up of 2 1-to-2- D3 5 A 1 A 0
line decoders and 4 AND gates.
(b)
56
Decoder Examples
Decoder y3
I1
Binary
y2
y1
I0 y0 Note that the 2-
4-line made up of
2 1-to-2- line
decoders and 4
I1 I0 Y3 Y2 Y1 Y0 AND gates.
0 0 0 0 0 1
0 1 0 0 1 0 Y3 I1 I 0 Y2 I1 I 0
1 0 0 1 0 0
Y1 I1 I 0 Y0 I1 I 0
1 1 1 0 0 0
57
Decoder Examples
0 1
x1 0
Binary
x0 0 Decoder 0
0
58
Decoders
Y6 I 2 I1 I 0
Y7 Y5 I 2 I1 I 0
Y6
Y5 Y4 I 2 I1 I 0
Decoder
Binary
I2 Y4 Y3 I 2 I1 I 0
I1 Y3
I0 Y2 Y2 I 2 I1 I 0
Y1 Y1 I 2 I1 I 0
Y0
Y0 I 2 I1 I 0
I2
I1
I0
59
Decoders with enable
X
F
EN
(a)
X
F
EN 60
Decoders with enable
“Enable” Control Y3
Y3
Decoder
I1 Y2
Binary Y2
I0 Y1
E Y1
Y0
Y0
E I1 I0 Y3 Y2 Y 1 Y0
0 x x 0 0 0 0
I1
1 0 0 0 0 0 1 I0
E
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
61
Decoders with enable
D0
Demultiplexer D1
E
D2
D3
62
3-to-8 decoder with enable implement the 4-to-16
decoder
63
Exercise
Solution
64
Implementation of a Full Adder with a Decoder
From the table, we obtain the functions for the combinational circuit in sum of
minterms (SOP):
S(x, y, z) = x’y’z + x’yz’+xy’z’+ xyz
C(x, y, z) = x’yz+xy’z + xyz’ + xyz
65
Encoders
• Encoding - the opposite of decoding - the conversion of an m-bit input
code to a n-bit output code with n m 2n such that each valid code
word produces a unique output code
• Circuits that perform encoding are called encoders
• An encoder has 2n (or fewer) input lines and n output lines which
generate the binary code corresponding to the input values
• Typically, an encoder converts a code containing exactly one bit that
is 1 to a binary code corresponding to the position in which the 1
appears.
• An encoder is a circuit that changes a set of signals into a code
• Put “Information” into code
66
Encoder / Decoder Pairs
Binary Binary
Encoder Decoder
I7 Y7
I6 Y6
I5 Y5
Y2 I2 Y4
I4 Y1 I1 Y3
I3 Y0 I0 Y2
I2
I1 Y1
I0 Y0
67
Encoder Example
A decimal-to-BCD encoder
● Inputs: decimal digits 0 to 9, (D0, …, D9)
● Outputs: 4 bits with BCD codes
● Function: If input bit Di is a 1, then the output (A3, A2,
A1, A0) is the BCD code for i,
The truth table could be formed, but alternatively, the
equations for each of the four outputs can be obtained
directly.
68
Encoders Example
x1
x3 x2 x1 y1 y 0
x2 y1 0 0 0 0 0
Binary
Encoder 0 0 1 0 1
y0 0 1 0 1 0
x3
1 0 0 1 1
69
Encoders Example
Encoder
0 0 0 0 0 0 0 1 0 0 0 Y2
Binary
0 0 0 0 0 0 1 0 0 0 1 I4 Y1
0 0 0 0 0 1 0 0 0 1 0 I3 Y0
0 0 0 0 1 0 0 0 0 1 1 I2
0 0 0 1 0 0 0 0 1 0 0 I1
0 0 1 0 0 0 0 0 1 0 1 I0
0 1 0 0 0 0 0 0 1 1 0 I7
1 0 0 0 0 0 0 0 1 1 1 I6 Y2
I5
Y2 I 7 I 6 I 5 I 4 I4
I3 Y1
Y1 I 7 I 6 I 3 I 2 I2
I1
Y0 I 7 I 5 I 3 I1 I0 Y0
70
Priority encoder
71
Priority encoder
72
4-input priority encoder
Implementation
0
0
0
0
x = D2 + D3
y = D3 + D1D’2
V = D0 + D 1 + D 2 + D 3
73
Multiplexers
74
Multiplexers
S1 S0 Y I0
0 0 I0 I1
MUX Y
0 1 I1 I2
1 0 I2 I3
S1 S0
1 1 I3
75
2-to-1 Line Multiplexer
The equation:
Y = S I0 + SI1 Decoder
Enabling
Circuits
The circuit:
I0
Y
S
I1
76
Multiplexers
2-to-1 MUX
I0
I0 Y
MUX Y
I1 I1
S
S
I0
4-to-1 MUX I1
Y
I0 I2
I1 I3
MUX Y
I2
I3
S1 S0
S1 S0
77
Cascading Multiplexers
Example:
0 1
1 2
0 3
● F(A,B,C) =A'B'C' + A'BC' + ABC' + ABC 0 4 8:1 MUX F
0 5
1 6
1 7
S2 S1 S0
A B C 79
Multiplexers as General-purpose Logic (cont’d)
81
DeMultiplexers
• Receives information on a single line & transmits it to one of 2n possible output
lines.
Y3
Y2
I DeMUX Y
1
S S Y0
1 0
Y3
Y2
S1 S0 Y3 Y2 Y1 Y0
I
Y1
0 0 0 0 0 I
0 1 0 0 I 0
Y0
1 0 0 I 0 0
S1
1 1 I 0 0 0
S0 82
Multiplexer / DeMultiplexer Pairs
MUX DeMUX
I7 Y7
I6 Y6
I5 Y5
I4 Y4
Y I Y3
I3
I2 Y2
I1 Y1
I0 Y0
S2 S1 S0 S2 S1 S0
Synchronize
x2 x1 x0 y2 y1 y0
83
DeMultiplexers / Decoders
Y3 Y3
Decoder
I1
Binary
Y2 Y2
I DeMUX Y I0 Y1
1
E Y0
S S Y0
1 0
E I1 I0 Y3 Y2 Y1 Y0
S1 S0 Y3 Y2 Y1 Y0 0 x x 0 0 0 0
0 0 0 0 0 I 1 0 0 0 0 0 1
0 1 0 0 I 0 1 0 1 0 0 1 0
1 0 0 I 0 0 1 1 0 0 1 0 0
1 1 I 0 0 0 1 1 1 1 0 0 0
84
Demultiplexers as General-purpose Logic
0 A'B'C'
1 A'B'C demultiplexer generates appropriate
2 A'BC'
3 A'BC minterm based on control signals
“1” 3:8 DEC 4 AB'C' (it "decodes" control signals)
5 AB'C
6 ABC'
7 ABC
S2 S1 S0
A B C
85
Demultiplexers as General-purpose Logic
A BC D
86
DLD Assignment from Chapter 4 (individual)
1. Construct a binary full adder using a multiplexer.
2. Construct a 16 X 1 multiplexer by using five 4x 1 multiplexers. Use block diagrams.
3. Design a combinational circuit that converts a 4-bit gray code to a 4-bit binary number. Implement the
circuit using exclusive-OR gates.
4. Construct a 16 x1 multiplexer with two 8 x1 and one 2 x1 multiplexers. Use block diagrams
5. Construct a 16 x1 multiplexer with four 4 x1 and 3 2 x1 multiplexers. Use block
diagrams and logical diagrams
6. Implement the following Boolean function with a 4 x 1 multiplexer:
7. F (A, B, C, D) = Σ (0, 1, 3, 4, 8, 9, 15)
8. Design a 4-bit by 4-bt binary multiplier combinational circuit.
9. Design a 4-bit by 5-bt binary multiplier combinational circuit.
10. Design a 4-bit magnitude comparator combinational circuit .
11. Design an 8-bit parallel adder using a Full Adder. Use block diagrams and logical
diagrams
12. Design an 8-bit parallel adder using a Full Adder. Use block diagrams and logical
diagrams