ANALOG CIRCUITS LAB (18ECL48) Manual 2021-22-STUDENT

Analog Circuits Lab – 18ECL48
LAB INCHARGE: SRINIVASAMURTHY R, Asst. Professor
STAFF INCHARGE: KRISHNA R, Associate Professor
MANASA P, Asst. Professor
SEMESTER: IV ECE: 2021-2022
(Approved by AICTE, New Delhi & affiliated to VTU, Belagavi)
Dept. of ECE, BIT

DEPARTMENT OF ELECTRONICS & COMMUNICATION
ENGINEERING
PROFILE OF THE LABORATORY
Name of the Laboratory : Analog Circuits Lab(18ECL48)
Semester / Year : IV / 2022
No. of Students/Batch : 20
No. of Equipments : 202
Major Equipments : Oscilloscopes, Function Generators,

Multimeters, Power Supply,
LCR Meters, Computers, Digital IC
trainers.
Area in square meters : 105.448 Sq. m
Location : 4th Floor
Total Cost of Lab : Rs. 15,95,865.00
Lab In Charge : Srinivasamurthy R,

Assistant Professor
Lab staff : Nirmala N, Gururaj L,

Raju N, Range Gowda M V
HOD : Dr. A.R. HEMANTH KUMAR

BANGALORE INSTITUTE OF TECHNOLOGY
BENGALURU
VISION
To Establish and Develop the Institute as a center of higher
learning, ever abreast with expanding horizon of knowledge
in the field of Engineering and Technology, with
Entrepreneurial thinking, Leadership Excellence for life-long
success and solve societal problem.
MISSION
 Provide high quality education in the Engineering

disciplines from the undergraduate through doctoral
levels with creative academic and professional
programs.
 Develop the Institute as a leader in Science,

Engineering, Technology and management, Research
and apply knowledge for the benefit of society.
 Establish mutual beneficial partnerships with industry,

alumni, local, state and central governments by public
service assistance and collaborative research.
 Inculcate personality development through sports,

cultural and extracurricular activities and engage in the
social, economic and professional challenges.
DEPARTMENT OF ELECTRONICS
AND
COMMUNICATION ENGINEERING
VISION
Imparting Quality Education to achieve Academic

Excellence in Electronics and Communication
Engineering for Global Competent Engineers.
MISSION
 Create state of art infrastructure for quality education.

 Nurture innovative concepts and problem-solving skills.
 Delivering Professional Engineers to meet the societal
PROGRAMME
needs. EDUCATIONAL OBJECTIVES (PEOs)
PEO1 Prepare graduates to be professionals, practicing engineers
and entrepreneurs in the field of Electronics and
Communication.
PEO2 To acquire sufficient knowledge base for innovative techniques in

design and development of tools and systems.
PEO3 Capable of competing globally in multidisciplinary field.
PEO4 Achieve personal and professional success with awareness and

commitment to ethical and social responsibilities as an
individual as well as a team.
PROGRAM SPECIFIC OUTCOMES (PSOs)
PEO5 Graduates will maintain and improve technical competence.
through continuous Learning process.
Electronicsand
PSO1 The graduates will be able to apply the principles of Electronics and
Communication in core areas
PSO2 An ability to use latest hardware and software tools in Electronics and
Communication engineering.
pursuehigher
PSO3 Preparing Graduates to satisfy industrial needs and pursue higher
studies with social-awareness and universal moral values.
PROGRAM OUTCOMES (POs)
POs Description
Engineering knowledge: Apply the knowledge of mathematics, science,
PO1 engineering fundamentals and an engineering specialization to the solution of
complex engineering problems.
Problem analysis: Identify, formulate, review research literature, and
PO2 analyze complex engineering problems reaching substantiated conclusions
using first principles of mathematics, natural sciences.
Design / development of solutions: Design solutions for complex
engineering problems and design system components or processes that meet
PO3 the specified needs with appropriate consideration for the public health and
safety, and the cultural, societal, and environmental considerations.
Conduct investigations of complex problems: Use research-based
knowledge and research methods including design of experiments, analysis
PO4 and interpretation of data, and synthesis of the information to provide valid
conclusions.
Modern tool usage: Create, select, and apply appropriate techniques,
resources, and modern engineering and IT tools including prediction an
PO5 modeling to complex engineering activities with an understanding of the
limitations.
The engineer and society: Apply reasoning informed by the contextual
PO6 knowledge to assess societal, health, safety, legal and cultural issues and the
consequent responsibilities relevant to the professional engineering practice.
Environment and sustainability: Understand the impact of the professional
PO7 engineering solutions in societal and environmental contexts, and demonstrate
the knowledge of, and need for sustainable development.
Ethics: Apply ethical principles and commit to professional ethics and
PO8 responsibilities and norms of the engineering practice.
Individual and team work: Function effectively as an individual, and as a
PO9 member or leader in diverse teams, and in multidisciplinary settings.
Communication: Communicate effectively on complex engineering activities
with the engineering community and with society at large, such as, being able
PO10 to comprehend and write effective reports and design documentation, make
effective presentations, and give and receive clear instructions.
Project management and finance: Demonstrate knowledge and
understanding of the engineering and management principles and apply
PO11 these to one’s own work, as a member and leader in a team, to manage
projects and in multidisciplinary environments.
Life-long learning: Recognize the need for and have the preparation and
PO12 ability to engage in independent and life-long learning in the broadest
context of technological change.
DOs and DONTs
01 Follow the schedule time, late comers will not be permitted.

02 Sign the Logbook available in the lab.
03 Compulsorily wear Footwear in the lab
04 Keep belongings in the specified place.
05 Students are expected to come prepared for experiments & VIVA
Show the completed observations book and submit record to the Teacher before the lab
06
session begins.
07 Cycle of experiments should be followed.
08 Don’t do the connections or remove the connections with power ON.

Check the circuit connections properly & get it checked, verified by staff
09
in – charge before switching it ON.
10 Follow all the safety measures as suggested by the Teachers / Lab Instructor.
Observe the instructions given by the Teacher / Lab Instructor and strictly follow
11
accordingly.
Report to the Teacher / Lab Instructor immediately in case of any Software / Hardware
12
/ Electrical failure during working. Never try to fixit manually / individually
Switch OFF the instruments, remove all connections & return components before
13
leaving the lab.
14 Get the observations verified / signed by the teacher before leaving the lab.
15 Maintain discipline & tidiness inside the lab. Attend the lab in formal attire.
Usage of Mobile phones, Pen Drive and Electronic Gadgets are restricted during the
16
lab session.
** You are Under CCTV Surveillance.

B. E. (EC / TC)
Choice Based Credit System (CBCS) and Outcome Based Education
(OBE) SEMESTER – IV
ANALOG CIRCUITS LABORATORY
Laboratory Code 18ECL48 CIE Marks 40
02Hr Tutorial (Instructions)
Number of Lecture SEE Marks 60
Hours/Week + 02 Hours Laboratory
RBT Level L1, L2, L3 Exam Hours 03
CREDITS – 02
Course Learning Objectives: This laboratory course enables students to
 Understand the circuit configurations and connectivity of BJT and FET Amplifiers
and Study of frequency response.
 Design and test of analog circuits using OPAMPs.
 Understand the feedback configurations of transistor and OPAMP circuits.
 Use of circuit simulation for the analysis of electronic circuits.
Laboratory Experiments
PART A: Hardware Experiments
1. Design and setup the Common Source JFET/MOSFET amplifier and plot the frequency.
response.
2. Design and set up the BJT common emitter voltage amplifier with and without feedback.
and determine the gain- bandwidth product, input and output impedances.
3. Design and set-up BJT/FET i) Colpitts Oscillator, and ii) Crystal Oscillator
4. Design active second order Butterworth low pass and high pass filters.
5. Design Adder, Integrator and Differentiator circuits using Op-Amp

6. Test a comparator circuit and design a Schmitt trigger for the given UTP and LTP values
and obtain the hysteresis.
7. Design 4-bit R – 2R Op-Amp Digital to Analog Converter (i) using 4-bit binary input
from toggle switches and (ii) by generating digital inputs using mod-16 counter.
8. Design Monostable and a stable Multivibrator using 555 Timer.
PART-B: Simulation using EDA software.
(Edwin, PSpice, MultiSim, Proteus, Circuit Lab or any other equivalent tool can be used)
1. RC Phase shift oscillator and Hartley oscillator.
2. Narrow Band-pass Filter and Narrow band-reject filter.
3. Precision Half and full wave rectifier.
4. Monostable and A stable Multivibrator using 555 Timer.
Dept. of ECE, BIT

Course Outcomes: On the completion of this laboratory course, the students will be able
to:
 Design analog circuits using BJT/FETs and evaluate their performance characteristics.
 Design analog circuits using OPAMPs for different applications.
 Simulate and analyze analog circuits that uses ICs for different electronic applications.
Conduct of Practical Examination:
 All laboratory experiments are to be included for practical examination.
 Students are allowed to pick one experiment from the lot.
 Strictly follow the instructions as printed on the cover page of answer script for breakup
of marks.
 Change of experiment is allowed only once and Marks allotted to the procedure part to
be made zero.
Reference Books:
1. David A Bell, “Fundamentals of Electronic Devices and Circuits Lab

Manual, 5th Edition,2009, Oxford University Press.
Dept. of ECE, BIT

ANALOG CIRCUITS LABORATORY (18ECL48) QUESTION BANK

1(a) Design a common source JFET amplifier; find the Gain Bandwidth Product from the
frequency response plot by conducting an experiment.
(b) Design and simulate 555 Timer as Astable Multivibrator using P-Spice for 50% duty cycle
/ 65% duty cycle with a frequency of 1kHz.
2. Design BJT common emitter voltage amplifier without feedback and determine
experimentally (i) Gain Bandwidth Product from frequency response curve (ii) Input
impedance (Zi) and Output impedance (Z0).
3. Design BJT common emitter voltage amplifier with feedback and determine
experimentally (i) Gain Bandwidth Product from frequency response curve (ii) Input
impedance (Zi) and Output impedance (Z0).
4.(a) Design a BJT Colpitts oscillator for a frequency of 100kHz.Verify experimentally

theoretical and practical Frequency.
(b) Design and simulate 555 Timer as Monostable Multivibrator for a pulse width of
T= 5ms/2ms.
5. (a) Design a BJT Crystal oscillator for a frequency of 1MHz. Verify experimentally, the
Crystal frequency with practical Frequency.
(b) Design and simulate narrowband pass filter for a Centre frequency of 1 kHz, Quality (Q)
factor = 3 and Pass band gain (AF) =10.
6 (a) Design a second order Butterworth active low pass filter for a cutoff frequency of 10 kHz.
Determine experimentally (i) Gain (ii) Cutoff frequency (iii) Roll-off rate by plotting the
frequency response curve.
(b) Design and simulate precision half wave rectifier using 741 Op-amp for a gain (Av) = 1 /
gain (Av) =10.
7 (a) Design a Second order Butterworth Active high pass filter for a cutoff frequency of 5
kHz. Determine experimentally (i) Gain (ii) Cutoff frequency and (iii) Roll-off rate by plotting
the frequency response curve.
(b) Design and simulate RC phase shift oscillator using 741 Op-amp for a frequency of
oscillation 2 kHz/ 650Hz.
Dept. of ECE, BIT

8 a) Design a three-input inverting adder for a gain (Av) = 1/ gain (Av) = 3. Verify the
theoretical gain and practical gain by conducting an experiment.
(b) Design and simulate Hartley oscillator using 741 Op- amp for a frequency of oscillation
100 kHz.
9 (a) Design 3 input Noninverting adder for a gain (Av) = 2 / gain (Av) = 3. Verify the
theoretical Gain and practical Gain by conducting an experiment
b) Design and simulate precision full wave rectifier using 741 Op-amp for a gain (Av) = 1 /
gain (Av) =10.
10 (a) Design a differentiator and integrator circuit using Op-amp 741 for a time period of 1ms.
Verify the circuit operation by conducting an experiment.
(b) Design and simulate narrowband reject filter for a notch out frequency of 50Hz / 60Hz.
11(a) Test a comparator circuit for reference voltage, Vref = +1V and Design an inverting
Schmitt trigger for |UTP| = |LTP| = 2V. Verify the UTP and LTP values by conducting an
experiment.
(b) Design and simulate precision half wave rectifier using 741 Op-amp for a gain (Av) = 1 /
gain (Av) =10.
12(a) Test a comparator circuit for reference voltage, Vref = -1V and Design an inverting
Schmitt trigger for UTP = 4V LTP = 2V. Verify the UTP and LTP values by conducting an
experiment.
(b) Design and simulate narrowband reject filter for a Notch out frequency of 50Hz / 60Hz.
13 Design 4-bit R-2R digital to analog converter using 741 Op-amp (i) Determine the output
voltage using 4-bit binary input from toggle switches (ii) Generate staircase waveform using
MOD 16 counter.
14(a) Design a Monostable multivibrator using 555 timer for a pulse width of 5ms.
(b) Design and simulate RC phase shift oscillator using 741 Op-amp for a frequency of
oscillation 2 kHz/ 650Hz.
15(a) Design an astable multivibrator using 555timer for a time period of 1ms and duty cycle
of 50%.
(b) Design and simulate Hartley oscillator using 741 Op- amp for a frequency of oscillation
100 kHz.
Dept. of ECE, BIT

CONTENT
SL. Page
Name of the Experiment
No. No.
I CYCLE
Design and setup the Common Source JFET / MOSFET amplifier and
1 1-4
plot the frequency response.
Design and setup the BJT Common Emitter voltage amplifier with and
2 without feedback and determine the gain bandwidth product, input and 5 - 12
output impedances.
3 Design Adder, Integrator and Differentiator circuits using Op-Amp. 13 - 21
Monostable and Astable Multivibrator using 555 Timer (Part- B

4 22 - 36
Experiment using PSpice Simulation Tool)
II CYCLE
Design and setup BJT/FET i) Colpitts Oscillator and ii) Crystal
5 37 -41
Oscillator
Test a comparator circuit and design a Schmitt trigger for the given
6 42 - 48
UTP and LTP values and obtain the hysteresis.
Design 4-bit R-2R Op-Amp Digital to Analog Converter (i) using 4-
7 bit binary input from toggle switches and ii) by generating digital 49 - 53
inputs using mod-16 counter.
RC Phase shift oscillator and Hartley oscillator (Part – B Experiment
8 54 - 57
using PSpice Simulation Tool)
III CYCLE
9 Design active second order Butterworth low pass and high pass filters. 58 - 64
10 Design Monostable and Astable Multivibrator using 555 Timer. 65 - 72

Narrow Band-pass Filter and Narrow band – reject filter (Part – B
11 73 - 78
Experiment using PSpice Simulation Tool)
Precision Half and Full wave Rectifier ((Part – B Experiment using
12 79 – 83
PSpice Simulation Tool)
EXPERIMENTS BEYOND SYLLABUS
1 Inverting Comparator
2 Inverting and Non - Inverting Amplifier

3 Hartley oscillator using BJT
Dept. of ECE, BIT

EXPERIMENT NO - 1
TITLE OF THE EXPERIMENT: Common Source JFET Amplifier
AIM OF THE EXPERIMENT: Design and setup the Common Source JFET
amplifier and plot the frequency response.
COMPONENTS REQUIRED: FET(BFW10/11), resistors, capacitors, DC

power supply, signal generator, CRO, multimeter, CRO probes, connecting wires
and Springboard.
Common Source JFET Amplifier:
CIRCUIT DIAGRAM:
Dept. of ECE, BIT 1

JFET TERMINAL IDENTIFICATION:
DESIGN:
From data sheet BFW10/11 specification (N channel JFET)
ID = 2mA, Vp = 8V, R0= 40KΩ, gm = 2.5mA/V
DC Biasing conditions:
VDD = 12V, VGS = -2V, VRD = 45% of VDD = 5.4V
To find RS:
𝑉𝑅𝑆 𝑉𝑅𝑆
RS = =
𝐼𝑆 𝐼𝐷
ID = IS = 2mA, VRS = VG – VGS = 0 – (–2V) = 2V
Then RS = 1K.
Select RG = 1MΩ
To find RD:
𝑉𝑅𝐷
RD = = 2.7k
𝐼𝐷
To find CS and CC:
Let f L = 100Hz
X CS = RS / 10 = 100/10 =100Ω, X CS ≤ 100Ω
X CS = 1 / 2π f LCS, Cs ≥ 1 / 2π f L X 100 = 16µf (Select 22µf)
Dept. of ECE, BIT 2

1
fL= 100Hz and RG= 1MΩ, CC1 = CC2 = = 1pF
2𝜋𝑓𝐿𝑅𝐺
Design of RL:
Gain of CS amplifier AV = gm (RD || RL)
Required AV = 15, We get RL = 4.7KΩ
PROCEDURE:
To determine Gain and Frequency Response: -
1. The Connections are made as per the circuit diagram.

2. Before applying AC input signal, the DC conditions are checked by
setting VDD =12V. Check VGS, VRD, VRS and VDS using multi meter.
3. Input sinusoidal signal (around 100mV) should be applied using signal
generator.
4. Keeping the input signal Vin constant, the frequency of the input signal
is varied from 100 Hz to 1 MHz in suitable steps while measuring output
voltage for different frequencies. The gain of the amplifier is calculated
from these values.
5. The gain in dB is calculated and tabulated. The graph of gain v/s frequency
is plotted on a semi log graph sheet.
6. Bandwidth is calculated from the frequency response. Also Gain
Bandwidth product is computed.
Tabular column:
Vi = 100mVp-p
Frequency V0(peak to peak) Gain Gain in dB

f (Hz) (Volts) AV = V0 / Vi AV= 20 log 10 (V0 / Vi)
100Hz
.
.
.
.
.
1M Hz
Dept. of ECE, BIT 3

FREQUENCY RESPONSE:
RESULT:
Midband Gain (Av mid) = Amax - 3dB
Band width BW = fH - fL in KHz
Gain Bandwidth product GBW in KHz
Gain band width product GBW= Midband Gain (Av mid) x (fH - fL)
Dept. of ECE, BIT 4

EXPERIMENT NO - 2
TITLE OF THE EXPERIMENT: Common Emitter Amplifier Using BJT
AIM OF THE EXPERIMENT: Design and setup the BJT Common Emitter
voltage amplifier with and without feedback and determine the gain bandwidth
product, input and output impedances.
COMPONENTS REQUIRED: Transistor (BC107), resistors, capacitors, DC

power supply, signal generator, Multimeter, connecting wires and Board, CRO,
CRO probes.
CE amplifier without feed back
CIRCUIT DIAGRAM:
Dept. of ECE, BIT 5

OUTPUT WAVE FORM:
THEORY:
In the circuit shown the NPN transistor is connected as a Common emitter (CE)
ac amplifier in which the voltage divider biasing (Voltage divider network is
formed by the resistors R1 and R2), is employed as it provides good stabilization
of the operating point so that the operating point can be made independent of the
variations in hfe. For proper functioning of transistor as an amplifier the transistor
must be biased in the active region where the base current has a complete control
over the collector current. Thus, a small increase in base current results in
relatively large increase in collector current and a small decrease is followed by
a large decrease in the collector current. The input resistance of the amplifier Ri
= R1|| R2||(1+hfe) re with the bypass capacitor CE is connected and Ri = R1||
R2||(1+hfe) (re + RE) with CE removed, where re= VT / RE, where re is the internal
emitter resistance of the transistor and VT = 26mV i.e the equivalent thermal
voltage at room temperature. The output resistance of the amplifier R0 ≈ RC, where
RC is the collector resistance. The purpose of the bypass capacitor CE is to bypass
signal current to the ground. the ac signal (feedback) voltage developed across
the emitter resistance RE is bypassed through CE. Since bypassing increases the
negative feedback the gain of the amplifier decreases. This implies that when the
bypass capacitor CE is connected the gain of the amplifier increases and band
width decreases and when disconnected the gain falls and bandwidth increases.
The purpose of the coupling capacitor Cc1 and Cc2 is to block dc and to couple ac
signal to the input and output of the amplifier respectively. The coupling
capacitors also determine the lowest frequency which is to be amplified.
DESIGN:
Given: Vcc =10V, Ic = 2mA, hfe or β =100 to 150 choose BC 107
To find RE:
VRE = Vcc /10 =1V

Dept. of ECE, BIT 6
IE = I C = 2mA, RE = VRE/IE = 1/2x10-3 = 500Ω (choose 470Ω)
To make the operating point in the middle of the load line take VCE = Vcc /2 = 5V
To find RC:
Applying KVL to output loop.
Vcc – VRC – VCE – VRE = 0
VRC = Vcc – VCE – VRE = 10 – 5 – 1 = 4V
RC = VRC / I C = 4 / 2x10-3 = 2KΩ (choose 2.2KΩ)
To find R1 and R2
Assume Stability factor, S = 5 and β = 100
S = (1+ β) (RE + RTh) / (1+ β) RE + RTh
Where RTh = R1 R2 / (R1 + R2) = 2.1KΩ
VR2 = V BE + V RE = 0.7 + 1 = 1.7V
VTh = VR2 = Vcc R2 / (R1 + R2)
R2 / (R1 + R2) = VTh / Vcc = 1.7 / 10 = 0.17V
RTh = R1 R2 / (R1 + R2), Solving R1 = 12.3KΩ, R2= 2.5KΩ
Choose R1 = 12K Ω, R2 = 2.2 K Ω
To find CE :
X CE = 1/ (2πf CE)
As a thumb rule take XCE = (1 / 10) RE = 50 Ω
For fL= 100 Hz, (lower frequency) CE = 31.8µF (choose 47µF)

1
Choose the coupling capacitors Cc= , Ri = R1||R2|| (1+hfe) re
2𝜋 𝑋 𝑅𝑖 𝑓𝐿
re = 25mV/ IE = 12.5Ω
up to 1µF can be selected. Choose 0.47µF and RL = 10KΩ
Dept. of ECE, BIT 7

PROCEDURE:
To determine Gain and Frequency Response:
1. The Connections are made as per the circuit diagram.

2. Before applying AC input signal, without connecting capacitors the DC
conditions are checked by setting Vcc =10V. Check VCE = 1 / 2 Vcc ≈ 5V,
VRE ≈ 1V, VBE ≈ 0.7V and VRC ≈ 4V using multimeter. Calculate I C = VRC /
Rc.
Find Q point (VCE, I C):
3. Connect the capacitors in the circuit. Apply input sinusoidal signal Vin
(around 20 m V peak to peak to 50 m V peak to peak) should be applied
using audio signal generator. Observe input, output wave forms
simultaneously on the CRO screen.
4. Keeping the input signal amplitude Vin constant at 20mVp-p, the
frequency of the input signal is varied from 100 Hz to 1 MHz in suitable
steps measure the output peak to peak voltage for different frequencies and
enter it in a tabular column. The gain of the amplifier is calculated from
these values.
5. The gain in dB is calculated and tabulated. The graph of gain vs frequency
is plotted on a semi log graph sheet. Plot the frequency response
characteristics on a semi log graph sheet with gain in dB on Y-axis and
frequency in Hz on X-axis. Mark fL and fH corresponding to 3dB points.
Bandwidth is calculated from the frequency response using expression
BW= fH - fL. Determine the mid-band gain from graph, also Calculate Gain
Band Width (GBW) product.
6. Remove the bypass capacitor CE from the circuit and repeat the steps 4 to
6. Observe the increase in band width and decrease in gain in the absence
of CE.
Dept. of ECE, BIT 8

Tabular column:
Vi = 20 mVp-p CE amplifier without feedback (with CE)
Frequency V0(peak to peak) Gain Gain in DB
100Hz
1MHz
Vi = 20 mV CE amplifier with feedback (without CE)

Frequency V0(peak to peak) Gain Gain in DB
100Hz
1MHz
Dept. of ECE, BIT 9

FREQUENCY RESPONSE CURVE:
Dept. of ECE, BIT 10

To measure the input impedance Zi with feedback (Without CE) and without
feedback (With CE):
PROCEDURE:
1. Connect 10KΩ potentiometer in series with Signal Generator and CC1 as

shown in the above the circuit diagram.
2. Display the output wave form in mid band frequency i.e maximum output
voltage (Vomax).
3. Vary the potentiometer till output reduces to half of its maximum value.
4. Remove the potentiometer, measure the resistance using ohmmeter. This
is the value of input impedance Zi of the amplifier.

To measure the output Impedance Zo With feedback (Without CE) and

Without feedback (With CE):
PROCEDURE:
5. Connect 4.7K/1KΩ potentiometer across the RL as shown in above circuit

diagram.
6. Display the output wave form in mid band frequency i.e maximum output
voltage (Vomax).
7. Vary the potentiometer till output reduces to half of its maximum value.
8. Remove the potentiometer, measure the resistance using ohmmeter. This
is the value of output impedance Zo of the amplifier.
RESULT:
Parameters Without With feedback

feedback
Midband Gain (Av mid) = Amax - 3dB
Band width BW = fH - fL in KHz
Gain-Bandwidth product in KHz
Input Impedance in Ω
Output Impedance in Ω
Gain band width product GBW = Midband Gain (Av mid) x (fH - fL)

EXPERIMENT NO - 3
TITLE OF THE EXPERIMENT: Adder, Integrator and Differentiator
AIM OF THE EXPERIMENT: Design Adder, Integrator and Differentiator

circuits using Op-Amp
COMPONENTS & EQUIPMENTS: Op-amp µA741, resistors, capacitor,

CRO, CRO probes, multi meter, connecting wires and Board, Dual power supply,
DC power supply, signal generator.
PIN DIAGRAM OF IC UA741

Summing Amplifier or Adder:
1. Inverting Adder:
CIRCUIT DIAGRAM:
This circuit gives the sum of two input voltages hence it is also called summing
amplifier. Refer to the circuit diagram shown in figure. Here an input dc voltages
V1, V2 and V3 are given as inputs to the adder. This is an inverting summing
amplifier because the output is sum of inputs with a sign change. The minus sign
in the expression for the output can be avoided if necessary, by inverting the
output once again using a unity gain inverting amplifier. Output can be scaled by
selecting the ratio RF/Ri. Where Ri can be R1/R2/R3. If the ratio is greater than
1, the circuit functions as a summing amplifier because it provides gain also.
DESIGN:
𝑅𝑓 𝑅𝑓 𝑅𝑓
Vo = - (𝑅1 V1 + 𝑉2 + 𝑅3 𝑉3) If Rf =R1 = R2 = R3= 1KΩ then Vo = - (V1+V2+V3)
𝑅2

2. Non- inverting Adder:
CIRCUIT DIAGRAM:
A non-inverting amplifier can be used a summing circuit. This gives the direct
sum of the inputs instead of the inverted sum.
DESIGN:
𝑅𝑓+𝑅1 𝑉1+𝑉2
𝑉0 = [ ]𝑋 [ ] For two input If Rf=R1=R2=1KΩ then VO= (V1+V2)
𝑅1 2
For three inputs:

𝑅𝑓+𝑅1 𝑉1+𝑉2+𝑉3 𝑅𝑓+𝑅1
1. 𝑉0 = [ ]𝑋 [ ] If 𝐴𝑣 = =3 And Rf= 2kΩ
𝑅1 3 𝑅1
R1=R2=R3=R4=1KΩ then
V0 = (V1+V2+V3)
𝑅𝑓+𝑅1 𝑉1+𝑉2+𝑉3 𝑅𝑓+𝑅1
2. 𝑉0 = [ ]𝑋 [ ] If 𝐴𝑣 = = 6 and
𝑅1 3 𝑅1
Rf = 5R1, R1=R2=R3=R4=1KΩ
Then V0 = 2(V1+V2+V3)

Tabular column:
𝑉0
INVERTING ADDER
Vo(V) Av = ( )
𝑉𝑖𝑛
Theoretical Practical Theoretical Practical
1) i) V1=V2=V3=1V
Rf=R1=R2=R3=1KΩ
ii) V1=V2=V3=1V
Rf=3K, R1=R2=R3=1KΩ
iii) V1=1V, V2=2V, V3=3V
Rf=R1=R2=R3=1KΩ
iv) V1=0.5V, V2=1V, V3=1.5V
Rf=2KΩ, R1=R2=R3=1KΩ
𝑉0
NON-INVERTING ADDER
Vo(V) Av = ( )
𝑉𝑖𝑛
Theoretical practical Theoretical practical
2) i) V1=V2=V3=1V
R1=R2=R3=1KΩ
1. Rf = 1KΩ
2. Rf = 2KΩ
ii) V1=V2=V3=1V
Rf= 5KΩ, R1=R2=R3=1KΩ,
R4= 1KΩ
iii) V1=1V, V2=2V, V3=3V
Rf= R1=R2=R3=1KΩ,
R4= 1KΩ
iv) V1=0.5V, V2=1V,
V3=1.5V
Rf= 8KΩ, R1=R2=R3=1KΩ,
R4= 1KΩ
PROCEDURE:
1. Verify correctness of the components and Connections are made as per

circuit diagram.
2. Switch on the dual power supply to power the Op-amp, apply the DC input
voltages V1, V2 and V3 using DC power supply as per the tabular column.
3. Note the corresponding output voltage using multimeter and calculate the
gain of the amplifier.

INTEGRATOR:
Refer to the circuit diagram shown in figure. This circuit performs the integration
of the input waveform. The output voltage V0 can be expressed as
1
Vo= - ∫ 𝑉 𝑖 𝑑𝑡 + 𝑘 where k is the constant of integration which depends on the
RC
value of Vo at t=0. The peak of the output waveform VT is given by the expression
VT
VT = , where V is the amplitude of input voltage and T is the time period of
4RC
the input square wave. Integrators are commonly used in analog computers and
wave shaping networks.
Gain and linearity of the output waveforms are the two important advantages of
op-amp integrators over ordinary RC integrators. Linearity of the waveform is
achieved by the constant current through the capacitor. Due to the property of
virtual ground, current through the input resistance is constant due to constant
potential drop across it. Current through the input resistor and capacitor is the
same.
At low frequencies of the input voltage, capacitor behaves as an open circuit. Op-
amp may saturate at low frequency even for a very low voltage at the input. This
is because the open loop gain is very high. A high value feedback resistor R F is
connected across the capacitor as shown in the figure to prevent the op-amp from
going to saturation. When RF is connected, gain will be reduced considerably at
low frequencies. At higher frequencies circuit behaves as an ordinary integrator.
In other words, at low frequencies RF is effective and at high frequencies C is
effective in the feedback path. Integrator is a first order low pass filter. It permits
low frequency signals to pass to output.

INTEGRATOR:
CIRCUIT DIAGRAM
DESIGN:
1
fb = Let T=1ms, Cf=0.1µF then R1=1.5KΩ
2𝜋𝑅1 𝐶𝑓
1
fa =
2𝜋𝑅𝑓 𝐶𝑓
1
fb = with fa < fb choose Rf = 100R1
2𝜋𝑅1𝑐𝑓
i.e fa= 15.9Hz, fb = 1KHz
fa < fb
fa = Gain Limiting Frequency (Frequency at which gain is reduced by 3dB from
its maximum value,
fb= Frequency at which gain is 0 dB.
Condition: Choose the frequency of the input signal as 1KHz and peak to
peak amplitude of Vi = 2V.

WAVEFORMS:
DIFFERENTIATOR:
CIRCUIT DIAGRAM:

If the input resistance of the inverting amplifier is replaced by a capacitor, it forms

an inverting differentiator. The output of this circuit is the derivative of the input.
Gain of the differentiator increases with increase in frequency. This makes the
circuit unstable which is a drawback of this circuit. The output voltage Vo can be
dvi
expressed as Vo = - R C . Differentiator functions as high pass filter. Both
dt
stability and high frequency noise problems are reduced significantly by the
addition of R and C, forming a practical differentiator.
DESIGN
1
f= Let T=1ms, C1=0.1µF then Rf=1.5KΩ
2𝜋𝑅𝑓 𝐶1
RfCf = R1C1 , Select Cf = 0.005uF (Use two 0.001uF in series)
R1 = 75Ω, Select R1 = 100Ω
Condition: Choose the frequency of the input signal as 1KHz and peak to
peak amplitude of Vi = 2V.
WAVEFORMS:

PROCEDURE:
4. Verify the correctness of the components and Connections are made as per
circuit diagram.
5. Switch on the dual power supply to power the Op-amp, apply the Square
Wave input voltage of 2V peak to peak using signal generator.
6. Note the corresponding output voltage wave form for both integrator and
differentiator circuits by varying frequency of input and plot the input and
output waveforms.
7. Also verify the output voltage for ac sinusoidal input voltage for both
integrator and differentiator circuits.
RESULT: Adder, Integrator and Differentiator circuits are tested and the outputs
of each circuit are verified.

EXPERIMENT NO - 4
TITLE OF THE EXPERIMENT: Simulation of Monostable and Astable

Multivibrator using PSpice.
AIM OF THE EXPERIMENT: To Design and Simulate 555 Timer as
Monostable and Astable Multivibrator
Software tool used: PSpice Schematics Version 9.1
Drawing the Astable Multivibrator circuit in the Pspice Schematic Window
1 Double Click on the Schematics Icon
2 The Schematic window opens. Select the menu  Draw  Get New Part… or (Ctrl + G)
3 Then the Part Browser window Opens. Click on the Libraries button.

4 In the Library Browser window select eval.slb library. Click OK
5 Select the part name 555D and click Place button. Place the part on the schematic window
page. After placing the part press esc key from the keyboard to deselect the part.

6 Then select another part VDC from the Part Browser window and place it on the schematic
window and press the esc button to deselect it.
7 Next select the R (Resistor) part and place it on the schematic page.

8 Next select the C (Capacitor) part and place it on the schematic page.
9 Next select the D1N4002 (Diode) part and place it on the schematic page.

10 Next select the EGND (Ground) part and place it on the schematic page.
11. Now connect the components by clicking on Draw Wire short cut button. Draw the lines
to connect the components and complete the circuit.

12. After drawing the circuit, place the Voltage marker symbol / Current marker symbol by
clicking on Voltage and Current shortcut buttons or select from the Markers menu.
13. Now save the circuit by selecting File  Save / Save As menu options. Type the
filename and click the save button.

14. Now Double click the VDC part to change the value. Uncheck the check box Include
Non-changeable Attributes and select the value name type the value in the Value
Textbox. Click Save Attr button.
15. Then select the Reference name type and the name in the Value textbox. Click Save Attr

button and press OK button.
Select the menu Analysis  Setup.

Select the check box Transient . Click on the Transient Analysis button.
Now Select Menu Analysis  Simulate or press F11 key from the Keyboard.
The waveform window opens.

5.0V
4.0V
3.0V
2.0V
1.0V
0V
-1.0V
0s 1ms 2ms 3ms 4ms 5ms 6ms 7ms 8ms 9ms 10ms
V(C:2) V(X1:OUTPUT)
Time
(a). ASTABLE MULTIVIBRATOR
CIRCUIT DESIGN FOR 50% DUTY CYCLE:

WAVEFORMS:
5.0V
4.0V
3.0V
2.0V
1.0V
0V
-1.0V
0s 1ms 2ms 3ms 4ms 5ms 6ms 7ms 8ms 9ms 10ms
V(C:2) V(X1:OUTPUT)
Time
Output Voltage Capacitor Voltage
TABULAR COLUMN:
Theoretical Practical
Ton
Toff
T= Ton + Toff
f = 1/T
% D = (Ton/T )x100
DESIGN:
Given, Duty cycle D = 50% and frequency = 1 KHz or T = 1ms
 Charging Time constant T1 = Ton = 0.693[RA+RB]C

 Discharging Time constant T2 = Toff = 0.693[RB]C
T1
 Duty Cycle D 
T1  T 2
 0.5 = T1/1ms
 T1 = 0.5ms and T2 = 0.5ms i. e T1 = T2
Choose RA = RB = R, C = 0.1 µF
T1 = Ton = 0.5ms = 0.693[RA]C,
T2 = Toff = 0.693[RB]C then RA = RB = 7.2KΩ,

CIRCUIT DESIGN FOR 65% DUTY CYCLE:
WAVEFORMS:

Duty cycle D = 65% and frequency = 1KHz
 Charging Time constant T1 = Ton = 0.693[RA+RB]C

 Discharging Time constant T2 = Toff = 0.693[RB]C
T1
 Duty Cycle D  ----------- (1)
T1  T 2
 T = T1+T2 =1/f, T =1ms
T1
 Duty Cycle D   65%
T
 T1 = 65% x T = 0.65ms and T2 = 0.35ms
 Assume C = 0.1 µF
RA = 4.32K, RB = 5.05K, C = 0.1 µF
TABULAR COLUMN:
Ton
Toff
T= Ton + Toff
f = 1/T
% D = (Ton/T )x100

(b). MONOSTABLE MULTIVIBRATOR
CIRCUIT DIAGRAM:
VPulse Specifications:
V1 = 0V, V2 = 10V, TD = 0, TR = 0, TF = 0, PW = 8ms, PER = 20ms
Transient Analysis:
Print Step = 1ms

Final Time = 100ms

WAVEFORMS:
Input Trigger
Signal at Pin no. 2

Vcc
T Timer Output
Capacitor Voltage
DESIGN 1:
Pulse Width T = 1.1RC Assume C = 0.47uF and T = 5ms, R = 9.671K, for
Differentiator choose C2 = 0.47uF, R1 = 1K for proper operation, Time period of
the Triggering pulse is given by R1C2 << T.
DESIGN 2:
Pulse Width T = 1.1RC Assume C = 0.47uF and T = 2ms, R = 3.868K, for
Differentiator choose C2 = 0.47uF, R1 = 1K, for proper operation, Time period of
the Triggering pulse is given by R1C2 << T.
TABULAR COLUMN:
Theoretical value Practical value
Pulse Width (Design 1)
Pulse Width (Design 2)
RESULT: Simulated Astable and Monostable Multivibrator using 555

Timer, Design is verified, and waveforms are noted.

EXPERIMENT NO - 5
TITLE OF THE EXPERIMENT: BJT Colpitts and Crystal Oscillator
AIM OF THE EXPERIMENT: To design and set up BJT Colpitts & Crystal
Oscillator circuit for measuring frequency of oscillations and amplitude.
COMPONENTS REQUIRED: Transistor (BC107), resistors, capacitors
inductors, potentiometer, DC power supply, CRO, CRO probes, multi meter,
connecting wires and Board.
THEORY:
LC oscillators are the radio frequency (RF) oscillators since they are preferred for
high frequency generation. Hartley and Colpitts oscillators are the two commonly
used LC oscillators in which an LC tank circuit is employed for frequency
selection. The voltage divider bias is used for the amplifier in CE configuration.
Amplifier section provides 180° phase shift to satisfy the Barkhausen criterion.
High frequency transistors are preferred for better performance. The resistor R E
is bypassed by CE to prevent ac signal degeneration and thus to improve the gain
of the amplifier.
Colpitts Oscillator:

DESIGN:
AMPLIFIER DESIGN
Given: Vcc = 10V, Ic = 2mA, hfe = 100 to 150, Choose BC 107
To find RE:
Vcc
VRE = = 1V
10
VRE
IE = I C = 2mA, RE = = 1/2x10-3 = 500Ω (choose 470Ω)
IE
To find RC :
In order to make the operating point in the middle of the load line
Take VCE = Vcc /2 = 5V
Applying KVL to output loop.
VCC – VRC – VCE - VRE= 0
VRC = Vcc - VCE - VRE = 10 – 5 – 1 = 4V
RC = VRC / I C = 4 / 2x10-3 = 2KΩ (choose 2.2KΩ)
To find R1 and R2
Assume S = 5 , S is stability factor

(1+β)
S= βRE
⌊1+(RE +Rth)⌋
R1 R2
Where Rth = i.e Rth = 2.086KΩ (using above stability factor equation)
(R1+ R2 )
VR2 = V BE +V RE = 0.7 + 1 =1.7V

R2
Vth = VR2 = Vcc
(R1+ R2 )
R2 Vth
= = 1.7 / 10 = 0.17V
(R1+ R2 ) Vcc

R1 R2
Rth = , Solving R1 = 12.27KΩ, R2= 2.2KΩ
(R1+ R2 )
Choose R1 = 12K Ω , R2 = 2.2 K Ω
To find CE :
1
X CE = As a thumb rule take X CE = (1 / 10)RE = 50 Ω
(2π𝑓𝐿 𝐶𝐸 )
For fL= 100Hz, (lower frequency) CE = 31.8µf (choose 47µf)

1
Choose the coupling capacitors C c= , Ri = R1||R2|| (1+hfe)re
2𝜋 𝑋 𝑅𝑖 𝑓𝐿
re = 25mV/ IE = 12.5Ω
upto 1µf can be chosen Choose 0.47 µf
FEED BACK CIRCUIT DESIGN:
Frequency of oscillations f = 100 KHz
f = 1/2π√ LC --------- (1) where C = C1C2/C1+C2,
Let C1 = 4700pF, C2 = 2200pF then β = C2/C1= 0.46
On solving eq (1) we get L = 1.69mH, choose L = 1mH.
PROCEDURE:
1. Without Connecting the feedback circuit, the amplifier circuit is connected

as per the circuit. The DC conditions of the amplifier is checked by setting
Vcc =10V, VCE must be =1 / 2 Vcc ≈ 5V, VRE≈ 1V, VBE ≈ 0.7V and check
VRC, using multi meter. Calculate I C = VRC / Rc. Find Q point (VCE, I C)
2. Connect the feedback circuit. Vary the 1 KΩ potentiometer to get.
Undistorted sine wave output.
3. Measure the amplitude and frequency of oscillations. compare theoretical.
and practical frequency.

BJT CRYTAL OSCILLATOR
Components required: Transistor (BC107), resistors, capacitors, Crystal

(1MHz), potentiometer DC power supply, CRO, CRO probes, multi meter,
connecting wires and Board.
Theory:
In conventional radio frequency oscillators using LC circuits, the frequency

stability is usually poor because of the variations in temperature, humidity,
transistor, and circuit parameters, etc. For certain applications such as radio or
television transmitters, it is essential the frequency of oscillation of master
oscillator must extremely stable. The crystal oscillator is an excellent solution
for this. It provides very high stability and quality factor. A piezo electric
crystal is used in crystal oscillator as a resonant tank circuit. A crystal acts like a
large inductor in series with a small capacitor. When alternating voltage is
applied across such a crystal, it vibrates at the frequency of applied voltage.
Conversely, if it is forced to vibrate, it will generate an alternating voltage. This
property is called piezoelectric effect. The common and readily available
crystals are Rochelle salt, Tourmaline, and quartz.
BJT CRYTAL OSCILLATOR:

AMPLIFIER DESIGN: Refer Colpitts Oscillator
PROCEDURE:
4. Without Connecting the feedback circuit (i.e., 1MHz crystal and

0.01µFand 1000pF), the amplifier circuit is connected as per the circuit.
The DC conditions of the amplifier is checked by setting Vcc =10V, VCE
1 1
must be Vcc ≈ 5V, VRE ≈ Vcc≈ 1V, VBE≈ 0.7V and check VRC = 4V,
2 10
using multi meter. Calculate I C = VRC / Rc. Find Q point (VCE, I C).
5. Connect the feedback circuit, vary the 1 KΩ potentiometer to get
undistorted sine wave output.
6. Measure the amplitude and frequency of oscillations. Compare
theoretical and practical frequency.
OUTPUT WAVEFORM
RESULT:
COLPITTS CRYSTAL
OSCILLATOR OSCILLATOR
Theoretical Frequency
Practical Frequency

EXPERIMENT NO - 6
TITLE OF THE EXPERIMENT: Schmitt Trigger Using Op-amp IC 741.
AIM OF THE EXPERIMENT: To test a comparator circuit and design the

Schmitt Trigger for the given UTP and LTP Values and obtain the hysteresis.
COMPONENTS REQUIRED: Opamp IC 741, resistors, RPS, CRO,
1N4001Diodes, connecting Wires.
THEORY:
About the Comparator:A comparator,as its name implies,compares a signal

voltage on one input of an opamp with a known voltage called reference voltage
on the other input.It is an open loop opamp,the output may be positive or
negative saturation voltage depending on the which input is larger.Comparators
are used in circuits such as digital interfacing,schmitt triggers ,voltage level
detectors and oscillators.
About Schmitt Trigger

Schmitt trigger is a refined sort of comparator which employs positive feedback.
The reference voltage with which the input is compared depends on the state of
the output. Since output has two possible states, Schmitt trigger has two reference
voltages known as upper trigger point (UTP) and lower trigger point (LTP).
Above figure shows a simple Schmitt trigger with |UTP|=|LTP|. As mentioned,

positive feedback is used. A fraction of the output i.e., βVout is feed back to the

non-inverting terminal of the Opamp. Where β is known as feedback ratio and is

R2
given by β=
R1  R 2
Output can take any one of the two +Vsat or –Vsat. Let us assume the output is
saturated at +Vsat. βVsat is feed back to the noninverting terminal and the input
signal is compared with this. As long as input is less than βVsat(also known as
UTP),output is maintained at +Vsat. When input becomes greater than UTP, the
output switches to -Vsat as shown in case (i) of transfer characteristics.
Now –βV sat is feed back to the non-inverting terminal and the input signal is
compared with this. As long as input is more than -βVsat (also known as LTP),
output is maintained at -Vsat. When input becomes less than LTP, the output
switches to +Vsat as shown in case (ii) of transfer characteristics.
Values of UTP and LTP can be varied by changing the value of feedback ratio β.
For |UTP|≠|LTP|, a battery maybe used in feedback network or Diodes may be
used. Main difference between a normal comparator and a Schmitt trigger is that
area under the hysteresis curve is a finite nonzero value for Schmitt trigger
whereas it is zero for a comparator.
Application: Schmitt triggers are typically used in open loop configurations for
noise immunity and closed loop configurations to implement function generators.
CIRCUIT DIAGRAM: Non inverting Comparator

PROCEDURE:
1.Verify the correctness of all the components and connect the circuit as shown
in the figure.
2. Apply the low frequency (around 500 Hz) input signal of peak-to-peak
amplitude of 5V from signal generator.
3. Verify the comparator operation for both +Vref and –Vref and note down the
waveforms

Inverting Schmitt trigger
CIRCUIT DIAGRAM:
Design:
R2 R1
Upper Triggering Point UTP = V 1  Vsat + Vref
R1  R 2 R1  R 2
R2 R1
Lower Triggering Point = LTP = V 2  Vsat + Vref
R1  R 2 R1  R 2
Let Vcc = 12V, Vsat = 80% Vcc = 9.6V
1. |UTP|=|LTP|
Let |UTP|=|LTP|= 2V
R1
UTP+LTP = 0 = 2 Vref
R1  R 2
R1≠0 => Vref=0V
R2
UTP - LTP = 4 = 2Vsat
R1  R 2
Put Vsat = 9.6V
R1 = 3.8 R2
Choose R1=3.8KΩ (3.3K+470Ω+33Ω) and R2=1KΩ

2. UTP > 0V and LTP > 0V

Choose UTP = 4V, LTP = 2V
R1
UTP + LTP => 6 = 2 Vref
R1  R 2
R2
UTP – LTP => 2 = 2Vsat
R1  R 2
Substitute Vsat=9.6V
R1 = 8.6R2
𝑅1
=> 6 = 2x𝑉𝑟𝑒𝑓 𝑅1+𝑅2
8.6𝑅2
=> 6 = 2x𝑉𝑟𝑒𝑓 8.6𝑅2+𝑅2
Vref = 3.35V.
Choose R1 = 8.6K (8.2K+330Ω+68Ω) and R2 = 1KΩ
Note
lUTPl=lLTPl Vref = 0V
UTP>0V and LTP >0V Vref = +ve
Transfer Characteristics

Hysteresis curve
1. UTP = LTP = 2V
Vo
Vi
LTP UTP
2. UTP = 4V, LTP = 2V
Vo
vi

PROCEDURE:
1. Verify the correctness of all the components and connect the circuit as
shown in the figure.
2 Apply the low frequency (around 1KHz) input signal of peak-to-peak
amplitude of 10V from signal generator.
3. Note down the input/ output wave form and Hysteresis curve.
4. Find UTP and LTP from Hysteresis curve.
5. Repeat the same for different values of UTP and LTP.
RESULT:
Schmitt trigger was designed and implemented.
Vref (V) Theoretical Value Practical Value

UTP LTP UTP LTP

EXPERIMENT NO - 7
TITLE OF THE EXPERIMENT: R-2R Digital to Analog Converter
AIM OF THE EXPERIMENT: To Design 4-bit R-2R Op-Amp Digital to

Analog Converter Using i) 4-bit binary input from toggle switches
ii). By generating digital inputs using MOD-16 counter.
COMPONENTS REQUIRED: ICµA741, resistors, Dual RPS,7493IC, CRO

probes , CRO and Connecting Wires, board.
THEORY:
ADC and DAC form the front end and back-end systems in a DSP environment.
Analog signal is converted to digital format by ADC. This is processed in digital
domain. Finally, the digital signal is converted back into analog format by DAC
Pulse Width modulators, binary weighed DAC, R-2R DAC, Cyclic DAC,
thermometer DAC are few examples of various types of DACs which are present.
Simplest of all DAC is R-2R DAC. The main advantage of R-2R DAC over
weighted resistor DAC is for an n-bits ADC the number of resistors
grows exponentially, as resistors are required, while the R-2R resistor ladder
only increases linearly with the number of bits as it needs only resistors. The
resistive network forms a potential divider and can be obtained using Thevenin’s
theorem as shown.

CIRCUIT DIAGRAM:
Note: D0 = LSB, D3= MSB, D0 – D3 are DIGITAL INPUTS
DESIGN:
Rf  D3 D2 D1 D0 
Vo  Vref  2  3  4
2 R  21 2 2 2 
Let Maximum output voltage Vref = 5V, Vo = -5V and gain =1

Rf
Gain =  1 Rf = 2R, Choose R = 10KΩ, Rf = 22KΩ
2R ,
Also can Choose R = 1KΩ, Then Rf = 2.2KΩ
Formulae:
𝑉𝑓𝑠 𝑉𝑓𝑠
Resolution = =
2𝑛 −1 24 −1
Vfs=Full-scale output voltage,

TABULAR COLUMN:
Binary Input Output Output
(volts) (volts)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

WAVEFORMS:
PROCEDURE:
1. Verify the correctness of each component and connections are made as per
the circuit diagram.
i) Manually varying Digital Input
2. Apply the digital inputs from 0000 -1111(by setting /resetting the input
switches of digital trainer kits)
3. Obtain the DAC output at pin No. 6 verify theoretical values with practical
output values.
ii) Using MOD16 counter as digital input
4. Observe the output of MOD 16 counter (7493) on the digital trainer kit at
low frequency (around 1Hz)
5. Connect the mod 16 counter output to input of DAC circuit and apply the
frequency of 1KHz.
6. Obtain the DAC output and note down the staircase waveform at pin No.6.
IC 7493 Connection details for Mod 16 counter
D0 D1 D2 D3
12 9 8 11
1 5 Vcc =5V
7493 14 Clk
10 3 2
MR1 MR2
GND
Based on the input binary data, the potentials are added by the resistive network
to obtain the corresponding analog value
Application: DAC’s can be found in any device that interfaces digital and analog
circuitry, analog displays, digital control Systems, digital audio, communications
etc.
RESULT:
Four-bit R-2R DAC was designed and implemented.

EXPERIMENT NO - 8
TITLE OF THE EXPERIMENT: Simulation of RC Phase shift Oscillator and

Hartley oscillator using PSpice.
AIM OF THE EXPERIMENT: To Design and Simulate RC Phase oscillator and

Hartley Oscillator.
CIRCUIT DIAGRAM: RC Phase Shift Oscillator
Note: Keep the initial conditions of any one of the capacitor IC = 1V. (In the capacitor
attribute window).

Transient Analysis:
Print Step = 1ms

Final Time = 10ms
WAVEFORMS:
TABULAR COLUMN:
Design 1 Design 2
Theoretical Frequency
Practical Frequency
RC Phase Shift Oscillator:
Design 1: f = Frequency of Oscillations = 2 KHz
T = 0.5ms
1 0.065
f= =
2𝜋√6𝑅𝐶 𝑅𝐶
Assume C = 0.1uF, R = 325Ω and Rf = 29 x R = 9425Ω
(R = R1 in the circuit diagram)
Voltage gain Av = RF / R1 = 29

Design 2: f = Frequency of Oscillations = 650 Hz
T = 1.53ms
1 0.065
f= =
2𝜋√6𝑅𝐶 𝑅𝐶
Assume C = 0.1uF, R = 1K and Rf = 29k
(R = R1 in the circuit diagram)
Voltage gain Av = Rf / R1 = 29
CIRCUIT DIAGRAM: Hartley Oscillator
Note: Keep the initial conditions of both the inductors IC = 1 mA and for the
capacitor IC = 1V (In the Inductor and capacitor attribute window).

Transient Analysis:
Print Step = 1ms

Final Time = 10ms
WAVEFORMS:
1.0V
0V
-1.0V
3.468ms 3.500ms 3.550ms 3.600ms 3.650ms 3.700ms 3.750ms 3.800ms

V(OUT_PUT)
Time
DESIGN:
Frequency of oscillations f = 100 KHz

1
f= where L = L1 + L2
2𝜋√𝐿𝐶
Let L1 = 100uH, L2 = 1000uH Then C = 2303pF

TABULAR COLUMN:
Theoretical Frequency (KHz)

Practical Frequency (KHz)
RESULT: Simulated RC Phase shift Oscillator and Hartley Oscillator

using 741 Opamp, Design is verified and waveforms are
noted.

EXPERIMENT NO - 9
TITLE OF THE EXPERIMENT: Active second order Butterworth low pass

And high pass filters.
AIM OF THE EXPERIMENT: To design and realize active second order
Butterworth low pass and high pass filters.
COMPONENTS & EQUIPMENTS: Op-amp µA741, Resistors, Capacitors,

CRO, Signal Generator, Connecting Wires.
CIRCUIT DIAGRAM (i) : Second order Butterworth Low Pass Filter
Vcc = +12V, VEE = -12V

R2 = R3 = 1.59K, C1 = C2 = 0.01µf
DESIGN: For a cut off frequency, fc = 10 KHz
1
1. 𝑓𝑐 = , Assume C=0.01f, R = 1.59K
2𝜋𝑅𝐶
Choose R=1.5K For R=1.5K  and C=0.01F, fc =10.6K Hz

Rf
2. Gain of Noninverting amplifier Av = 1+
R1
For second order butter worth filter, Gain =1.586
Choosing R1= 10K, Rf = 5.86K
Note:
Gain of the filter,
𝑉𝑜 Av 1
= and fC =
𝑉𝑖 √1+(𝑓/𝑓𝑐)2 2𝜋√𝑅2𝑅3𝐶1𝐶2
R2=R3=R, C1=C2=C
PROCEDURE:
1. Test the correctness of each component.
2. Connect the Components as shown in the circuit diagram.
3. Connect the signal generator, set Vp-p >1 or 2V.
4. Vary the frequency from 0 Hz to 500 KHz in suitable steps such that the
3dB frequency values are noted.
5. Plot a graph of Gain Vs Frequency, Using semi log graph sheet.
6. Determine the cutoff frequency, Bandwidth and roll of rate.
TABULAR COLUMN:
Vin = ____ V
Frequency Vout Gain (Av)=Vout/Vin Gain(dB)=20logAv
Roll of rate = gain at 10 fc - gain at fc

Cutoff Frequency
Pass band Gain
Roll off Rate
About Low Pass Filter
LPF is a circuit which passes all the frequency components below a particular
frequency (called cutoff frequency fc) and attenuates all higher frequency
components. The rate at which it attenuates frequencies higher than fc depends
on the order of the filter. In general roll off rate is 20xn dB. Where n is the order
of the filter. Order of any filter indicates the number of poles present in the
transfer function of that filter. Hence second order filter has two poles in its
transfer function. Frequency response of an idle LPF is as shown.
Gain
PB SB
Frequency
f<fc f=fc f>fc

Roll off rate for an ideal filter is Infinite it is not practically possible to implement
such a filter as such a system is non causal (i.e., inverse Fourier transform of such
a response is a sync function, which is non causal and hence cannot be realized
practically). An active filter is the one which uses active components like
transistors, op-amps etc. Whereas passive filters are implemented only using
passive components i.e., R, L& C.
Applications:
LPF are widely used in communication i.e., during demodulation of signals, it is

used for anti-aliasing in A/D converters; it is used in PCM to band limit the voice
signal.
CIRCUIT DIAGRAM (ii) : Second order butterworth High Pass Filter

DESIGN:
For a cut off frequency of fC = 5 KHz
1. fc = 1/2πRC
Assume C=0.01F
R=3.18K
Choose R=3.3K
For R=3.3K and C=0.01F, fc =4.8 KHz
Rf
2, Gain of Noninverting amplifier Av=1+
R1
For second order filter, Gain =1.586

Choosing R1= 10K, Rf = 5.86K
𝑉𝑜 Av 1
= and fc =
𝑉𝑖 √1+(𝑓𝑐/𝑓)2 2𝜋√𝑅2𝑅3𝐶1𝐶2
R2=R3=R, C1=C2=C
PROCEDURE:
1. Test the correctness of each component.

2. Connect the Circuit as shown.
3. Connect the signal generator, set Vp-p of about 1V /2V.
4. Vary the frequency from 0 Hz to 50 KHz in suitable steps such that the
3dB frequency values are noted.
5. Plot a graph of Gain Vs Frequency, Using semi log graph sheet.
6. Determine the cutoff frequency, Bandwidth and roll of rate.
TABULAR COLUMN: Vin= ________V
Frequency Vout Gain (Av)=Vout/Vin Gain(dB)=20logAv
Roll of rate =gain at fc - gain at fc /10

Cutoff Frequency
Pass band Gain
Roll off Rate
About High Pass Filter
HPF is a circuit which passes all the frequency components above a particular
frequency (called cutoff frequency fc) and attenuates all low frequency
components. The rate at which it attenuates frequencies lower than fc depends on
the order of the filter. In general roll off rate is 10xn dB/Decade or 3xn dB/Octave
where n is the order of the filter. Order of any filter indicates the number of poles
present in the transfer function of that filter. Hence second order filter has two
poles in its transfer function Frequency response of an idle HPF is as shown.

Gain
SB PB
Frequency
f<fc f=fc f>fc
Roll off rate for an ideal filter is Infinite it is not practically possible to implement
such a filter as such a system is non causal (i.e., inverse Fourier transform of such
a response is a sync function, which is non causal and hence cannot be realized
practically). An active filter is the one which uses active components like
transistors, op-amps etc. Whereas passive filters are implemented only using
passive components i.e., R, L & C.
Application: HPF is used in communication systems to remove low frequency

noise and dc components. They are extensively used in Bio-medical signal
processing.
RESULT: Designed and realized Second order Butterworth Low Pass and High
Pass Filter.

EXPERIMENT NO - 10
TITLE OF THE EXPERIMENT: Monostable and Astable Multivibrator

using 555 Timer.
AIM OF THE EXPERIMENT: To Design and realize 555 Timer as
Monostable and Astable Multivibrator.
COMPONENTS & EQUIPMENTS: IC555, Resistors, Capacitors, Diode
BY127(D), RPS, CRO and Connecting Wires.
PIN DIAGRAM:

CIRCUIT DIAGRAM: Astable Multivibrator
THEORY:
Internal structure of an IC 555 timer is as shown
IC 555 Timer is widely used for signal modulation and to produce pulses
of duration ranging from few fractions of a micro second to hours. Internally it

consists of three 5K resistors in form of a potential divider circuit and hence the
name 555. Two comparators compare the input voltages with (1/3) VCC and (2/3)
VCC and suitably SET/RESET the RS latch Output of the latch drives the base
terminal of a NPN transistor. An inverter acts as a booster at the output (pin 3).
In an Astable Multivibrator, output across the capacitor continuously switches
between (1/3) VCC and (2/3) VCC producing the waveform as shown previously.
Below table summarizes Astable operation
Voltage S/R Output Transistor Output Vc (capacitor voltage)

of latch
Initial ---- 0 OFF --- Charges with time
constant,
Ton= 0.693[RA+RB]C,
as diode is ON RB is
short circuited.
Ton= 0.693[RA]C
Vc>(2/3)VCC S=1 1 ON 0 Discharges with time

constant
Toff= 0.693[RB]C
Vc<(1/3)VCC R=1 0 OFF 1 Charges with time
constant, diode short
ckts resistance RB
Ton= 0.693[RA]C.
Applications:
In the field of communication, Astable Multivibrator is used in generation of
PWM, PPM etc. They are used to produce Square wave of variable duty cycle
etc.

WAVEFORMS:
DESIGN:
Duty cycle of 50% and frequency= 1 K Hz
 Charging Time constant T1=Ton= 0.693[RA+RB]C

 Discharging Time constant T2=Toff= 0.693[RB]C
T1
 Duty Cycle D 
T 1  T 2 __________(1)
 T=T1+T2 =1/f, T=1ms
Choose RA = RB = R, C = 0.1 µF and for D = 50%, T1 = T2
 T1=Ton = 0.5ms = 0.693[RA]C, T2=Toff= 0.693[RB]C
Substitute for T1, T2 and D in equation (1), then RA = RB = 7.2K Ω,
Choose standard value RA = RB = 6.8K Ω, C = 0.1µF

PROCEDURE:
1. Verify the correctness of all the components.

2. Connect the circuit as shown in the figure.
3. Switch ON the RPS and set the VCC to 5V.
4. Check and note down the capacitor charging and discharging waveform at
pin 6 i.e., VC.
5. Check and note down the Astable output waveform at pin 3 i.e V0
6. Determine the Duty cycle and Time period.
7. Compare theoretical and practical Ton, Toff , T and Duty cycle.
RESULT:
Designed and Realized Astable Multivibrator using 555 Timer.
TABULAR COLUMN:
Ton
Toff
T= Ton + Toff
f = 1/T
% D = (Ton/T )x100

CIRCUIT DIAGRAM: Monostable Multivibrator
Note: Resistor Rd and capacitor Cd forms a differentiator.
THEORY:
About Monostable Multivibrator
Monostable Multivibrator is a circuit which has only one stable state which can
be 0 (or logic low) or a non-zero (logic high).
Latch/ Flip flop are one of the popular digital Bistable Multivibrator where output
will be stable (held constant) at logic LOW/HIGH until a trigger (Input) may
change its state.
In case of a Monostable Multivibrator, when a suitable trigger is applied, it
switches to the unstable state for a predetermined time before it switches back
into its stable state. Monostable Multivibrator is also known as pulse elongater
circuit.

Below table summarizes Monostable operation
Logic
Output Logic
Vc(Capacitor state of
Voltage S/R of Transistor state at
voltage) the
latch Pin 7
Output
Charges with
time constant
Initial ---- 1 ON 0 0
Ton=
0.693[RA+RB]C
On (lower
Charges with
triggering comp
0 OFF ---- time constant 1
i.e. =1)
T= 1.1[R]C
Vc<(1/3)Vcc R=1
(Upper
Vc>(2/3)Vcc comp Discharges
1 ON 0 0
=Vc =1) Rapidly
S=1
Applications: Used in generation of PWM, PPM, delay generation.
WAVEFORMS:

DESIGN:
(For a Monostable Multivibrator pulse width of 5ms)
T = 1.1RC, Let C = 0.47 µF
5ms =1.1x0.47 µF x R, R = 9.671K Ω
Choose standard value R = 10K Ω
For differentiator choose Cd = 0.01 µF and Rd=1K Ω.
Always note that for proper operation, Time period of Triggering pulse
Tt= RdCd << T
PROCEDURE:
8. Verify the correctness of all the components.

9. Connect the circuit as shown in the figure.
10.Switch ON the RPS and Set the VCC to 5V.
11.Suitably set the frequency duty cycle and width of input trigger pulse from
the signal generator Check and note down the differentiated trigger pulse
at pin 2. Increase the amplitude of the input until charging and discharging
of the capacitor is observed.
12.Check and note down the capacitor charging and discharging waveform at
pin 6.
13.Check and note down the Monostable output waveform at pin 3.
14.Determine the Time period.
15.Compare theoretical and practical time period pulse width.
Note: To get pulse input (press symmetrical button and press square wave
vary frequency to get on time greater than off time)
RESULT: Designed and Realized Monostable Multivibrator using 555 Timer.
Pulse width

EXPERIMENT NO - 11
TITLE OF THE EXPERIMENT: Simulation of Narrow Band-pass Filter and

Narrow band reject filter.
AIM OF THE EXPERIMENT: To Design and Simulate Narrow Band-pass
and Narrow band reject filter using OP-AMP uA741.
CIRCUIT DIAGRAM: Narrow Band-pass Filter
Note: Keep the initial conditions of any one of the capacitor IC = 1V.(In the capacitor
attribute window).

Select Input Source – Part name (VAC)
AC Sweep Analysis:
WAVEFORMS:
fc
Gain
|Vo / Vin|
fL fH

DESIGN:
fc = Center Frequency = 1KHz
Q = Quality Factor = 3
AF = Pass band Gain of the Filter = 10
Let C1 = C2 = C = 0.01uF
𝑄 3
R1 = = = 4.77KΩ
2𝜋𝑓𝑐 𝐶𝐴𝐹 2𝜋∗103 ∗0.01∗10−6 ∗10
𝑄 3
R2 = = = 5.97KΩ
2𝜋𝑓𝑐 𝐶(2𝑄2 −𝐴𝐹 ) 2𝜋∗103 ∗0.01∗10−6 (2∗32 −10)
𝑄 3
R3 = R4 = = = 95.5KΩ
𝜋𝑓𝑐 𝐶 𝜋∗103 ∗0.01∗10−6
Practical value of Q can be found by determining 𝑓𝑐 , 𝑓𝐻 and 𝑓𝐿 from the

frequency response curve.
𝑓𝑐
Q = 𝑓 −𝑓
𝐻 𝐿
TABULAR COLUMN:
fc
Q
AF

CIRCUIT DIAGRAM: Narrow Band-Reject Filter
Note: Keep the initial conditions of any one of the capacitor IC = 1V (In the capacitor
attribute window).
AC Sweep Analysis:

WAVEFORMS:
AF 1.0
0.8
0.6
Gain
|Vo / Vin|
0.4
0.2
0
0Hz fN 100Hz 200Hz 300Hz 400Hz 500Hz 600Hz 700Hz
V(VOUT)/ V(VIN)
Frequency
Note: To Plot Gain (Vo/Vin)

 Select Trace > Add Trace.
 In the Trace Expression text box type V(VOUT) / V(VIN) and enter
OK.
DESIGN 1:
Notch out frequency fN = 60 Hz
Assume C1 = C2 = 0.068uF
𝟏
R1 = R2 = = 39.01K
𝟐𝝅𝒇𝑵 𝑪
R3 = R1 / 2, C3 = 2C1

DESIGN 2:
Notch out frequency fN = 50 Hz
Assume C1= C2 = 0.068uF

𝟏
R1 = R2 = = 46.81K
𝟐𝝅𝒇𝑵 𝑪
R3 = R1 / 2, C3 = 2C1
TABULAR COLUMN:
Notch out frequency fN
(Design 1)
Notch out frequency fN
(Design 2)
RESULT: Simulated Narrow Band-pass Filter and Narrow band reject filter,
Design is verified and noted the frequency response.

EXPERIMENT NO - 12
TITLE OF THE EXPERIMENT: Simulation of Precision Half and Full wave

Rectifier
AIM OF THE EXPERIMENT: To Design and Simulate Precision Half and
Full Wave Rectifier using OP AMP 741 and diodes.
CIRCUIT DIAGRAM: Precision Half wave Rectifier
Select Input Source – Part name (VSIN)

Transient Analysis:
Print Step = 1ms

Final Time = 5ms
WAVE FORMS:
500mV
0V
SEL>>
-500mV
500mV
V(VIN) Gain = 1
0V
-500mV
0s 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms
V(VOUT)
Time
5.0V
Gain = 10
4.0V
3.0V
2.0V
1.0V
0V
-1.0V
V(VOUT)
Time

DESIGN 1:
Output Voltage Vout = - (R2 / R1) xVin
For Gain = 1
Select R2 = R1 = 1K
DESIGN 2:
For Gain = 10
Select R1 = 1K and find R2 from the above equation which is 10K .
TABULAR COLUMN:
Theoretical Practical (Vout/Vin)

Gain = 1 (Design 1)
Gain =10 (Design 2)
CIRCUIT DIAGRAM: Precision Full wave Rectifier
Transient Analysis:
Print Step = 1ms
Final Time = 5ms

WAVE FORMS:
500mV
0V
-500mV
V(VIN) Gain = 1
800mV
400mV
0V
SEL>>
-400mV
V(VOUT)
Time
5.0V
Gain = 10
4.0V
3.0V
2.0V
1.0V
0V
-1.0V
V(VOUT)
Time
DESIGN 1: For Gain = 1
Select R1=R2=R3=R4 = R5 =R=1K
In the positive half cycle
Vo= (R4/R3) xVin=0.5 V
In the Negative half cycle
V0= [1+R/2R](-2/3 Vin) =Vin=0.5V
DESIGN 2: For Gain = 10
R1=R2=R3 =R=1K

Select R4 = R5 = 10K
In the positive half cycle
Vo=(R4/R3) xVin=5V
In the Negative half cycle
V0 = [1+10R/2R](-2/1.2 Vin) =10 xVin=5V
Theoretical Practical (Vout/Vin)

Gain = 1(Design 1)
Gain=10 (Design 2)
RESULT: Simulated Precision Half Wave and Full Wave Rectifier. Design is
Verified and noted the waveforms.

ANALOG CIRCUITS LAB (18ECL48) Manual 2021-22-STUDENT

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Analog Circuits Lab – 18ECL48

LAB INCHARGE: SRINIVASAMURTHY R, Asst. Professor

STAFF INCHARGE: KRISHNA R, Associate Professor

MANASA P, Asst. Professor

SEMESTER: IV ECE: 2021-2022

(Approved by AICTE, New Delhi & affiliated to VTU, Belagavi)

Dept. of ECE, BIT

PROFILE OF THE LABORATORY

Name of the Laboratory : Analog Circuits Lab(18ECL48)

Semester / Year : IV / 2022

No. of Equipments : 202

Major Equipments : Oscilloscopes, Function Generators,

Area in square meters : 105.448 Sq. m

Location : 4th Floor

Total Cost of Lab : Rs. 15,95,865.00

Lab In Charge : Srinivasamurthy R,

Lab staff : Nirmala N, Gururaj L,

HOD : Dr. A.R. HEMANTH KUMAR

 Provide high quality education in the Engineering

 Develop the Institute as a leader in Science,

 Establish mutual beneficial partnerships with industry,

 Inculcate personality development through sports,

Imparting Quality Education to achieve Academic

 Create state of art infrastructure for quality education.

PEO2 To acquire sufficient knowledge base for innovative techniques in

PEO3 Capable of competing globally in multidisciplinary field.

PEO4 Achieve personal and professional success with awareness and

01 Follow the schedule time, late comers will not be permitted.

08 Don’t do the connections or remove the connections with power ON.

** You are Under CCTV Surveillance.

5. Design Adder, Integrator and Differentiator circuits using Op-Amp

Dept. of ECE, BIT

 Design analog circuits using OPAMPs for different applications.

Conduct of Practical Examination:

 All laboratory experiments are to be included for practical examination.

 Students are allowed to pick one experiment from the lot.

1. David A Bell, “Fundamentals of Electronic Devices and Circuits Lab

Dept. of ECE, BIT

ANALOG CIRCUITS LABORATORY (18ECL48) QUESTION BANK

4.(a) Design a BJT Colpitts oscillator for a frequency of 100kHz.Verify experimentally

Dept. of ECE, BIT

Dept. of ECE, BIT

Monostable and Astable Multivibrator using 555 Timer (Part- B

10 Design Monostable and Astable Multivibrator using 555 Timer. 65 - 72

2 Inverting and Non - Inverting Amplifier

Dept. of ECE, BIT

TITLE OF THE EXPERIMENT: Common Source JFET Amplifier

COMPONENTS REQUIRED: FET(BFW10/11), resistors, capacitors, DC

Common Source JFET Amplifier:

Dept. of ECE, BIT 1

JFET TERMINAL IDENTIFICATION:

From data sheet BFW10/11 specification (N channel JFET)

ID = 2mA, Vp = 8V, R0= 40KΩ, gm = 2.5mA/V

VDD = 12V, VGS = -2V, VRD = 45% of VDD = 5.4V

ID = IS = 2mA, VRS = VG – VGS = 0 – (–2V) = 2V

To find CS and CC:

X CS = RS / 10 = 100/10 =100Ω, X CS ≤ 100Ω

X CS = 1 / 2π f LCS, Cs ≥ 1 / 2π f L X 100 = 16µf (Select 22µf)

Dept. of ECE, BIT 2

Gain of CS amplifier AV = gm (RD || RL)

Required AV = 15, We get RL = 4.7KΩ

To determine Gain and Frequency Response: -