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Hetero-Dielectric Oxide Engineering on Dopingless Gate All Around Nanowire

MOSFET with Schottky Contact Source/Drain

Agamreet Kaur, Rajesh Mehra, Amit Saini

PII: S1434-8411(19)30857-X
DOI: https://doi.org/10.1016/j.aeue.2019.152888
Reference: AEUE 152888

To appear in: International Journal of Electronics and Communi-

cations

Received Date: 2 April 2019

Revised Date: 4 June 2019
Accepted Date: 27 August 2019

Please cite this article as: A. Kaur, R. Mehra, A. Saini, Hetero-Dielectric Oxide Engineering on Dopingless Gate
All Around Nanowire MOSFET with Schottky Contact Source/Drain, International Journal of Electronics and
Communications (2019), doi: https://doi.org/10.1016/j.aeue.2019.152888

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 Hetero-Dielectric Oxide Engineering on Dopingless Gate All Around
Nanowire MOSFET with Schottky Contact Source/Drain
Agamreet Kaur1, Rajesh Mehra2, Amit Saini3
1M.E. Scholar, Electronics and Communication Department, NITTTR Chandigarh, India
2Professor, NITTTR Chandigarh, India
3Cadre Design System, Ghaziabad, UP, India

ABSTRACT
In proposed work, gate oxide engineered Schottky Barrier (SB) Hetero-Dielectric (HD) Single Metal
(SM) Gate All around Nanowire MOSFET is purposed for low power digital circuitry. Proposed
device has an asymmetric oxide geometry having high-k (HfxTi1-xO2) on source side and SiO2 on drain
side with Schottky Source/Drain regions. Leakage currents are reduced to an order of 10−15 over 10−9
A as compared to conventional GAA MOSFET. Device is simpler in fabrication in contrast to
Junctionless (JL) NWFETs due to its dopingless design. Also, it has almost negligible gate induced
drain leakage (GIDL) current value. An extensive comparison is outlined between the subthreshold
performance of Single metal, Dual metal hetero-Dielectric (HD) and Gate Stack (GS) SB-SM-GAA
NWFET configurations. An improvement is observed in ON to OFF-state current ratio by 68.05% and
an impressive decline in drain induced barrier lowering (DIBL) by 48.15% in HD-SB-SM-GAA
NWFET as compared to Gate stack structure at same physical dimensions. Further, SM device has
been found to have better ION/IOFF ratio, higher transconductance, lowered DIBL and an optimum
subthreshold slope as compared to DM device.

Keywords: Charge plasma, Gate all around, Gate stack, Gate-induced drain leakage, High-K
dielectric, Short channel effects, Sub-threshold Slope.

1. Introduction

In the era of evolution of multi-gate MOSFETs, Gate All Around structure has emerged as a
promising candidate in terms of better electrostatic control. Intensive downscaling of transistors
paved way for multiple short channel effects (SCEs) out of which Drain induced barrier lowering
(DIBL) is in focus in presented work. It is the lowering of potential barrier due to widened depletion
region by high drain voltage as channel becomes short. SCEs could be suppressed largely by
embedding charge plasma technique which was first explained by Heuting et al [1]. Two essential
criterions for charge plasma to be formed are: 1) work function of metal contacts at S/D should be
less than work function of Silicon 2) thickness of substrate body must be less than Debye length as
elaborated in [2]. The charge plasma technique was initially presented for p–n diode for studying its
rectifying behavior [1, 3], the concept was further taken to bipolar transistors [4, 5], tunnel field-effect
transistor [6] and junctionless transistors (JLTs) [7]. The conventional JLTs require high uniform
doping (~1019 cm-3 ) in the Silicon channel region and a high work function of gate metal (φm ~ 5.1
eV) for fully depleting the channel. However, dopingless devices have almost intrinsic Si Nanowire
channel and gate work function requirement is also greatly reduced (~4.8eV) [8]. Metallic
source/drain contacts exhibit lower resistivity (ρc~10-9 Ω cm) at S/D interface as compared to doped
S/D junction (ρc~10-7 Ωcm)[9] giving better ON current. These Schottky barrier MOSFETs with
metallic S/D regions [10]–[12] has immensely helped downscaling of transistor devices to sub-micron
level. Schottky barrier gap (φB) between the S/D metal and the intrinsic silicon channel is a decisive
metric in determining ON-state resistance as well as low leakage current of device [13]. Proposed
device has single gate metal but gives results very close to dual metal devices thereby saving the
resources and easing the fabrication. The device (SB GAA NWFET) is utile in ultra low power sub-
threshold digital applications.
2. Device modeling

In this paper two device configurations namely, Gate Stack (GS) and hetero-Dielectric (HD) SB GAA
NWFETs are modeled in sections 2.1 and 2.2 respectively. Finally, a performance comparison on
basis of various performance metrics is carried out for both the devices in section 3.

2.1 Gate Stack (GS) Single metal (SM) Schottky barrier (SB) GAA NWFET

Calibration: Firstly, a charge plasma (CP) dopingless GAA NWFET device is designed and calibrated
with published data in Trivedi et al. [8] as shown in Fig. 1.

1.0E+00
1.0E-02 Simulated results
Drain Current, Id [A] on log scale

Referred data[8]
1.0E-04
1.0E-06
1.0E-08
1.0E-10 L=20nm
1.0E-12
tOX=2nm
VDS=0.7V
1.0E-14
1.0E-16
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Gate bias, Vgs [V]

Fig.1. Calibrated IDS-VGS characteristics

Authors et al. [8] have achieved very low OFF state drain current (IOFF) of order 10-15 in charge plasma
based gate all around NWFET working in accumulation mode. Proposed work, however focuses on
Schottky S/D, along with oxide engineering using single gate metal. In Gate Stack [14, 15]
configuration, high dielectric gate oxide, HfxTi1-xO2 having permittivity of ~50 encloses conventional
gate oxide (SiO2) in a cylindrical manner as evinced in Fig.2. Need of high-k materials arose as at
decananometer scale, SiO2 permits tunneling of electrons causing high leakages. High-k material
soars up the gate capacitance thereby reducing the OFF state device leakages and static power
consumption [16]. Hf based high-k dielectrics have been encouraged in recent research due to
enhanced thermodynamic stability, electrical properties and interface quality [17-19]. Authors et al.
[20] explained that the HfO2 films doped with TiO2 as dielectric GOX can be deposited by RF
sputtering on Silicon substrate. Fermi level pinning issue arising from HfTiO layer deposition has
been addressed by growing a passivated layer of dimethyl aluminum hydride derived aluminum
oxynitride (AlON) [21].

Gate Metal
R=10nm
Cylindrical Spacer High-k oxide thi-k=1nm Spacer R=8nm
SiO2
LS=10nm LG=20nm LD=10nm R=6nm Gate metal
Schottky Schottky High-k Oxide
Source Drain
Intrinsic Channel (Al)
R=5nm SiO
(Al) tSi=10nm Si2 Nanowire

SiO2 tSiO2=1nm

Spacer High-k oxide Spacer

Gate Metal

Fig.2. Device Schematic of GS-SB-SM-GAA NWFET

In chosen high-k oxide HfxTi1-xO2, HfO2 and TiO2 have been amalgamated to shoot up its permittivity
to as high as 50 for improving insulation potentiality. HfxTi1-xO2 film can withstand temperature as
high up to 1000 °C and can be deposited on Silicon by chemical vapor deposition (CVD) method.
CVD technique gives consistent coverage over complicated geometries and a highly adaptable growth
rate [22]. Proposed device is modelled at L=20nm, physical oxide thickness, tox = 2 nm which is
further split into 1 nm of SiO2 and 1 nm of high-k GOX (tOX = tSiO2 +thigh−k=2 nm). All other device
specifications are highlighted in Table I.

Table I. Design specifications

Symbol Parameters Values

ΦG Gate Work Function (eV) 4.81

ΦS/D Source/Drain Work Function (eV) 4.2,4.2

Lsi Si channel Length (nm) 20

rSi Radii of Si body (nm) 4,5

tOX Oxide thickness (nm) 2

LS/D Length of S/D (nm) 10

Nch Channel doping concentration (cm-3 ) 1E16

Device simulations performed for SM-GS-SB NWFET device structure at different channel lengths
revealed the leakage current (IOFF) values of 7e-14, 7.2e-15 and 1.7e-15 A for Silicon channel length
of 16,20 and 25nm respectively. Graph in Fig.3 shows that lowest leakage current is obtained at
channel length, L=25nm. This trend is highly contributed by short channel effects. Threshold
saturation and linear voltages, Vtsat and Vtlin are nearly 0.4 V.

1.0E+00
Drain current, Id on Log scale [A]

L=25nm
1.0E-02
L=20nm
1.0E-04 Vds=0.1V
L=16nm
1.0E-06
1.0E-08
1.0E-10
1.0E-12
1.0E-14
1.0E-16
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Gate Voltage, Vgs [V]

Fig.3. Leakage current variation at different channel lengths in GS device

2.2 Hetero-Dielectric (HD) Single metal (SM) Schottky barrier (SB) GAA NWFET
Rewari et al. [23] proposed a dual gate metal hetero-Dielectric [24] cylindrical GAA NWFET at
channel lengths of 30, 40 and 50 nm. The OFF-state current in purposed device modelSiO
was obtained 2

-15
quite low (of order 10 ). This work investigates the similar kind of geometry but by simply
employing single gate metal of relevant work function. Fig.4(a) shows detailed schematic of purposed
device model. Both oxides are asymmetrically distributed along the length of device i.e. Lhigh-
k+LSiO2=10+10nm with high-k being kept on Source side. It is notable that interchanging the positions
of high-k GOX and SiO2 as GOXs does not manifest any significant effect on leakage performance
of the device but poses a significant reduction in ON state current as shown in fig. 4(b).

High-k GOX Drain

Gate Metal (Φm)
Spacer Spacer Source
High-k oxide SiO2
Lhigh-k=10nm LSiO2=10n
Schottky m Schottky
Cylindrical Source (Al) Intrinsic Channel (Si) Drain (Al)
LD=10nm
tSi=10nm

High-k oxide SiO2 LSiO2=10nm

tGOX=2nm
Spacer Spacer Lhi-k=10nm
Gate Metal (Φm) Ls=10nm

Fig.4 (a) 2-D and 3-D Device Structure of HD-SB GAA NWFET

1.0E-04 1.0E-04
Drain Current, Id [A] on Linear scale

9.0E-05

Drain Current, Id [A] on Log scale

8.0E-05 1.0E-06
7.0E-05 1.0E-08
6.0E-05
5.0E-05 1.0E-10 Fig.4 (b) Current
4.0E-05 comparison of HD-SB
3.0E-05 1.0E-12 GAA NWFET device
high-k on source side
2.0E-05 high-k on drain side with altered high-k
1.0E-14
1.0E-05 positioning
0.0E+00 1.0E-16
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Gate Voltage, Vgs [V]

The gate metal work

function is kept at 4.8eV. Metal S/D regions are taken to be 10 nm long. Silicon channel is almost
intrinsic having acceptor type doping concentration (NA) of 1 X1016 cm-3. Inspected high-k oxides
are Al2O3 and HfxTi1-xO2 with their permittivities being 22 and 50 respectively. Other physical and
electrical parameters are elaborated in table I itself. The proposed device emerges as a single mask
device as mask requirement at Source/Drain region vanishes due to use of schottky metal contacts
of admissible work function. The given work investigates the figure of merits (FOM’s) such as
ION/IOFF, DIBL and subthreshold slope (SS) for the purposed device models. Also, for comparison a
dual metal (DM) SB-HD-GAA-NWFET device configuration is designed keeping physical
dimensions and dielectric configuration same. The work functions of respective metals at gate, Φm1
and Φm2 are taken as 4.6 and 4.9 eV respectively.

1.00E-04
Drain Current, Id [A] on log scale

1.00E-06
1.00E-08
1.00E-10 Fig 5.Leakage current
HD-SM-SB GAA
comparison of SM-HD,
1.00E-12 DM-HD and GS device
HD-DM-SB GAA
1.00E-14 GS- SB GAA configurations
1.00E-16
3. Device Physics
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Gate bias, Vgs [V]
1) Proposed devices are simulated using Drift-diffusion model which considered which solves set of
Poisson equation given by
∇ ⋅ ε∇ψ = −q (p − n + ND+ − NA− ) (1)

where ψ is the electrostatic potential of the vacuum level, n and p represents the electron and hole
concentration, ND+ and NA− represents the ionized doping concentrations, q is electron charge. The
lattice temperature is kept uniform throughout Drift-diffusion model.

2) The Lombardi mobility model has been introduced to address carrier mobility in the inversion
layer of proposed device. A cumulative carrier mobility spanning doping-based bulk mobility (μB),
mobility degradation, scattering due to acoustic phonon (μac) and scattering because of surface
roughness (μSR) is given by:
μ s−1 = μB−1 + μAC−1 + μSR−1 (2)

3) Carrier generation as given by Kane’s model through Band-to-band tunneling (GBB) is expressed
as:
GBB = A.BBT. E2. exp −B.BBT . EG3/2 (3)
√EG E
where E denotes electrical field magnitude, EG represents the band-gap, A.BBT and B.BBT are
experimental fitting parameters.
4) Carrier recombination mechanism considered is Shockley-Read-Hall (SRH) wherein
recombination rate is calculated as
USRH = pn − nie2 (4)
τp [n + ni eET/KTL ]+ τn [p+ ni e-E /KT ]
T L

τn and τp are carrier life time which are reliant on doping concentration, ni denotes the intrinsic carrier
concentration, ET is energy trap level, TL is lattice temperature. [25].

5) GIDL current, IGIDLα AE5/2exp(−B/EOX). (5)

Parameters A and B are temperature dependent and independent respectively, EOX is the gate oxide
electric field [26].

4. Results and Discussions

All design and simulation work is performed on COGENDA Genius 3D Device Simulation tool.
Physical models such as drift diffusion, Lombardi mobility, band-to-band tunneling (BBT), along
with Shockley-Read-Hall (SRH) carrier recombination mechanism have been incorporated in
presented study. Fermi-Dirac model has been inculcated in order to determine electron and hole
distribution. Study spans following aspects related to device performance:

4.1 Impact of different high-k materials

Using HfxTi1-xO2 and Al2O3 as high-k GOXs, simulation study reveals that a lower leakage
(IOFF=2.43x10-15 A) in case of HfxTi1-xO2 is obtained owing to its high insulation capability due to
high permittivity value. ID-VG trend for the same is given in Fig. 6(a) at linear drain-source voltage,
Vdslin of 0.1V. Linear and saturation threshold voltages, Vtlin and Vtsat are found be nearly 0.4 V.
Extremely low leakages have been obtained as in [23] but employing single gate metal; thereby
reducing the resource consumption. Leakage at gate is verified for both modeled devices which is
found to be nearly negligible.

4.2 Transconductance (S/µm) and TGF (V-1)

 An important analog performance metric is transconductance (gm) which indicates device efficiency
in terms of effective voltage conversion into the current. Transconductance generation factor (TGF)
given by gm /IDS is another FOM, which indicates how efficiently a device converts current into
transconductance [2]. Variation of gm as well as TGF for all three devices with respect to applied gate
bias VGS in shown in Fig. 6(b). It is clear from the graph that highest transconductance is found in
SM-HD device as compared to both other devices.

1.0E-04

1.0E-06

1.0E-08
VDS=0.1V
Log(Id) [A]

1.0E-10

1.0E-12
HfxTi1-xO2
1.0E-14 Al2O3

1.0E-16
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Gate Voltage,Vgs [V]

120 6.0E-05

Transconductance,gm (S/µm)
(a) 100 5.0E-05

80 4.0E-05
TGF (V-1)

60 3.0E-05

40 2.0E-05

Vds=0.1V
20 1.0E-05 gm_SM_HD
TGF_SM_HD
gm_GS
0 0.0E+00
TGF_GS
0 0.050.10.150.20.250.30.350.40.450.50.550.60.650.70.750.80.850.90.95
gm_DM_HD
Gate voltage, Vgs [V] TGF_DM_HD

(b)
Fig.6. (a) IOFF comparison between Al2O3 and HfxTi1-xO2 as high-k GOXs (b) Transconductance (gm) and
TGF comparison of GS, SM and DM-HD-SB-NWFET devices
4.3 Channel Potential (V) and Electric Field (V/cm)

A horizontal cut-line is marked at the center of core as well at surface of the structure along the z-
axis keeping VGS and VDS both at 0.1 V. Potential variation at center of silicon wire core as well as at
surface along channel length with different permittivities of high-k GOX (keeping VDS and VGS both
0.1V) is depicted in Fig. 7(a). The potential at the outermost edges of the metal contact S/D junctions
is higher because of appended side contacts having lower work function. It is clear from Fig. 7(a) that
as the permittivity of GOX appended on source side increases, the minimum surface potential is
shifted towards the source. The effective gate capacitance increases with rise in permittivity which
increases the gate-channel coupling lowering the channel center potential.

1.2 35
Vds=0.1V Vgs=1V
1.1 core_k=50 30
Vds=0.1V Vg=0.1V
1 core_k=22 ) 25
surface_k=50
0.9
V/cm
surface_k=22 20
05
Potential(V)

0.8 E(x1 15

0.7 10

0.6 5
0.5 0
0.4 101112131415161718192021222324252627282930
Channel position(nm)
0.3 Gate Oxide along channel length(nm)

(a) (b)

Fig. 7(a) Surface and core potential profiles with different permittivities of high-k GOX (b) Electric field in
GOX region vs channel length of HD-SB-SM-GAA NWFET device

Fig. 7(b) shows Electric field, E(V/cm) distribution along channel length in asymmetric gate oxide
region at drain bias, VDS=0.1 V and gate bias, VGS=1V as well as VDS=0.1 V, VGS=0.1V. When device
is in ON state, presence of high-k material lowers the electric field at the source side due to fringing
effect providing enhanced controllability over the channel. Simulated results of HD device geometry
are compared with dual material charge plasma technique based Gate Stack device proposed in [2].
Leakage current is found slightly reduced on calibrating results at at r=5nm and ON current is
improved too as shown in plot in Fig. 8(a).

4.4 Hot Carrier Effects

To study its impact on device performance, the direct tunnelling model, which also includes Fowler
Nordheim (FN) tunnelling mechanism and hot carrier injection by lucky electron model have been
considered. For SM device, as seen from graph, VTH is common for both conventional and HCE model
simulations, hence no effect on device performance in terms of DIBL and SS is observed. However
increased leakages have deteriorated ION/IOFF ratio from 7.1e10 to 4.3e7 as shown in figure 8.
However in DM configuration, higher work function gate metal act as accelerator and another as
screen gate thereby providing suppressed leakages with reduced HCEs [9]. Overall leakages after
incorporating tunneling and HCEs in proposed device design are at par with DM configuration as
visible from figure 8. Lastly, OFF state leakage current has increased with HCE incorporation in GS
structure.

1.0E-04

1.0E-06

1.0E-08
Id, Log Scale [A]

SM_Conventional
1.0E-10
SM_With HCE
DM_Conventional
1.0E-12 DM_With HCE
GS_Conventional
1.0E-14 GS_With HCE

1.0E-16
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Vgs [V]
 Fig. 8 Impact of HCEs on leakage current in both SM and DM HD devices

4.5 GIDL current

Gate-induced drain leakage (GIDL) current is found to be almost negligible for the purposed device
in the order of 10-14. GIDL current increases with rise in temperature under low electric field as
explained by eq.(11) which can be described by SRH model [24]. Fig.9(b) highlights this trend for
Hetero-Dielectric device at r=5nm.

1.00E-02
1E-09
(a)
1.00E-04
(b)
Drain Current, Id [A/µm]

1E-10
1.00E-06 Fig. 9 (a). Comparison analysis of purposed HD
device with published results in [2] (b) GIDL
GIDL Current [A]

1E-11 VDS=0.9V
1.00E-08 Referred data at current variation with temperature
1E-12 r=5nm [2]
1.00E-10 Simulated data at DS V = 0.1V
r=5nm 4.6 Sub-threshold Slope V(mV/dec)
GS= -0.5V
and
1.00E-12
1E-13 Simulated data at ION/IOFF parameter
r=4nm

1.00E-14 1E-14 SS is a measure of change in gate voltage for a

300 decade change in drain current and is calculated
350 400 450 500 550
0

1
1

9
0.

0.

0.

0.

0.

0.

0.

0.

0.

Gate Voltage,Vgs
Temp.(K) [V] mathematically
SS =∂ VG
/∂ log10ID (8) By introducing a reduced channel thickness
parameter, comparative performance analysis of both the devices is summarized in Table II.

Table II. Comparative analysis of both devices in nMOS configuration at different radii
Parameters GS-GAA-NWFET SM-SB-HD-GAA-NWFET DM-SB-HD-GAA-NWFET
rSi=4nm rSi=5nm rSi=4nm rSi=5nm rSi=4nm rSi=5nm

Vthlin (V) 0.3926 0.3681 0.4003 0.3809 0.4031 0.3774

Vthsat (V) 0.3737 0.3344 0.3904 0.3617 0.3238 0.2798

DIBL(mV/V) 21.1 37.4 10.96 21.28 88.15 108.5

Sslin(mV/dec) 63.76 67.02 61.76 63.88 54.07 62.53

ION/IOFF 5.75E+09 1.7E+09 1.8E+10 7.1E+09 3E+07 6.86E+06

It can be observed that HD-SB-GAA NWFET exhibit Sub-threshold Slope of 62.1 mV/dec at tSi=8nm,
Vdslin=0.1V which is closest to ideal value of 60mV/dec at room temperature. Such a low SS aids in
faster switching of the transistor device. SS and ION/IOFF parameter of both devices are summarized
in Fig.10(a) and 10(b) respectively. Also, HD configuration has higher ION/IOFF parameter by 68.05%
and 76.06% at tSi=8nm and tSi=10nm respectively as compared to gate stack (GS) configuration. This
is mainly because of direct contact of Si channel with high-k insulating layer. Results are studied for
varying Nanowire channel thickness (tSi) which addressed better performance of device with a
narrower channel. Also, results in table II reveal a higher DIBL value in case of DM-SB-HD-GAA-
NWFET as compared to SM-SB-HD-GAA-NWFET manifesting latter to be more resilient to short
channel effects. Additionally, a superior ION/IOFF ratio is obtained in single metal device than dual
metal configuration.

4.7 Drain Induced barrier Lowering (DIBL)

DIBL is lowering of threshold voltage on application of drain-source voltage. It is a short channel

effect which comes into play on downscaling devices to nano dimension. The subthreshold region
signifies the rate of fall of current on application of a gate bias voltage [27]. DIBL for r=5nm and
4nm declined by 43.1% and 48.05% respectively in HD device configuration than GS geometry.
Reason can be owed to higher VT and barrier height providing lower band-to-band tunneling (BTBT).
Consequently, device evinces lower leakage causing massive decline in DIBL value. DIBL values
for both devices are comparatively displayed in Fig. 10(c). Fig. 10(d) highlights DIBL variation with
drain bias voltage for both single metal and dual metal HD configurations.
Subthreshold Slope, SS (mV/dec)
68 18.00
tsi=8nm 67.02
67 16.00
tsi=10nm
tsi=10nm
)
66 14.00
tsi=8nm
109
65 12.00
63.88
(X
63.76
SS(mV/dec)

64
10.00
Ion/Ioff

63
61.76 8.00
62
6.00
61
4.00
60
59 2.00
HD-SB NWFET GS-SB NWFET 0.00
HD-SB NWFET GS-SB-NWFET

(a) (b)

120
DIBL(mV/V)
40 37.4 DM-SB-GAA NWFET

35 100 SM-SB-GAA NWFET

tsi=10nm
30 tsi=8nm
80
25
DIBL (mv/V)

21.27 21.08
20 60
15
10.96 40
10

5 20
0
HD SB NWFET GS SB NWFET
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Vds [V]

(c) (d)

Fig.10. (a) Subthreshold slope, Sslin (mV/dec) (b) ION/IOFF (c) DIBL (mV/V) for GS and SM-HD devices at
different tSi (d) DIBL variation with drain source bias
4.8 pMOS Configuration design

Further, since HD geometry demonstrate superior performance to GS device, pMOS configuration

for SM-SB-HD-GAA NWFET is purposed. Design parameters taken are, channel length, L=20nm,
Silicon thickness of 10nm, oxide thickness of 2nm for threshold region operation at Vdslin=0.1V. In
order to match leakage and ON currents in both pMOS and nMOS configurations, work function
engineering has been employed. Threshold saturation and linear voltages, Vtsat and Vtlin are nearly 0.4
V. ID-VGS characteristics of nMOS and pMOS structures making a V-curve are shown in Fig.11.

1.00E-04

VDS=-0.8V VDS=0.8V

Drain current, Id [A]

1.00E-06
VDS=0.1V
VDS=-0.1V
1.00E-08
VDS=0.1V

1.00E-10
pmos_lin
nmos_lin
nmos_sat
1.00E-12 pmos_sat

1.00E-14

1.00E-16
0

1
-1
.9
.8
.7
.6
.5
.4
.3
.2
.1

1
2
3
4
5
6
7
8
9
0.
0.
0.
0.
0.
0.
0.
0.
0.
-0
-0
-0
-0
-0
-0
-0
-0
-0

Gate Voltage,Vgs [V]

Fig.11. ID-VGS characteristics for pMOS and nMOS HD structures at L=20nm.

Simulated parameters influencing device performance are compared and highlighted in Table III.
Threshold linear voltage, Vtlin for pMOS configuration of GS and HD devices are found to be 0.35V
and 0.37V respectively. SS of pMOS HD model is lower making device specifically apt for faster
switching applications. Further, ID- VDS characteristics are plotted for HD nMOS as well as pMOS
configuration as shown in Fig.12.

Table III . Comparative analysis of pMOS configuration of both devices

Parameters SM-SB-GS-GAA-NWFET SM-SB-HD-GAA-NWFET

DIBL(mV/V) 38.69 25.72

Sslin (mV/dec) 67.02 64.06

ION/IOFF 6.88E+08 2.8E+09

 1.8E+01 Id-Vds Curve 1.8E+01

1.6E+01 VGS=0.9V VGS=0.9V 1.6E+01

VGS=0.8V

nmos Drain Current, Id [µA]

1.4E+01 1.4E+01

pmos Drain current, Id [µA]

VGS=0.8V
1.2E+01 1.2E+01

1.0E+01 1.0E+01
VGS=0.7V
8.0E+00 8.0E+00
VGS=0.7V
6.0E+00 6.0E+00

4.0E+00 4.0E+00

2.0E+00 VGS=0.4V 2.0E+00

0.0E+00 0.0E+00
1
2
3
4
5
6
7
8
9
0

1
0.
0.
0.
0.
0.
0.
0.
0.
0.
Drain Voltage, Vds [V]

Fig.12. ID-VDS characteristics for pMOS and nMOS HD configuration

5. CONCLUSION
Overall device modeling analysis concludes that Hetero-Dielectric Schottky Barrier GAA NWFET
on single metal is a powerful design for utility in low power digital circuitry. It shows lower OFF state
current of approx. 2.4x10-15 A, suppressed SCEs with much lower DIBL of 10.96 mV/V. Device has
magnificent subthreshold region performance with a sub-threshold slope of 61.76 mV/dec. With
reduced leakages, it manifests extremely low static power consumption making it highly apt for low
voltage, low power digital applications. High permittivity oxides reduce leakage current more
efficiently in Hetero-Dielectric configuration as in Gate stack geometry. This can be owed to direct
contact of high-k insulator with channel in HD configuration. As device use Schottky Source/Drain
regions, there is no requirement of mask in fabrication process at S/D region rendering the fabrication
process inexpensive and simpler. Further, the behavior of p/nMOS HD GAA NWFET is studied in
linear and saturation region. As compared to DM device, SM device has better ION/IOFF ratio, lower
DIBL, higher transconductance, at par HCEs and near to ideal subthreshold slope.

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Authors’ bio:

Agamreet Kaur: Agamreet Kaur completed her Bachelor of Technology in 2017 and is currently
pursuing Masters of Engineering degree at Electronics and Communication Engineering Department
at National Institute of Technical Teacher Training & Research, Chandigarh, India. Her research areas
include semiconductor physics and VLSI design.

Dr. Rajesh Mehra: Dr. Mehra is presently Head of Electronics and Communication Engineering
Department at National Institute of Technical Teacher Training & Research, Chandigarh, India. He
has received his Doctor of Philosophy and Masters Degree in Electronics & Communication
Engineering from Punjab University, Chandigarh, India. Dr. Mehra has completed his Bachelor of
Technology from NIT, Jalandhar, India. Dr. Mehra has 22 years of Academic Experience along with
10 years of Research Experience. He has nearly 500 publications in Refereed Peer Reviewed
International Journals and International Conferences. Dr. Mehra has guided more than 100 PG
scholars for their ME thesis work and also guiding 03 independent PhD scholars in his research areas.
His research areas include VLSI Design, Digital Signal & Image Processing, Renewable Energy and
Energy Harvesting. He has authored one book on PLC & SCADA.Dr. Mehra is senior member IEEE
and Life member ISTE.

Mr. Amit Saini: Mr. Saini is TCAD expert at Cadre Design Systems. His areas of research are nano-
devices and semiconductor physics.