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-- Company:
-- Engineer:
--
-- Create Date: 08/19/2022 01:48:45 PM
-- Design Name:
-- Module Name: adt7420_intento1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
library ieee;
use ieee.std_logic_1164.all;
entity adt7420_intento1 is
port(clk_100MHz, rst: in std_logic;
scl: out std_logic;
sda: inout std_logic;
led: out std_logic_vector(10 downto 0)
);
end entity;
architecture Behavioral of adt7420_intento1 is
type state is (st_idle, st0_start, st1_txSlaveAddress, st2_ack1,
st3_txAddress, st4_ack2, st5_restart, st6_txSlaveAddress, st7_ack3, st8_rd_data,
st9_nack, st10_stop);
signal DataOut: std_logic_vector(7 downto 0);
constant Address_tobe_Read: std_logic_vector(7 downto 0):=x"0b";
constant slave_address_with_rd_flg: std_logic_vector(7 downto 0):=x"97";
constant slave_address_with_wrt_flg: std_logic_vector(7 downto 0):=x"96";
signal scl_buss: std_logic:='0';
signal dcl_buss: std_logic:='0';
constant max_length: integer:=8;
signal present_state,next_state :state ;
shared variable data_index: integer range 0 to max_length -1;
signal timer: integer range 0 to max_length; signal clk_400KHz:
std_logic:='0';
signal ack_bits: std_logic_vector(2 downto 0);
signal count: integer range 0 to 250:=0;
signal sda_signal, scl_signal: std_logic;
signal rd_flag: std_logic:='0';
begin

clk400KHz: process(clk_100MHz)
begin
if(rst='1') then
clk_400KHz<='0';
count<=0;
elsif(rising_edge(clk_100MHz)) then
if(count=124) then
clk_400KHz <= not clk_400KHz;
count <= 0;
else
count<=count + 1;
 end if;
end if;
end process;

clk_100KHz: process (clk_400KHz)

variable count_1: integer range 0 to 3:=0;
begin
if(rst='1') then
scl_buss<='1';
dcl_buss<='1';
count_1:=0;
elsif(rising_edge(clk_400KHz)) then
if(count_1=0) then
scl_buss<='0';
elsif(count_1=1) then
dcl_buss<='1';
elsif(count_1=2) then
scl_buss<='1';
else
dcl_buss<='0';
end if;
if(count_1=3) then
count_1:=0;
else
count_1:=count_1 + 1;
end if;
end if;
end process;

p1: process(dcl_buss, rst)

begin
if (rst ='1') then
present_state<=st_idle;
data_index:=0;
elsif (dcl_buss 'event and dcl_buss ='1') then
if(data_index=timer-1) then
present_state<=next_state;
data_index:=0;
else
data_index:=data_index +1;
end if;
end if;
end process;

led(7 downto 0)<=DataOut(7 downto 0);

led(10 downto 8)<=ack_bits;

p2: process(dcl_buss, rst)

begin
if(dcl_buss'event and dcl_buss='0') then
if(present_state=st2_ack1) then
ack_bits(0)<=sda;
elsif( present_state=st4_ack2) then
ack_bits(1)<=sda;
elsif (present_state=st7_ack3) then
ack_bits(2)<=sda;
elsif (present_state=st8_rd_data) then
DataOut(7-data_index)<=sda;
end if;
end if;
end process;

scl<=scl_signal;
sda<=sda_signal;

p3: process(present_state, scl_buss, dcl_buss, sda)

begin
case present_state is
when st_idle =>
scl_signal<='1';
sda_signal<='1';
timer<=1;
if(rd_flag='1') then
next_state<=st_idle;
else
next_state<=st0_start;
end if;

when st0_start =>

sda_signal<=dcl_buss;
scl_signal<='1';
timer<=1;
next_state<=st1_txSlaveAddress;

when st1_txSlaveAddress =>

sda_signal<=slave_address_with_wrt_flg(7-data_index);
scl_signal<=scl_buss;
timer<=8;
next_state<=st2_ack1;

when st2_ack1=>
sda_signal<='Z';
scl_signal<=scl_buss;
timer<=1;
next_state<=st3_txAddress;

when st3_txAddress =>

sda_signal<=Address_tobe_Read(7-data_index);
scl_signal<=scl_buss;
timer<=8;
next_state<=st4_ack2;

when st4_ack2=>
sda_signal<='Z';
scl_signal<=scl_buss;
timer<=1;
next_state<=st5_restart;

when st5_restart =>

sda_signal<=dcl_buss;
scl_signal<='1';
timer<=1;
next_state<=st6_txSlaveAddress;

when st6_txSlaveAddress =>

sda_signal<=slave_address_with_rd_flg(7-data_index);
scl_signal<=scl_buss;
timer<=8;
 next_state<=st7_ack3;

when st7_ack3 =>

sda_signal<='Z';
scl_signal<=scl_buss;
timer<=1;
next_state<=st8_rd_data;

when st8_rd_data =>

sda_signal<='Z';
scl_signal<=scl_buss;
timer<=8;
next_state<=st9_nack;

when st9_nack=>
sda_signal<='1';
scl_signal<=scl_buss;
timer<=1;
next_state<=st10_stop;

when st10_stop =>

sda_signal<=not dcl_buss;
scl_signal<='1';
timer<=1;
rd_flag<='1';
next_state<=st_idle;

end case;
end process;
end Behavioral;