Unit : Computational logic 

1. Radix and Number system

a. Questions based on radix. size. value 

 
        i. Find the value of X, (135)x + (144)8 = (214)x + 2 
 
        ii. (470.56)16 - (297.55)16 
 
      iii. (271.05)8 - (475.235)16  
 
        iv. if(136)10 = (210)x what is x  
 
        v. (88)16 = (?)10  
 
        vi. (1551/443)r = (3)10  
 
        vii. (104010401)8 = (1101101)?  
 
        viii. (156088/123)10 = (710)r what is r  
 
        ix. (221505)8 = (12345)r what is r  
 
        x. (512/41)r = 10, what is r.  
 
        xi. (1A53)16= ? 
 
        xii. (734)8 = (?)16 .
 
 
b. If (84)x (in base-x number system) is equal to (64)y (in base-
y number system), then possible values of x and y  are
  (A) 12, 9 
          (B) 6, 8 
(C) 9, 12  
(D) 12, 18
 
 
c.  Consider the addition of number with different bases 
 
                i. (x)7 + (y)8 +(w)10 +(z)5 = (k)9   
                ii. if x = 36, y = 67, w = 98, k = 241 then find the value of z.
 
 d. The minimum decimal equivalent of the number 
(21A)x is
 
(A) 538  
(B) 1032 
(C) 263  
(D) 220
 
 
Answer- C 

e. The base of the number system for which the following operation
is to be correct 66/5 = 13

a.         
b. (A) 6 

c.         
d. (B) 7 

e.         
f. (C) 8

g.         
h.  (D) 9
 i.         
j. Answer- D

k.     

    

f.     
g. In expression (11A1B)8 = (12CD)16, A and B represent positive
digits in octal number system, and C and D have their original
meaning in hexadecimal. Find the values of A and B?
    

a.         
b. (A) 2, 5 

c.         
d. (B) 2, 3 

e.         
f. (C) 3, 2 

g.         
h. (D) 3, 5
 i.         
j. Answer-D

k.     

    

 
 
 
 
 
 

2.     
3. Complements
 
    

a.         
b. 1's and 2's complement of -19.

c.         
d. find out 2s complement of -45 with 8 bit representation 

e.         
f. Subtract ABCD from ABCD using 16's complement 
 g.         
h. consider the system ‘s’ as shown in figure below
        

a.             
b.
          

            
            
            system
S: performs 1s compliment of the input
and then 2s complement to produce the output

c.         

        

i.     

    

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

1.     
2.
    

1.         
2.
        

b.             
c. system H:3 cascaded system ‘S’

d.         

        
 3.     

    

 
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

1.     
2.
    
 1.         
2.
        

c.             
d. if the input is applied (I3, I2, I1, I0) is 1010, then what
is the output (o3, o2, o1, o0)

e.         

        

3.     

    

 
 
 
 
 
 

1.     
2.
    

1.         
2.
        

d.             
e. The 10’s complement of (843)11 is
 
            

1.                 

2. (A) (157)11

3.                 

4. (B) (267)11 

5.                 

6. (C) (156)11 

7.                 

8. (D) (268)11

9.                 

10. Answer- B

11.             

             

f.             
g. The two numbers represented in signed 2’s
complement

h.         

        

3.     

    

 
 
 
form are P = 11101101 and Q = 11100110. If Q
 
 
is subtracted from P, the value obtained in signed 2’s
 
 
complement form is 
 
 
(A) 100000111 
 
 
(B) 00000111
 
 
 (C) 11111001 
 
 
(D) 111111001
 
 
Answer- B
 
 

1.     
2.
    

1.         
2.
        

f.             
g. X = 01110 and Y = 11001 are two 5-bit binary numbers

h.         

        

3.     

    

 
 
 
represented in two’s complement format. The
 
 
sum of X and Y represented in 2’s complement format
 
 
using 6 bits is:
 
 
(A) 100111 
 
 
(B) 001000
 
 
(C) 000111
 
 
                                (D) 101001
 
 
Answer- C
 
 

1.     
2.
    

1.         
2.
        

g.             
h. A number in 4-bit two complement signed
representation
 i.         

        

3.     

    

 
 
 
is a3 a2 a1 a0. The same number, when stored using
 
 
8 bits will appear like.
 
 
(A) 0000 a3 a2 a1 a0
 
 
(B) a3’ a3’ a3’ a3’ a3 a2 a1 a0
 
 
(C) a3 a2 a1 a0 a3 a2 a1 a0
 
 
(D) a3 a3 a3 a3 a3 a2 a1 a0
 
 
Answer- D
 
 

1.     
2.
    

1.         
2.
        

h.             
i. 8-bit 2’s complement representation a decimal
number is 10000000. The number in decimal is
 
            

1.                 

2.
                

i.                     

ii. (A) +256 

iii.                     

iv. (B) 0 

v.                     

vi. (C) -128 
 vii.                     
viii. (D) -256

ix.                 

                

3.             

            

j.         

        

3.     

    

 
 
 
Answer- C
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

3.     
4. Logic gates, realization
 
    

a.         
b. Implement 3 input NAND gate using minimum number 2
input NAND gates 

c.         
d. Design an inverter using XOR gate 

e.     

    

 
 
 
c.  Gates using other gates 
 
 
d. Implement Buffer and inverter using XOR gates 
 
 
e. Implement 2 bit comparator using 1 bit comparator 
 
 
f. Applications of buffer 
 
 
g.  AB+BC+CA 
 
 
                i. Implement only using NAND 
 
 
                ii. Implement only using NOR 
 
 
               h. Two I/P nand gate to inverter 
 
 
               I .Y=AB~CD + A~C~D+B~DC+~BCD using NAND gates
 
 
               j. Implement the following function using fewer number of
NOR gates F=M(23,4,6,7) 
 
 
              k. Assume an X-gate whose outputs is ~pq, if P and q are the
inputs using the AND & OR gate. 
 
 
              l. Give two ways of converting a two input NAND gate to an
inverter. 
 
 
                   m. Convert XOR gate in to buffer and an inverter (using
only one XOR gate).
 
 
            n. The output of a logic gate is 1 when all its inputs are at logic
0. the gate is either 
 
 
                a. (A) a NAND or an EX-OR (B) an OR or an EX-NOR 
 
 
                b. (C) an AND or an EX-OR (D) a NOR or an EX-NOR 
 
 
             o. The output of an exclusive -OR gate is high if ___________  
 
 
             p. Give the transistor level circuit of a CMOS NAND gate. 
 
 
             q. Draw the I-V characteristics of CMOS inverter? And explain
CMOS latchup? 
 
 
r. When a logic gate is driving another logic gate,  the condition
which must be satisfied for proper
 
 
operation is
 
 
(A) VOH > VIH and VOL > VIL
 
 
(B) VOH < VIH and VO L > VIL
 
 
(C) VOH > VIH and VOL < VIL
 
 
(D) VOH < VIH and VOL < VIL
 
 
Answer – C
 
 
    s. The minimum number of NAND gates required to implement
A ⊕ B ⊕ C is
 
 
(A) 8 (B) 10 (C) 9 (D) 6
 
 
 
 
 
Ans: A
 
 
 
 
 
             t. An OR gate has six inputs. How many input words are  there
in its truth table?
 
 
(A) 6 (B) 36 (C) 32 (D) 64
 
 
Ans:D
 
 
u. The minimum number of two input NOR gates are required to
implement the simplified value    of  the following equation
 
 
f(w, x, y, z) = ∑m(0, 1, 2, 3, 8,9 10,11)
 
 
(A) One (B) Two (C) Three (D) Four
 
 
 
 
 
Answer: A
 
 
v. The output of a logic gate is ‘1’, when all inputs are at  logic ‘0’.
Then, the gate is either
 
 
(1) NAND or XOR gate
 
 
 (2) NOR or XOR gate
 
 
(3) NOR or XNOR gate
 
 
(4) NAND or XNOR gate
 
 
 
 
 
(A) 1 and 2 (B) 2 and 3
 
 
(C) 3 and 4 (D) 4 and
 
 
Ans: C
 
 
w. A three-input majority gate is defined by the logic     
function M(a, b, c) ab bc ca. Which one of
 
 
the following gates is represented by the function
 
 
M (M (a,b,c)’,M (a,b,c’),c) ?
 
 
(A) three-input NAND gate
 
 
(B) three-input XOR gate
 
 
(C) three-input NOR gate
 
 
(D) three-input XNOR gate
 
 
Ans. B
 
 

1.     
2. For the following circuit, the output Y is

 
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
(a) P’ + Q’ + R’ + S’
 
 
(B) P+Q+R+S
 
 
(C)PQRS
 
 
(D) (P+Q)(R+S)
 
 
Answer- B
 
 

2.     
3. The logic circuit for the figure is

 
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
(a) Half adder
 
 
(b) XOR
 
 
                                (c) Full adder
 
 
(d) Equality detector
 
 
Answer- D
 
 

3.     
4. Which of the following statement/s is/are true

 
 
 
S1: The dual of NAND function is NOR
 
 
S2: The dual of XOR function is XNOR
 
 
(A) S1 and S2 are true
 
 
 (B) S1 is true
 
 
(C) S2 is true
 
 
(D) None of these
 
 
Answer: A
 
 

4.     
5. If the following circuit is converted to all-NAND network,

 
 
 
then how many number of NAND gates are
 
 
required? (inverted inputs are available)
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
(A) 3 (B) 4
 
 
(C) 5 (D) 6
 
 
 
 
 
 Answer: A
 
 

5.     
6. Match the logic gates in Column I with their

 
 
 
Equivalents in Column II shown in the following table.
 
 
 
 
 
 
 
 
 
 
(a) P-2, Q-4, R-1, S-3 
 
 
(b) P-4, Q-2, R-1, S-3
 
 
(c) P-2, Q-4, R-3, S-1
 
 
 (d) P-4, Q-2, R-3, S-1
 
 
Answer- D
 
 
 
 
 

6.     
7. The point P in the following figure is stuck at 1.
  
 
 
The output f will be
 
 
 
 
 

 
 
 
 
 
(a) (ABC’)’ 
 
 
(b) A’
 
 
 (c) ABC’
 
 
(d) A
 
 
Answer- D
 
 

7.     
8. How many two-input EX-NOR gates can be used to

 
 
 
implement one three-input EX-NOR gate function?
 
 
(a) 1
 
 
(b) 2
 
 
(c) 3
 
 
(d) 4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
4.     
5. Mux based questions
 
    

a.         
b. Bigger mux using smaller mux 
 
        

i.             
ii. 5x1 mux using 2x1 mux 

iii.             

iv. 2.1 mux using 4xl mux 

v.         

        

c.         
d. Gates using mux 
        

i.             
ii. 2 Input AND gate using mux 
 iii.             
iv. 3 Input AND gate using MUX 

v.             
vi. Design a FA using 4.1 Mux and single inverter 
            

1.                 

2. 2X1 mux only 

3.             

            

vii.             

viii. Design FA using HA 

ix.             

x. Design 4 bit FA using 2 bit FA 

xi.             

xii. Design 10x1 mux using 3 4X1 mux 
 xiii.             
xiv. 8x1 mux using 4xl and 2x1 mux 

xv.             

xvi. XOR using 2x1 mux

xvii.             

xviii. XOR using NAND gate

xix.             

xx. 2 input and gate usign 2x1 mux

xxi.             

xxii. design full adder using
            

1.                 

2. 8x1 mux

3.                 

4. 4x1 mux

5.             

            
 xxiii.             
xxiv. Design 16x1 mux using
            

1.                 

2. 8x1 mux

3.                 

4. 4x1 mux

5.             

            

xxv.             

xxvi. design 4x1 mux using decoder and tristate buffer

xxvii.             

xxviii. implement NAND gate using NOR gate

xxix.         

        
e.         
f. use XOR gate to implement
        

i.             
ii. comparator

iii.             

iv. inverter

v.         

        

g.         
h. Mux using gates
        

i.             
ii. 3x1 Mux using 2X1 mux'S (2) with following selection
requirement 
            

1.                 

2. If AB==00, Select i0 
 3.                 
4. if AB==01, select i3 

5.                 

6. if AB==10. select i2 

7.             

            

iii.         

        

i.         
j. 2x1 max using NOR gate

k.     

    

 
 
 
f.     F(a,b,c,d) = M(1,2,3,5,6,8,10) using 
 
 
                                a. 2x1 mux 
 
 
                                b. 4x1 mux 
 
 
        g. F(a.b.c.d)= M(1.3.5.9.11.13) using 
 
 
                                a. 2x1 mux 
 
 
                                b. 4x1 mux 
 
 
                h.    Design 8xl mux using 2:4 decoder gates 
 
 
                         i.      F(w1, w2, w3, w4, w5) = ~w1~w2w4~w5 +
w1w2 +w1w3 + w1w4 + w3w4w5 using
 
 
                                a. 4x1 mux
 
 
                                b. 2x1 mux 
 
 
       j.     Implement 4x1 Mux using tri state buffer and a decoder 
 
 
       k.     Design half adder using 2x1 MUX 
 
 
              l.     what is the output for below circuit in terms x,y,z
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   m. The number of control lines for a 8 - to - 1 multiplexer is? 
 
 
    n. Design a combinational logic circuit with four 2x1 mux
which works as HA and FA. If control input is '1' circuit
should work as HA, else as HA. assuming that no
complemented inputs are available
 
 
            o. Write truth table for 3x1 Mux 
 
 
p. What is the status of the inputs S0, S1, and S2 of the 74151
eight-line multiplexer in order for the output Y     to be a copy of
input I5? 
 
 
                a. SO = 0, S1=1, S2=0 
 
 
                b. SO = 0, S1 =0, S2=1 
 
 
                c. S0=1, S1=1, S2=0 
 
 
                d. S0=1, S1=0, S2=1
 
 
        q. Consider the logic circuit given below
 
 
 
 
 
 
 
 
 
 
 
 
 
Input in all the line I13 in 16x1 Mux corresponds to o/p at line bar of
16 Demux, find the value of n.
 
 
                r. The output of the following Multiplexer circuit is
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
(A) x’ + yz 
 
 
(B) x’ y+ z
 
 
(C) (x’ + y)z
 
 
 (D) x’ y’ + yz + xy’z
 
 
Answer- B
 
 

s.     
t. What are the minimum number of 2-to-1 multiplexer required to
generate a two-input AND gate and a two-input EX-OR gate?

 
 
 
(a) 1 and 2 
 
 
(b) 1 and 3 
 
 
(c) 1 and 1
 
 
                        (d) 2 and 2
 
 
Answer- C
 
 

t.     
u. The output f of the 4 to 1 Mux shown in the figure is

 
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
(a) XY + X
 
 
(B) X+Y
 
 
(c)X’ + Y’
 
 
(D) X Y’ + X
 
 
ANSWER – B
 
 

u.     
v. The output Q of the circuit is

 
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 
 
 
 
 
(a) A’B’C
 
 
(b)A+B+C
 
 
(c) AÅBÅC
 
 
(d)A’ B’ C’
 
 
Answer- C
 
 

v.     
vi. In the following circuit X is given by

 
 
 
 
 
 
 
 
 
 
 
(a) X= AB’C’ + A’BC’ + A’B’C + ABC 
 
 
(b) X= A’BC + AB’C + ABC’ + A’B’C’
 
 
(c) X= AB+BC+AC
 
 
(d) X= A’B’+B’C’+A’C’
 
 
Answer: A
 
 
 
 
 

w.     
x. The logic function implemented by the circuit
  
 
 
shown in the following figure is (ground implies a
 
 
logic `0’)
 
 
 
 
 

 
 
 
 
 
(a) F = AND (P, Q) 
 
 
(b) F = OR (P, Q)
 
 
(c) F = XNOR (P, Q) 
 
 
(d) F = XOR (P, Q)
  
 
 
 
 

x.     
xi. For the circuit shown in the following figure, I0 to I3

 
 
 
are the inputs to the 4:1 multiplexer R(MSB)
 
 
and S are control bits. The output Z can be represented
 
 
by
 
 
 
 
 

 
 
 
 
 
 (a) PQ + PQ’S +Q’R’S’
 
 
(b) PQ’ + PQR’ +P’Q’S’
 
 
(c) PQ’R’ +P’QR +PQRS +Q’R’S’
 
 
(d) PQR’ +PQRS’ +PQ’R’S +Q’R’S’
 
 
Answer- A
 
 

1.     
2. An 8-to-1 multiplexer is used to generate the CARRY output of a
full-adder. If the three control inputs are used as the two input
bits to be added and the CARRY IN bit; how many numbers of
data bits would need to be tied to logic `1’ status?

 
 
 
(a) 2
 
 
(b) 3
 
 
(c)4
 
 
(d) 5
 
 
Answer- C
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

1.     
2.
    

a.         
b.
        

1.             
2.
            

5.                 

 6. Decoder based questions

7.             

            

3.         

        

c.         
d. Design 3:6 Decoder using 8x1 mux

e.         
f. F = minterms(1,2,3,5,10,12,15) using 2:4 decoder with 

g.     

    

 
 
 
1. Active low (OR) inverting (AND gate) 
 
 
2. Active high (OR) Non-inverting (OR gate) 
 
 
                        c.   A 5 × 32 Decoder can be constructed by using
 
 
S1: four 3 × 8 Decoders and one 2 × 4 Decoder
 
 
S2: five 2 × 4 Decoders
 
 
S3: eight 2 × 4 Decoders, one 3 × 8 Decoder
 
 
S4: four 3 × 8 Decoders
 
 
Consider all the decoders are having enable input.
 
 
(A) S1, is true alone
 
 
 (B) S1, S3, S4 are true
 
 
(C) S2, S3 are true
 
 
 (D) S1, S3 are true
 
 
Answer- D
 
 
d. To construct a 5 to 32 line decoder, how many number of
3 to 8 line decoders and 2 to 4 line decoders are required
respectively without using any extra hardware?
 
 
(A) 3, 2
 
 
  (B) 4, 1
 
 
(C) 2, 4
 
 
                                (D) 2, 2
 
 
Answer- B
 
 

a.     
b. f (x2, x1, x0) = ?

 
 
 
 
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
(A) p (1, 2, 4, 5, 7) 
 
 
(B) ∑(1, 2, 4, 5, 7)
 
 
(C) ∑(0, 3, 6) 
 
 
(D) p (0, 2, 3, 6)
 
 
Ans: C
 
 

b.     
c. For a 4 × 16 decoder circuit, the outputs of decoder (y0, y1, y4 ,
y5 , y10 ,y11,  y14, y15) are connected to 8-input NOR gate. Find
the expression of NOR gate output.

 
 
 
(A) A ⊕ D (B) A Ꙩ D
 
 
(C) A Ꙩ C (D) A ⊕ C
 
 
Answer: D
 
 

c.     
d. Full subtractor can be implemented by using

 
 
 
(A) 3 to 8 line decoder only
 
 
(B) 3 to 8 line decoder and one OR gate
 
 
(C) 3 to 8 line decoder and two OR gates
 
 
(D) None
 
 
Ans. C
 
 

d.     
e.  

 
 
 
 
 
 
6.      Boolean expression minimization
 
 
      a.K Maps 
 
 
i. Simplify F(A, B, C, D) = S ( 0, 1, 4, 5, 7, 8, 9, 12, 13) 
 
 
ii. Write the function F3 in the given circuit.
 
 
a. F = sum if minterms(0,1,3,5) 
 
 
b. F1 = (2,3,6,7) 
 
 
c. F2 = (0,1,5) 
 
 
d. Circuit 
 
 
      i. Fl. f2 input to NAND => n1 is output 
 
 
Ii. F3 is input to inverter  => n2 is output 
 
 
iii.n1 and n2 are input to AND gate => F is output 
 
 

1.     
2.
    

a.         
b. Minimal cost function F=M(3,4,5,7,9,13,14,15) using 4x1
Mux 
c.         
d.  Implement a minimal cost circuit for F = M(0,1,3,7) in SOP
form. Is the circuit hazard free? If not how to rectify it to
obtain a hazard free ckt? 

e.         
f. . The number of min terms for the function
        

i.             
ii. F(a, b, c, d, e) = b + cd is
            

1.                 

2. (A) 24 

3.                 

4. (B) 20

5.                 

6. (C) 32 

7.                 

8. (D) 16
 9.                 
10. Answer- B

11.             

            

iii.             

iv. The minimum SOP form of
            

1.                 

2. f (P, Q, R) = (P’ + R + Q’)(P’ + R’+ Q)(P’ + R + Q)
                

1.                     

2.
                    

i.                         

ii. (A) P’ + QR 

iii.                         

iv. (B) P’ + Q
 v.                         
vi. (C) P’Q’ + R

vii.                         

viii.  (D) P

ix.                         

x. Answer- A

xi.                     

                    

3.                 

                

3.             

            

v.         
         

g.         
h.  The max term expression of a four variable even function is
        

1.             
2.
            

1.                 

2.
                

a.                     

b. (A) π M (0, 2, 4, 6, 8, 10, 12, 14)

c.                     

d. (B) π M(1, 3, 5, 7, 9, 11, 13, 15)

e.                     

f. (C) π M (0, 3, 5, 6, 9, 10, 12, 15)

g.                     

h. (D) π M (1, 2, 4, 7, 8, 11, 13, 14)
 i.                     
j. Answer- D

k.                 

                

3.             

            

3.         

        

i.         
j.  Ifthe Boolean function f(a, b, c, d) = a + b + c + d has to be
implemented with only 2 input NAND gates, then how
many NAND gates are required?
        

1.             
2.
            
 1.                 
2.
                

a.                     

b. (A) 6 

c.                     

d. (B) 7

e.                     

f. (C) 8

g.                 

                

3.             

            

3.         

        
 k.     

    

 
 
 
                               Iv.         (D) 9
 
 

1.     
2.
    

e.         
f.
        

1.             
2.
            

1.                 

2.
                

d.                     

e. Answer-D
 f.                 

                

3.             

            

3.         

        

g.         
h.  The number of distinct Boolean expressions of four
variables is

i.     

    

 
 
 
(a) 16 
 
 
(b) 256
 
 
(c) 1024 
 
 
(d) 65536
 
 
Answer-  D 
 
 

1.     
2.
    

g.         
h. The function f A ÅB ÅC ÅD is represented as

i.     

    

 
 
 
(A) f(A, B, C, D)
 
 
= Σ(2, 6, 10, 11, 12, 13, 14)
 
 
(B) f(A, B, C, D)
 
 
= Σ(3, 5, 7, 10, 11, 12, 13, 14)
 
 
 (C) f(A, B, C, D)
 
 
= Σ(1, 2, 6, 8, 10, 12, 13, 14)
 
 
(D) f(A, B, C, D)
 
 
= Σ(1, 2, 4, 7, 8, 11, 13, 14)
 
 
 
 
 
Answer- D
 
 
 
 
 

1.     
2.
    

h.         
i. Boolean expression for shaded portion is

j.     

    

 
 
 
  
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
(A) ABC ABC )’
 
 
(B) AB BC CA
 
 
(C) ABC’ + AB’C + A’BC 
 
 
(D) ABC’ + A’BC’ + (ABC)’
 
 
Ans: C
 
 
 
 
 

1.     
2.
    

i.         
ii. The Boolean function Y = AB + CD is to be realized

iii.     

    

 
 
 
using only 2-input NAND gates. The minimum number
 
 
of gates required is:
 
 
(A) 2 (B) 3 (C) 4 (D) 5 
 
 
Ans: B
 
 
 
 
 

1.     
2.
    

j.         
k.  For an n-variable Boolean function, the maximum 

l.     

    

 
 
 
number of prime implicants is 
 
 
(A) 2(n – 1) (B) n/2 (C) 2n (D) 2(n-1)
 
 
Ans. D
 
 

1.     
2.
    

k.         
 l.  Find the number of product terms in the minimized sum-
of-product expression obtained through the following K-
map (where ‘d’ denotes don’t care states)

m.     

    

 
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
(A) 2 (B) 3 (C) 4 (D) 5
 
 
Ans. A
 
 

1.     
2.
    

l.         

xx. A relay is to operate with conditions that it should be ON

when the input combinations are 0000, 0010, 0101, and
0111. The states 1000, 1001, and 1010 do not

yy.     

    

 
 
 
occur. For rest of the status, relay should be OFF.
The
 
 
minimized Boolean expression notifying the
relationship
 
 
is
 
 
A) BC + ACD
 
 
(B) B’D’ + A’BD
 
 
(C) BD + AC
 
 
(D) AB + CD
 
 
Answer: B
 
 

1.     
2.
    

m.         

lllllllllllllllllllllllllllllllllllllll. The function F is

mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm.     

    

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
(A) a’ + b’ + c 
 
 
(B) (abc)’
 
 
(C) (a’ + b’)c’ 
 
 
(D) (a + b)’ + c’
 
 
Answer: B
 
 

1.     
2.
    

n.         
o.
        

 
        

        
        In the circuit the function F(a, b) in POS form

p.     
     

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
(A) (a + b)(a’ + b’) 
 
 
(B) (a’ + b)(a + b’)
 
 
(C) (a + b’)(a’ + b’)
 
 
                                (D) (a + b)(a’ + b)
 
 
Answer: B
 
 

     

    
 o         
o A combinational circuit has 3 inputs x, y, z and three  

o     

    

 
 
 
outputs A, B, C. When the binary input is 4, 5, 6 and
7,
 
 
the binary output is 2 less than the binary input.
When
 
 
the binary input is 0, 1, 2 and 3, the output is 4 more
 
 
than the binary input the Boolean expression for
output
 
 
A and C respectively are?
 
 
(A) x’ y, z 
 
 
(B) x + y’, z’
 
 
(C) x, z 
 
 
(D) x’ + y, z
 
 

1.     
2.
    

p.         
q. The Boolean function f(a, b, c) = a’ b + b’ c + ac’ has to be

r.     

    

 
 
 
implemented by the following 2 × 1 multiplexer then
 
 
the gate 1 and gate 2 are respectively?
 
 
 
 
 
 
 
 
 
 
(A) OR, NAND 
 
 
(B) AND, OR
 
 
(C) NOR, AND
 
 
    (D) NAND, OR
 
 
Answer: A
 
 

1.     
2.
    
 q.         
r. If the Boolean function f(a, b, c, d) = a + b + c + d has

s.     

    

 
 
 
to be implemented with only 2 input NAND gates,
then       
 
 
how many NAND gates are required? 
 
 
(A) 6 (B) 7
 
 
(C) 8 (D) 9
 
 
Answer- D
 
 

1.     
2.
    

r.         
s. The minimized POS expression of the function
 t.     

    

 
 
 
f(A, B, C, D) = AB + AC’ + C + AD + A B’C + ABC
 
 
 
 
 
(A) A + C’
 
 
                    (B) A’ + B’
 
 
(C) AC 
 
 
(D) A + C
 
 
Answer-D
 
 

1.     
2.
    

s.         
 t.  A Boolean function f of two variables x and y is defined as
follows:

u.     

    

 
 
 
f(0, 0) = f(0, 1) = f(1, 1) = 1; f(1, 0) = 0  Assuming
that the complements of x and y are not available,
a minimum cost solution for realizing f using only
two-input NOR gates and two-input OR gates (each
having unit cost) would have a total cost of
 
 
(a) 1 unit 
 
 
(b) 4 unit
 
 
(c) 3 unit 
 
 
(d) 2 unit
 
 
Answer- D
 
 

1.     
2.
    
 t.         
u.  

v.     

    

 
 
 
 
 
 
 
 
 
7. Combinational circuits
 
 

1.     
2.
    

1.         
2.
        

1.             
2.
            
1.                 
2. Binary encoding. one hot encoding

3.                 

4. Design an HA using minimum number of NAND
gates 

5.                 

6. Design a half substractor using half adder  

7.                 

8. Design 2 bit comparator using 1-bit 

9.                 

10. Design 4 bit add-subtractor circuit 

11.                 

12. Compare two 8-bit numbers without using
comparator

13.                 

14. Consider the given circuit
 15.             

            

3.         

        

3.     

    

 
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
In this circuit, the race around condition
 
 
(A) does not occur
 
 
(B) occurs when clk = 0
 
 
(C) occurs when clk = 0, A = 1 and X = Y = 1
 
 
(D) occurs when clk = 1, A = 1
 
 
Answer: D
 
 
 
 
 

1.     
2.
    
 1.         
2.
        

1.             
2.
            

8.                 

9. The output Y of a two-bit comparator is logic 1
whenever the two-bit input A is greater than the
two-bit input B. The number of combinations
for  which the output is logic 1, is

10.             

            

3.         

        

3.     

    
  
 
 
(a) 4 (b) 6 (c) 8 (d) 10
 
 
Answer- B
 
 
 
 
 

1.     
2.
    

1.         
2.
        

1.             
2.
            

9.                 

10. The 10-input bits to a 10-line decimal to four-
line  BCD priority encoder corresponding to 0, 1,
2, 3,4, 5, 6, 7, 8 and 9, respectively, are 1, 0, 0, 0,
1, 1,0, 1, 0 and 0. What will be the
corresponding BCD output if all inputs and
outputs are active HIGH?
 11.             

            

3.         

        

3.     

    

 
 
 
The encoder has priority for higher order bits.
 
 
(a) 0111
 
 
 (b) 1000
 
 
(c) 1001 
 
 
(d) 0110
 
 
Answer- A
 
 
  
 
 

1.     
2.
    

1.         
2.
        

1.             
2.
            

10.                 

11. A four-bit adder-subtractor can be constructed
from four full-adders and

12.             

            

3.         

        
 3.     

    

 
 
 
(a) four two-input OR gates
 
 
(b) two four-input OR gates
 
 
(c) two four-input Exclusive-OR gates
 
 
(d) four two-input Exclusive-OR gates
 
 
Answer- D
 
 
 
 
 

1.     
2.
    

1.         
2.
        

1.             
2.
            
 11.                 
12.  Given that IC 7483 is four-bit parallel adder chip;
how would you construct a 16-bit parallel adder
circuit?

13.             

            

3.         

        

3.     

    

 
 
 
(a) By a cascaded arrangement of four 7483’s
 
 
(b) By a cascaded arrangement of 16 7483’s
 
 
(c) 16-bit adder cannot be constructed from 7483’s
 
 
(d) None of these
 
 
Answer- A
 
 

1.     
2.
    

1.         
2.
        

1.             
2.
            

12.                 

13. The output Y in the circuit shown in the
following

14.             

            

3.         

        
 3.     

    

 
 
 
figure is always “1” when
 
 
 
 
 
 
 
 

 
 
 
 
 
(a) two or more of the inputs P, Q, R are “0”
 
 
(b) two or more of the inputs P, Q, R are “1”
 
 
 (c) any odd number of the inputs P, Q, R is “0”
 
 
(d) any odd number of the inputs P, Q, R is “1”
 
 
 
 
 
Answer- B
 
 
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