ELX218 Semester 1 Revision

September 2018 Paper

Dr. I. Fletcher
 Diode Model
 nkT
qV

Forward Biased : I  I s  e  1
 

I
1/Rd Rd

V Vd
Vd

where Vd is the diodes cut-in voltage

Rd is the diodes forward resistance
 Zener Diode Model
Designed to operate in reverse bias
using the steeper reverse breakdown
characteristic :

VZ
V RZ
1/RZ VZ
I

where VZ is the Zener Voltage

RZ is the Zener Resistance
 Question 1a :
The circuit in figure Q1a shows a Series
regulator structure. Explain how the output
voltage is regulated if an increase in Io
occurs. I o

Vin Vout
R
VZ

An increase in Io :
increases Vout and hence VZ
increases shunt current
Reduces Ib and hence Io
 Using a zener diode
Question 1b : model and the following
transistor small signal h-parameter model
sketch the equivalent circuit of the circuit.

R
Io
Ib
B C
Vin Vout Vin
R
RZ hie hfeIb
VZ
E E
Io
VZ Vout

Ground Rail
 Question 1c : Using the above series
regulator equivalent circuit show that :
 RZ   R   1  R.RZ 
Vout  Vin    VZ    I 0    hie 
 h  R  R
 R  RZ   R  RZ   fe  Z 

From KCL at the output :

R
Ib
I o  I b  h fe I b  h fe I b
V B C
Vin hie
Consider the voltage V :
RZ hfeIb
E E  I0 
V  Vout  hie I b  Vout  hie  
Io h 
VZ Vout  fe 
From KCL at the V :
Ground Rail
Vin  V I 0 V  VZ
I R  Ib  I Z  
R h fe RZ
Question 1c :  RZ 
Vout  Vin
 R   1  R.RZ
 VZ 
 R  RZ 
  I0  
 
 R  RZ   hfe  R  RZ

 hie 


Manipulating equation 3 to gather common terms :

Vin VZ I 0 1 1   R  RZ 
  
V  
  V  
R RZ h fe  R RZ   R.RZ 

Replacing V using equation 2 :

Vin VZ I 0  hie I 0  R  RZ 
   Vout   
R RZ h fe  
h fe  R.RZ 

Re-arrange to isolate Vout :

 RZ   R   1  R.RZ 
Vout  Vin  VZ 
 R  RZ 
  I0 




 R  RZ   hfe  R  RZ
 hie 
 
 The input regulation factor SV
Question 1d : is defined as Vout/Vin .
Derive its value from the equation shown and
explain what its ‘ideal’ value is and why ?

 RZ   R   1  R.RZ 
Vout  Vin  VZ    I0    hie 
 
 R  RZ   R  RZ   hfe  R  RZ 

Hence : Vout R
SV   Z
Vin R  RZ
As the point of a regulator is to limit the variation
in the output voltage then ideally :
Vout R
SV   Z 0 R  RZ
Vin R  RZ
 Figure Q1b shows a circuit
Question 1e) : that is commonly connected
to the output of the circuit in figure Q1a.
Describe why it is needed and how it achieves
this ?
RX Io
To emitter of the
series transistor

To base of the
series transistor

• Shunt current is still controlled by the series transistor

• If IoRX > 0.7V then the above transistor turns ‘ON’
• Which drains the series transistor’s base current
Turning it ‘OFF’ to protect it from over-currents
 The Ideal Amplifier
• Infinite Gain +VS

• Infinite Input Impedance V+ +

Vo
• Zero Output Impedance V- _

• Infinite Bandwidth -VS

V0 = A(V+ - V-)
An open loop op-amp has nearly infinite gain and
so mostly operates saturated at ‘supply’ rail levels.
So how do we control its Gain ?
Negative Feedback !
Operational Amplifier Analysis
Ideal Op-Amp :
• Virtual Earth as A → ∞ V+ = V-
• Zero Input Current as Zin → ∞ I+ = I- = 0
• Form component Equations
• Derive required expression
Non-Ideal Op-Amp :
• KCL equations at inputs
• Derive V+ and V- expressions
• Place in V0 = A(V+ - V-)
• Derive required expression
 The Differential Amplifier
R2

V1 R _
Vo
V2 R +
R

0V

R2
Where V0  V2  V1 
R1

Ratio’ed Gain Differential Input

Gains 0→∞ +ve or –ve Gain
 Filter Analysis
Z2 Vin
+
_
Vout
Vin Z _
Z
Vout
+
Z
0V 0V
Inverting Amplifier Non-Inverting Amplifier
Vout Z2 Vout Z2
  1
Vin Z1 Vin Z1

Passive Impedances in s-plane :

• Resistor Z R s   R
• Inductor Z L s   sL
• Capacitor Z C s   1 / sC
Question 2a :
What operational amplifier properties allow the
following rules to be used when analyzing ‘ideal’
operational amplifiers :

i) Virtual Earth ( V+ = V- )
ii) Zero input Current ( I+ = I- = 0 )
Infinite Gain requires the
Virtual Earth differential input to be zero
to produce a finite output !

Zero Input Infinite Input Impedance

Current ensures zero input current !
 Show that the voltage gain
Question 2b)i) of the inverting amplifier
R2 is given by :
 
R1 _
 
Vo R2  1 
Vin
+   
Vo Vi R1  1  R2  
 
 1  A 1  R  
  1 
0V

For a non-ideal op-amp,  Vo  A V   V   , assuming no

current into the op-amp then :

V 0 Vo   AV 

Vi V  V  Vo  R2   R1 
For V :- I 


V  
Vi   V0
R1 R2  R1  R2   R1  R2 
Placing in V – and 
Vo 1 
AR1    AR2 
   Vi
gathering terms :  R1  R2   R1  R2 
 Show that the voltage gain
Question 2b)i) of the inverting amplifier
R2 is given by :
 
R1 _
 
Vo R2  1 
Vin
+   
Vo Vi R1  1  R2  
 
 1  A 1  R  
  1 
0V
  AR2    A  
     
Forming the Vo  R1  R2  Vo R2   R1  R2  
   
Gain ratio: Vi  AR1  Vi R1   1 A 
1  
 R1  R2    R  R  R  
 1 1 2 

 
 
Multiply top & Vo R  1 
R R
bottom by A :1 2
Vi
 2
R1 

1  R1  R2  


  1 

 A  R1  
 Question 2b)ii)
What is the ideal value of A and what would be
the inverting amplifiers voltage gain be with it ?

Ideally A
   
   
Vo R2  1  R2  1 
Hence :       0
Vi R1  1  R2   R1
 1  R2  
1  1    1  1   
 
 A  R1      R1  

Vo R2  1  R2
Therefore :    
Vi R1  1  0  R1
Question 2c :
R

Derive the transfer R

_
function of the op-amp +
Vin
shown (assuming an Vo
ideal amplifier) 0V

 1 
R2  
1  sC   R2
Z1  R1 and Z2  R2 
sC 1 sCR2  1
R2 
sC
 R2 
 
VO Z2  sCR2  1  R2  1 
Hence :      
Vin Z1 R1 R1  sCR2  1 
 The amplifier in figure Q2a
Question 2d : is seen to produce a small
output voltage when its input is grounded. Provide
a possible reason for this. Explain why that
problem occurs and how it may be overcome ?

Most likely either :

Input offset problem , or

Mismatched transistors/resistors
in the input circuitry

Null offset adjustment required !

 A.C. Transistor Model
Ib hie Ic
B C
Vbe hreVce + hfeib hoe Vce
E E

Common emitter model :

KVL at input : V be  h ie I b  h re V ce
KCL at output : I c  h fe I b  h oe V ce

Note : Commonly hre  0 and hoe  0

A.C. Transistor Circuit Analysis
1. Re-draw your circuit noting that for ac analysis:
• capacitors are s/c
• dc voltage rails are s/c
Ib hie
B C
2. Sketch transistor
hreVce + hfeib hoe Vce
equivalent circuit
E E
3. Establish the rail levels on your sketch
4. Establish the resistors between transistor
terminals/rail levels
5. Analyse the circuit ( in terms of Ib )
Note ! Establishing Rail Levels
Normally this comes down to two alternatives :
Ib hie
B C
No Emitter Resistance is
Present (either directly hreVce + hfeib hoe Vce
or via Capacitor S/C) E E
Rail Level

Ib hie
B C
An Emitter Resistance is
Present hreVce + hfeib hoe Vce

E E

RE

Rail Level
Question 3a)i) : VDD
R1
Cin
For the Common Co
Collector Amplifier Vin R2
RE RL Vout
shown : 0V

What form of biasing is used ?

Biasing sets up the transistor’s base current !

Potential Divider Bias Shown

 VDD
Question 3a)ii) : Cin
R1
Co
For the Common
Collector Amplifier Vin R2
RE RL Vout

shown : 0V

Given that  = 150 and IC = 30mA calculate

the transistor’s base and emitter currents.

2 Equations : Ic = .Ib and Ie = Ib + Ic

Solve the 2 unknowns
Ib = Ic / = (3010-3)/150 = 0.2mA

Ie = Ib + Ic = 0.2 + 30 = 30.2mA
 Evaluate the resistor
Question 3a)iii) : values R1, R2 and RE
required to bias the amplifier to provide the
maximum output voltage swing if VDD = 20V
and IR1 = 10Ib.
Ic V
20V
DD
Since 10Ib
Vbe=0.7VC
R1 Capacitors O/C for dc
in Ib
10.7V Co Identify voltages
10V
R2
Vin RE RL Vout Identify currents
KCL 9Ib Ie
0V
0V 0V

as Ib = 0.2mA, Ic = 30mA and Ie = 30.2mA then :

20-10.7 10.7-0 10-0

R1 = = 4.65k R2 = = 5.94k RE = = 331
10(0.2mA) 9(0.2mA) 30.2mA
Question 3b)i) :
Sketch the high frequency equivalent circuit of
the amplifier. VDD
R1
Cin
• s/c capacitors Co

• s/c dc voltage rails Vin R2

RE RL Vout
0V
• Sketch equivalent Circuit :
B Ib C
• Find rail level
• Establish R’s V
R
in
1 R2 hie hfeib

• Identify V/I’s E
RE RL
E
Vout

Rail
 Show that its voltage
Question 3b)ii) : gain is given by :
RL 1  h fe 
*
Vout where RL* is the parallel
AV  
Vin hie  RL* 1  h fe  combination of RL and RE

B Ib C

R1 R2 hie hfeib
Vin
E E
 RLE* RL Vout

Rail

Vout = (Ib + hfe Ib )RL* = (1 + hfe )IbRL*

Vin = hieIb + Vout = ( hie + (1 + hfe )RL* ) Ib

 Show that its voltage
Question 3b)ii) : gain is given by :
RL 1  h fe 
*
Vout where RL* is the parallel
AV  
Vin hie  RL* 1  h fe  combination of RL and RE

Vout (1 + hfe )IbRL*

Vin
=
( hie + (1 + hfe )RL* ) Ib 
 Transistors are known to be
Question 3c : temperature unstable as an
increase in temperature produces an increase in
output current. Identify the component in figure
Q3 that provides compensation for this and
explain how it does so. What other components
could be added to help with this ?
VDD An increase in IC :
R1 increases Ie
Cin
Co increases VRe
Vin R2 decreases Vbe
RE RL Vout
0V regulating Ic

Cooling required, i.e. heatsinks etc…

 For the values shown,
Question 4a) : sketch (with respect to Vo)
the waveforms of the op-amps input voltages V+
and V- and its output Vo .
R Positive feedback :
_  3k 
Vo  0.6Vo

Vo V  
+
R
 2k  3k 
C
2k Negative feedback :
5.6V
3k Zeners
RC Charging/D ischarging
0V
Vo
V+=0.6Vo
time
V-
 When considering Vo why
Question 4b)i) : does it tend towards the
voltage supply rail levels?

R
_
R Vo
+
C
2k
5.6V
3k Zeners

0V

Positive feedback drives the output into

saturation around ±VS
 When considering Vo which
Question 4b)ii) : circuit components influence
the actual magnitude of its output voltage and
what will be its value will be for the two output
conditions possible as shown ?
R
_
R Vo
+
C
2k
5.6V
3k Zeners

0V

Output Voltage : Vo  VZ  0.7   5.6  0.7   6.3V

 The Astable shown can be
Question 4c)i) : modified to create a
monostable multivibrator.
What is a monostable multivibrator ?

A monostable produces a pulse of fixed

duration when an input is detected

When an input is detected :

• a monostable leaves its rail level saturated
stable state
• after a circuit dependant fixed duration it
returns to its stable state
 The Astable shown can be
Question 4c)ii) : modified to create a
monostable multivibrator.
Explain the necessary modifications needed to
achieve this and sketch the resulting circuit
Negative going input
trigger pulse needed to VT
instantaneously pull V+
R
down to a value lower
than +0.7V _
Diode ensures that V-
R Vo
+
never reaches V+ and C
2k
hence remains in a 5.6V
3k Zeners
positive saturated
stable state
0V
 With the aid of a sketch
Question 4d) : illustrate the adaptations
necessary to the circuit
shown to allow the output waveforms mark/space
ratio to be changed.
This requires a different timing for each half cycle
RPOS

RNEG
R
_
R Vo
+
C
2k
5.6V
3k Zeners

0V
 Flip-Flops
One bit clock controlled storage devices based
upon a Bi-stable Latch.
The basic device is the SR Flip-Flop :
S R Qn+1 Qn+1
0 0 Qn Qn Memory
S Q
CLK
0 1 0 1 Reset
R Q 1 0 1 0 Set
1 1 ? ? Race !
The clock (CLK) can be either :
• Edge triggered : Falling (–ve) or Rising (+ve)
• Level triggered : High or Low
 Common Flip-Flops
J K Qn+1 Qn+1
JK Flip-Flop :
0 0 Qn Qn Memory
J Q 0 1 0 1 Reset
K Q 1 0 1 0 Set
1 1 Qn Qn Toggle
D-Type Flip-Flop : Qn+1 Qn+1
D
D Q 0 0 1 Reset
Q 1 1 0 Set
T-Type Flip-Flop : Qn+1 Qn+1
D
T Q 0 Qn Qn Memory
Q 1 Qn Qn Toggle
 Sequential Design
• Draw a truth Table which shows the sequence
required in terms of the mapping from present to
next required states
• A flip-flop is required for to represent each bit in
the ‘unique’ state codes
• Derive the flip-flop inputs required to map its
present bit to its next bit
• Use K-maps to design the required flip-flop inputs
Qn Qn+1 J K D T
0 0 0 - 0 0
0 1 1 - 1 1
1 0 - 0 0 1
1 1 - 1 1 0
 Show the truth table for
Question 5a) : aalong J-K flip-flop and use it,
with the circuit
shown, to confirm that the truth table of a
T-type flip-flop is :
T T Qn+1
J     Q
Clk
0 Qn
K
1 Qn

J K Qn+1 Qn+1 Circuit Shows T = J = K !

0 0 Qn Qn
T=J=K=0
0 1 0 1
1 0
1 1
1 0
Qn Qn
T=J=K=1 
 A T-type flip-flop has the
Question 5b)i) : input waveforms shown
below. Assuming Q=0 initially, sketch its output
waveform if the device is Negative edge
triggered.

Clk
1
0
• Identify –ve
T
1 clock edges
0
• Q=0 initially
• T=0 No change
1
Q
0
• T=1 Toggle
T=1 T=1 T=0
 Question 5b)ii) :
Why would we not operate a T-type flip-flop
using level triggering ?

Clk
1
0
• Consider a high
T
1 level trigger
0
• Q=0 initially
• T=0 No change
1
Q
0 ?
• T=1 Toggle
If the level is held high the output can change
continuously providing T = 1 !
(ok if T = 0 as No Change required)
 Use T-Type flip-flops to
Question 5c : design a synchronous octal
reset counter.
000 001 010 011 100 101 110 111

~ ~ ~
Q3Q2Q1 Q3Q2Q1 T3 T2 T1
0 0 0 0 0 1 0 0 1
T Qn+1
0 0 1 0 1 0 0 1 1
0
0 1 0 0 1 1 0 0 1
Qn
1
0 1 1 1 0 0 1 1 1
Qn
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
 Use T-Type flip-flops to
Question 5c : design a synchronous octal
reset counter.

~ ~ Q3Q2
Q3Q2Q1 Q3Q2Q1 T3 T2 T1 Q1 00 01 11 10
~
0 0 0 0 0 1 0 0 1 0 0 1 1 0
T3  Q2 .Q1
0 0 1 0 1 0 0 1 1 1
0 0 0 0
0 1 0 0 1 1 0 0 1 Q3Q2
0 1 1 1 0 0 1 1 1 Q1 00 01 11 10
1 0 0 1 0 1 0 0 1 0 0 0 0 0
T2  Q1
1 0 1 1 1 0 0 1 1
1
1 1 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1 Obviously : T1  1
Question 5d :
Describe how the reset counter designed above
could be used to form the basis of any 8 step
sequence design ?

The counter provides 8 sequential steps each

identified by their own unique ‘count’ code using
3 flip-flops

Simply use logic to derive the

desired outputs as a function of
these flip-flop output codes
 Rectification ( AC to DC )
Half-Wave : Full-Wave :
D4 D1
RL
Vin RL Vout Vin
D3 Vout D2

Diodes : ‘ON’ if VD ≥ 0.7v , ‘OFF’ if VD < 0.7v

Vout Vout
Time Time
Vin Vin

Thyristor’s : ‘ON’ if VG ≥ 0.7 + VC and VA > VC , ‘OFF’ if IT < 0

Vout Vout
Time Time
Vin Vin
VG VG1,3
0.7V 0.7V
VG2,4
Time Time
 SCR (Thyristor) Issues
The main issue is that the thyristor switches off by
itself but when IT ≤ 0.
Resistive Loads : I and V in phase so when V=0 as Diode

Inductive Loads : I and V not in phase so when I=0

 L  Vout
I lags V by :   tan 1   Time
 R  Vin

Average Voltage :
2 2 
1 1 V 2
VAV  
2 0
Vout d  
2 0
V sin  d  
2 1
sin  d

where the actual limits (1 , 2) refer to the angles when
the waveform is present (and not zero) in a period (0→2
 Figure Q6 shows the
Question 6a)i) : basic circuit for an SCR.
Assuming the load is purely resistive :
Sketch the load voltage
waveform you would expect L

to see if the thyristors

O
A
D

firing angle, , was 30o

Vout
0 Time
Vin
VG
0.7V
0 Time


 Figure Q6 shows the
Question 6a)ii) : basic circuit for an SCR.
Assuming the load is purely resistive :
For a secondary voltage of V
Vsint show that the average VAV  1  cos 
2
load voltage is described by :
1 2
Given that VAV   V sin  d where   t
2 0

Vin
Vout As the waveform only exists
0
Time between  and  then :

1 1 V -1
VAV  V sin.d  V cos    cos   cos 


2  2 2
V
VAV  1  cos 
2
 Figure Q6 shows the
Question 6a)iii) : basic circuit for an SCR.
Assuming the load is purely resistive :
If the ac secondary voltage was 10Vrms and
the resistive load is 20 what would be the
average load current ?
As rms voltage is given then (from Q6a)ii) above) :
2Vrms 2 10 
VAV  1  cos   1  cos30   4.20V
2 2

Since this is across the resistance then :

4.20
I Peak   0.21A ( 0.15A rms )
20
 If the load also contains
Question 6b)i) : inductance then the
thyristors conduction cycle will extend to ,
where  > 180o :
Sketch the corresponding load voltage and
current waveforms and explain why this occurs?
Vout

0 Time
 Vin


The thyristor switches ‘off’ when the current

through it falls to zero. But with inductance
then I lags V by anything from 0 to 90 0
 If the load also contains
Question 6b)ii) : inductance then the
thyristors conduction cycle will extend to ,
where  > 180o :
Evaluate an expression for its average load
voltage VAV
Vout
Vin Now the waveform exists
0
 Time from  to  hence :


1 V
VAV  V sin.d  V cos    cos   cos 
1 

2  2 2
V
VAV  cos  cos  
2
 If the load also contains
Question 6b)iii) : inductance then the
thyristors conduction cycle will extend to ,
where  > 180o :
How would placing a free-wheeling diode
across the load improve operation ?

L
O
A
D

It allows a conduction path for the dissipation

of the inductors energy allowing the thyristor to
switch off at 180 degrees (as the R only load).
Question 6c :
Estimate an approximate value for  for a load
of resistance R ohms and inductance L Henry’s.

For a Series R-L circuit then we found that :

I.Z  L 
I.XL
 where :   tan 
1

Iref  R 
I.R

The voltage switches off at approximately 

The current lags the voltage by 
A good estimate of  is +
( especially if ≤ 60o )
 Darlington Pair
Improved Current Gain :

Ie1 = Ib2
Hence   1 2
*

*
V  Vbe1  Vbe2  1.4V
Note: be
*
Vce  Vce1  Vbe2  1V
 Current Mirror
A current mirror may be thought of as an
adjustable current regulator (sink shown)
where the output current is designed to follow
the reference current :
With matched transistors :
IR I0
IX
Control   1   2 and VBE 1  VBE 2
I0 2I0 / I B1  I B2  I0 / 
T1 T2
I0  IC 2  IC1

0V I R  IO  I X
 Alternate Circuit Forms
Sink Source Conversion :
• Flip the Circuit to the opposite rail, GND VDD
• Change BJT Transistors, NPN PNP
• Align Emitter with Current Direction

BJT CMOS Conversion :

• Change NPN NMOS
• Change PNP PMOS