Optik - International Journal for Light and Electron Optics 251 (2022) 168409

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Optik
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An efficient structure for designing a nano-scale fault-tolerant 2:1

multiplexer based on quantum-dot cellular automata
Saeid Seyedi a, *, Nima Jafari Navimipour b, **
a
Department of Computer Engineering, Tabriz Branch, Islamic Azad University, Tabriz, Iran
b
Future Technology Research Center, National Yunlin University of Science and Technology, 123 University Road, Section 3, Douliou, Yunlin
64002, Taiwan

A R T I C L E I N F O A B S T R A C T

Keywords: Quantum-dot Cellular Automata (QCA) is a unique and appealing technique for developing and
Quantum-dot cellular automata implementing high-performance and low-power digital circuits at the nanometer scale. In this
Fault-tolerant technology, fault-tolerant circuits guarantee reliability circuits through cells redundancy.
Nano
Therefore, fault-tolerant and optimized architecture are very important in designing a wide range
Multiplexer
of QCA circuits. However, although there are some QCA structures for multiplexer designs in the
literature, QCA characteristics can be used to design a more optimized multiplexer rather than
blindly modeling traditional logic in QCA. As a result, we developed an alternate version of the
proposed approaches that leverage fault-tolerant design methodologies. In this article, a new
structure for a fault-tolerant 2:1 multiplexer in QCA technology is suggested. Cell redundancy on
the wire, NOT gates and majority gates are used. Simulating the suggested designs and demon­
strating their correctness was done with QCADesigner 2.0.3. When the additional cell or single
missing cell fault occurs in the QCA architecture, the suggested fault-tolerant multiplexer can
achieve 90% fault tolerance.

1. Introduction

New nano-scale computational architectures, such as Quantum-dot Cellular Automata (QCA), are developing due to rapid tech­
nological advancements. The confinement and mutual repulsion of electrons are the main foundations of QCA [1]. Because QCA can be
implemented at a high frequency, with low power consumption, and in a very compact size, it is a viable alternative to the present most
widely Complementary Metal Oxide Semiconductor (CMOS) technology, which uses a silicon-based paradigm [2]. Dissipating heat
from high-performance and high-density CMOS components is already a challenging task, and it will become more challenging in the
future. The advancement of CMOS is further jeopardized by the exponential increase in the cost of production facilities [3]. The
intrinsic physical restrictions that will be encountered as feature size reduction are more concerning. Transistor-based manufacturing
will be slowed by quantum mechanical phenomena, connection constraints, and circuit lithography challenges [4]. Therefore, the
main QCA technology goals are designing circuits with high device density, low power consumption, high clock frequency, and quick
operation circuits.
QCA-based technologies are expected to have high manufacturing time fault stages and operational time defect measures [5,6].

* Correspondence to: Young Researchers and Elite Club, Islamic Azad University, Urmia, Iran.
** Corresponding author.
E-mail addresses: Stu.SaeidSeyedi@iaut.ac.ir (S. Seyedi), JNNima@yuntech.edu.tw (N.J. Navimipour).

https://doi.org/10.1016/j.ijleo.2021.168409
Received 10 September 2020; Received in revised form 16 September 2021; Accepted 26 November 2021
Available online 27 November 2021
0030-4026/© 2021 Published by Elsevier GmbH.
S. Seyedi and N.J. Navimipour Optik 251 (2022) 168409

Because of their enormous complexity, they have a high defect rate and require excellent fault tolerance mechanisms [5]. For working
correctly, QCA cells must be placed in the correct order and at the right location. Apart from errors in the QCA execution step, the
fabrication method, which may be partially controlled, may result in fault-tolerance problems [7]. As a result, QCA-based fault-tol­
erance logic is gaining popularity in the field of electronic circuit design. Multiplexer-based circuits [8], such as data transmission logic
[8], FPGA [9], and memory circuits [10], are widely used in the field of digital electronics, according to the literature. However, the
efficacy of fault-tolerance design for multiplexer’s in QCA has yet to be studied. The proposed study investigates the design of a
fault-tolerance 2:1 multiplexer in QCA. As a result, a helpful design for executing a fault-tolerant 2:1 multiplexer based on cell
redundancy and a fault-tolerant majority gate is provided. In a nutshell, the following are the main contributions of this article:

• Using QCA and cost analysis, we propose a fault-tolerant 2:1 multiplexer with a coplanar structure.
• Examining the presented design in terms of cell counts, size, fault tolerance, and cost compared to other current designs.

The remainder of the paper is laid out: Section 2 includes a review of QCA basic logics and prior multiplexer architectures. Section 3
discusses the new fault-tolerant 2:1 multiplexer. Section 4 contains the simulation findings, and Section 5 provides the conclusion.

2. Background of QCA

A QCA cell has four quantum dots, two of which can be occupied by electrons (Fig. 1(a)). The electrons will be drawn to opposite
corners of the cell due to Coulombic repulsion. The arrangement of electrons within a cell represents the cell’s state. Similarly, by
forcing nearby cells to tunnel from one location to another, Coulombic contact between surrounding cells may be utilized to transmit
configurations to other cells by used 45-degree and 90-degree cells (Fig. 1(b)). The state can be transmitted in this manner along a line
of neighboring QCA cells, producing a wire. To execute logical processes, further structures can be constructed.
Because of its flexibility in constructing diverse designs, the majority gate is one of the main blocks of QCA circuits [11]. A
three-input majority gate has three input cells, one device cell, and one output cell, as shown in Fig. 2(a). Due to electron repulsion
between the three input cells, the device cell is polarized to the majority polarization. Also, Fig. 2(b) shows a QCA implementation of
an inverter. The input signal is supplied from the left side, split into two QCA wires, and then merged; the complement of the input
signal is then calculated at the merging point and transferred to the right side [12].
A four-phase clocking method has been devised to prevent the loss of coherence in QCA circuits. The cells in this system are
subjected to an electric field. Within a QCA cell, this field boosts or decreases the tunneling barriers between electron sites. This has the
impact of either blocking or enabling electrons to move around or influence nearby cells. Cells can be organized into zones, with the
same field impacting all cells in that zone. A zone goes through four stages. The four stages of the QCA clock are shown in Fig. 3:
Switch, Hold, Release, and Relax [15,16].
The flaws of the cell’s incorrect location, on the other hand, emerge inside the deposition level as the most widespread errors. In
QCA circuit architecture, the following defects are common [18]:

1. One of the cells (Fig. 4(a)) is missing

2. A cell division has occurred (Fig. 4(b))
3. Displacement of cells has occurred (Fig. 4(c))
4. Fig. 4(d) shows a rotation of the cell

2.1. Related works

Investigators have recently given multiplexer designs and schematizations for simple multiplexers and fault tolerance in multi­
plexer design. The following papers illustrate the analysis of these schematizations.
In QCA technology, Ahmadpour, et al. [19] presented a fault-tolerant ALU based on the multiplexer. In fact, the authors of this work
developed a 3-input majority gate with 10 rotating cells and a high output signal strength. As stated by the authors, the fault tolerance
of the suggested construct has been checked out in contrast to extra-cell deposition, cell omission, and cell displacement faults. The
simulation outcomes attained by QCADesigner 2.0.3 demonstrated that the suggested circuits operate proficiently.
Ahmad [20] suggested a 2n:1 Multiplexer (MUX) and 1:2n Demultiplexer (DeMUX) architectures. With the help of the proposed

Fig. 1. (a) QCA cells [13], (b) QCA ordinary wire by 90 and 45 degrees cells.

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S. Seyedi and N.J. Navimipour Optik 251 (2022) 168409

Fig. 2. Construct blocks of (a) majority gate and (b) inverter gate [14].

Fig. 3. Four-phases of the clock in QCA technology [17].

Fig. 4. The following are some instances of common QCA circuit manufacturing flaws: a) cell missing, b) an extra cell, c) cell displacement, and d)
cell rotation [18].

2n:1 multiplexer, a unique technique for executing spectacular digital logic gates was proposed in this work. This paper has devised a
new approach to implement efficient digital logic gates using the proposed 2n:1 multiplexer. To verify the functionality of the proposed
structures, some Boolean proofs were performed. Also, a detailed comparison, structural evaluation, and power analysis of the pro­
posed multiplexer with recently robust designs were analyzed. In addition, a novel concept of QCA based Multiplexing/Demultiplexing
is presented. The functioning of the recommended constructions was approved using QCADesigner 2.0.3.
Also, Ahmadpour and Mosleh [21] proposed a fault-tolerant QCA-based multiplexer. In this article, a unique fault-tolerant
three-input majority gate is suggested first, followed by a novel single-layer 2:1 multiplexer based on the proposed structure. All
forms of extra cell deposition, cell displacement, and cell omission errors have been evaluated against the suggested design. QCA
Designer 2.0.3 confirmed the simulation findings, revealing that it is 100, 84.98, and 100% tolerant to single-cell omission, double-cell
omission, and additional cell deposition, respectively. In addition, the suggested structure’s energy dissipation was estimated using the
QCAPro power estimator tool.
Xingjun, et al. [22] presented a QCA-based multiplexer. The research suggested a novel QCA-based Nano-scale multiplexer
schematization and its use in Nano communications. A helpful structure for implementing a 2–1 multiplexer based on the innovative
XOR gate was described in this article, which can also be utilized as a module to construct the 4–1 and 8–1 multiplexer. To test the
performance of the recommended designs, simulations using the QCADesigner program were run. The recommended designs have
stable and relevant structures in terms of size, cost, and complexity, according to the QCADesigner tool.
Jeon [23] suggested a nanotechnology-based QCA–multiplexer for quantum computing that uses a majority function-based NAND.
Researchers suggested a multiplexer based on three NAND gates in QCA. Morgan’s law was used to create new equations and mul­
tiplexers using just NAND logic. Not only was the suggested circuit developed and confirmed to minimize time and space complexity,
but it was also designed and verified to minimize energy loss. Finally, utilizing the suggested multiplexer, researchers created an

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arithmetic circuit capable of executing various operations. The suggested designs were simulated using the QCADesigner tool, version
2.0.3, and their efficiency in terms of the number of constituent cells and surface area was shown.
Finally, in QCA nano computing, Rashidi and Rezai [24] suggested a design of new multiplexer circuits. Using the majority gate and
inverter gate, a single layer 2–1 QCA multiplexer circuit is presented in this work. This 2–1 multiplexer circuit can create efficient 4–1
and 8–1 QCA multiplexer circuits. The QCADesigner tool was used to implement and analyse the designed circuits.

3. The proposed fault-tolerant 2:1 multiplexer

A multiplexer, sometimes known as a data selector, is an electrical device that chooses one of the numerous input signals and sends
it to a single output line. Instead of having one device per input signal, a multiplexer allows multiple input signals, such as an analog-to-
digital converter or a communications transmission channel. Multiplexers can also be utilized to implement multiple-variable Boolean
functions. A demultiplexer is a single-input, multiple-output switch, while an electronic multiplexer is a multiple-input, single-output
switch. A multiplexer is a creative circuit that has been used in ALU, RAM, decoders, and shift registers, among other computational
circuits. In addition, the majority gate is used in the majority of QCA circuits. One selection line, two inputs, and one output make up
the most basic multiplexer. However, in contrast to numerous frequent faults, the commonly used majority gate displayed in Fig. 2(a)
and has not so well fault-tolerant behavior. Nonetheless, a fault-tolerant majority gate is presented, and its use in circuit design may
improve the tolerance of defects. Fig. 5 depicts the fault-tolerant majority gate [25].
The boolean equation for a 2-to-1 multiplexer is: X and Y are the two inputs, S is the selection input, and OUT is the output:

OUT = (X ^ S) ˅ (Y ^ S) (1)

The number of selector pins in bigger multiplexers is equal to n, the number of inputs.
This multiplexer architecture sends input to the output based on the select (S) line value. If the select line value is ’0’ (S = 0), the
input (X) will be sent to the output (OUT). If the select line value is ’1’ (S = 1), (Y) will be sent to the output (OUT). Table 1 depicts the
logical link between the multiplexer trust table and the logical relationship. Fig. 6(a) depicts the block schematics of the suggested
multiplexers, and Fig. 6(b) depicts a new proposed design. The inputs are introduced from one side of the system and output from the
other, as shown in Fig. 6. The fault-tolerant majority blocks are the main components of the recommended design, which is given in
one layer.

4. Simulation tools, parameters, and results

QCADesigner 2.0.3 is used to model the proposed QCA fault-tolerant multiplexer design. This is a simulation tool for QCA circuits at
the cell level. Both of the QCADesigner’s simulation engines ("Bistable Approximation" and "Coherence Vector") were used for
simulation because of their high speed and accuracy. For a Coherence Vector, the following parameters are used [26–28]:

1. 18 nm cell height
2. 18 nm cell width
3. The operating temperature is equal to 1 K
4. 1.00e-015s relaxation time
5. 1.00e-016s time step
6. Total simulation time= 7.00e-011 s
7. Clock high= 9.80e-22J
8. Low clock= 3.80e-23J
9. The clock is set to 0 o’clock
10. The clock’s amplitude factor is 2.0000
11. Permittivity relative= 12.900

Fig. 5. The layout of fault-tolerant majority gate [25].

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S. Seyedi and N.J. Navimipour Optik 251 (2022) 168409

Table 1
The multiplexer truth table.
Input’s Output

X Y S OUT
Low Low Low Low
Low Low High Low
Low High Low Low
Low High High High
High Low Low High
High Low High Low
High High Low High
High High High High

Fig. 6. (a) The proposed schematic design used three majority gates and one inverter gate, and (b) The proposed fault-tolerant multiplexer design
used three majority gates and one inverter gate.

12. The impact radius is 80 nm

13. Layer separation= 11.5 nm

All of the parameters are set to their default settings in the QCADesigner.

4.1. Accuracy, cell defect and cost analysis

As shown in Fig. 6, the recommended fault-tolerant multiplexer architecture employed three majority gates and one inverter gate,
with one output and three inputs. The simulation results reveal that the fault-tolerant multiplexer design employed three majority
gates and one inverter gate, as illustrated in Fig. 7. Furthermore, the appropriate output was created after two clock phases. The
obtained results show that the function of the proposed QCA structure for fault-tolerant multiplexer design is excellent, and the desired
function is accessible in this circumstance. Also, all of the inputs have been used to construct fault-tolerant multiplexers, as well as the
genuine outputs created by circuits.
The recommended fault-tolerant multiplexer was tested against cell rotation, cell missing, cell displacement, and extra cell to
demonstrate the suggested structures’ excellent fault tolerance. To achieve design power, 10% of the cells must be examined by ac­
cident. As a result, the most stringent tolerance range has been established. Table 2 shows the simulation results for the recommended
fault-tolerant multiplexer architecture. This multiplexer design can tolerate 90% of faults in the cell missing and cell displacement
cases. The recommended fault-tolerant multiplexer has a greater fault-tolerant level than other current multiplexers. This suggested
fault-tolerant multiplexer outperforms entire multiplexers, as shown in the comparison. Finally, when compared to the total types of
misplacement faults, the fault-tolerant degree of the recommended fault-tolerant multiplexer is higher.
The cost value is calculated using the following equation, where the area is the design area in m2 and latency is the number of clock
cycles [36,37]:

Cost=Area×Latancy2 (2)

In terms of parameters such as area, cells, latency, and cost, Table 3 compares the proposed fault-tolerant architecture to the
preceding designs. Table 3 shows that the proposed fault-tolerant multiplexer outperforms previous techniques in terms of clock
cycles.

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Fig. 7. Simulation outcomes of the suggested fault-tolerant multiplexer design.

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Table 2
The comparative designs’ percentages of the fault-tolerant amount.
Designs Fault-tolerance

Cell missing (%) Extra cell (%) Cell displacement (%) Cell rotation (%)

Iqbal, et al. [29] 20% 15% 15% 20%

Sabbaghi-Nadooshan and Kianpour [30] 20% 20% 30% 40%
Sen, et al. [31] 10% 15% 10% 10%
Sen, et al. [32] 15% 20% 15% 20%
Rashidi, et al. [33] 20% 15% 20% 20%
Rashidi and Rezai [34] 15% 15% 10% 20%
Ahmadpour and Mosleh [21] 30% 40% 45% 50%
Xingjun, et al. [22] 25% 30% 20% 20%
Ahmadpour and Mosleh [35] 50% 40% 40% 45%
Ahmadpour, et al. [19] 55% 50% 60% 50%
Proposed design 90% 80% 90% 85%

Table 3
Comparisons among the suggested and modern designs.
Designs Area (µm2 ) Cells Latency Cost

Iqbal, et al.[29] 0.04 30 0.5 0.01

Sabbaghi-Nadooshan and Kianpour[30] 0.02 26 0.5 0.005
Sen, et al.[31] 0.01 23 0.5 0.0025
Sen, et al.[32] 0.02 23 0.5 0.005
Rashidi, et al.[33] 0.01 15 0.5 0.0025
Rashidi and Rezai[34] 0.02 17 0.5 0.005
Ahmadpour and Mosleh[21] 0.04 36 1 0.04
Xingjun, et al.[22] 0.03 22 0.75 0.016875
Ahmadpour and Mosleh[35] 0.06 61 1 0.06
Ahmadpour, et al.[19] 0.08 85 1 0.08
Proposed design 0.07 51 0.5 0.0175

5. Conclusion

This study built and simulated a novel hierarchical QCA-based fault-tolerant multiplexer using a fault-tolerance three-input ma­
jority circuit. QCADesigner version 2.0.3, a quick design and simulation tool for QCA, was used to verify the accuracy of the given
circuit. Simulation findings demonstrate that the proposed QCA fault-tolerant multiplexer scheme outperforms similar circuits in terms
of fault tolerance. This design is one of the multiplexer’s best fault-tolerant circuits in terms of cell number, space, and latency.
Compared to a normal multiplexer, the suggested architecture is significantly more resistant to single-faults such as cell missing, extra
cell, cell displacement, and cell rotation. The 2:1 QCA multiplexer is used to produce n:1 QCA multiplexers, making this circuit
appropriate for usage in more extensive circuits.

Declaration of Competing Interest

The authors declare that there is no conflict of interest.

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