A Major Project

Report On
A COMPACT QUANTUM COST-EFFICIENT DESIGN OF A
REVERSABLE BINARY COUNTER
Submitted in Partial fulfillment of the requirement for the award of the degree

of

BACHELOR OF TECHNOLOGY

In

ELECTRONICS AND COMMUNICATION ENGINEERING

Submitted By

P.VINEETH 19625A0417

K.MUKESH 18621A0430

P.ASHRITHA 17621A0434

Under the guidance of

Mr. CHANDRAMOULI JOSHI

(HOD OF ECE)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

AURORA’S ENGINEERING COLLEGE

(Affiliated to Jawaharlal Nehru Technological University, Hyderabad)

Abids , Hyderabad. 50000

(2019-2020)
 AURORA’S ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

(Affiliated to Jawaharlal Nehru Technological University, Hyderabad)

Abids, Hyderabad. 500001

CERTIFICATE
This is to certify that the major-project report titled “A COMPACT QUANTUM
COST-EFFICIENT DESIGN OF A REVERSABLE BINARY COUNTER” is
being submitted by P.VINEETH (19625A0417), K.MUKESH (18621A0430),
P.ASHRITHA (17621A0434) in partial fulfillment for the award of the degree of
Bachelor of Technology in Electronics and Communication Engineering to the
Jawaharlal Nehru Technological University is a record of bonafide work carried
out by us. The results embodied in this project report have not been submitted to
any other university for the award of any degree.

INTERNAL GUIDE HOD OF ECE

Mr. CHANDRAMOULI JOSHI Mr.CHANDRAMOULI JOSHI

EXTERNAL EXAMINER PRINCIPAL

Mr.K.CHANDRASEKHAR
 ACKNOWLEDGMENT

A major-project is the exposure for a student to the real world. A part from the knowledge we get
from the experience, a major-project also lays the foundation of team-work, integrity, hard-work
and dedication which are the pre-requisites for successfully completing and engineering project
in the future.

This entire project would not have been possible without the guidance of a few scholars. I take
this opportunity to thank all those I have extended their cooperation during the course of this
project.

We thank our Principal Mr.K.CHANDRASEKHAR, who has brought forward such an activity to
augment a student’s practical knowledge.

We want to express our deepest gratitude to Prof.Mr. Chandramouli Joshi HOD of

Electronics and Communication Engineering & for exposing us to this project work and for
his grand support.

It is great pleasure to acknowledge our profound sense of gratitude to our project guide Prof.Mr.
Chandramouli Joshi HOD of Electronics and Communication Engineering, for his valuable
guidance, comments, and suggestions towards the completion of this work successfully.

We would like to thank all the staff members of the department of electrical and electronic
engineering for their encouragement throughout the course of this project. I would like to thank
our parents and our friends for being supportive all the time, and I am very much obliged to
them.

PROJECT ACQUAINTANCE,

P.VINEETH 19625A0417

K.MUKESH 18621A0430

P.ASHRITHA 17621A0434
 CONTENTS

CHAPTER - 1……………………………………………………………….……..1
INTRODUCTION………………………………………………………………………………...1

CHAPTER - 2 ............................................................................................................ 3
LITERATURE SERVEY .................................................................................................... 3

CHAPTER - 3……………………………………………………………….……..6
PROJECT DISCRIPTION........................................................................................6

CHAPTER - 4……………………………………………………………….……..8
CONCEPT OF PROJECT.........................................................................................8
4.1 RELATED WORK............................................................................................11

CHAPTER - 5…………………………………………………………………….13
CONCEPT OF METHODOLOGY……………………………...………………………………13

CHAPTER - 6…………………………………………………………………....14
ALGORITHM AND DATA FLOW DIAGRAM…………………………………...…...14

6.1 PROPOSED ALGORITHEM...........................................................................14

6.2 PROPOSED CIRCUIT......................................................................................14

6.3 DATA FLOW DIAGRAM................................................................................16

CHAPTER – 7…………………………………………………………………...14
INTRODUTION TO VLSI…………………………………………………………....17

7.1 FPGA DESIGN FLOW.....................................................................................19

7.2 INTRODUCTION TO VERILOG.....................................................................28

7.3 HISTORY..........................................................................................................30

7.4 SOFTWARE DISCRIPTION............................................................................46

7.5 INTRODUCTION TO XILINX........................................................................52

CHAPTER - 8……………………………………………………………….…...59
SAMPLE CODING AND RESULT……………………………………………...……59

8.1 CODE OF MSH GATE ....................................................................................59

8.2 CODE OF HNG GATE.....................................................................................60

8.3 CODE OF LOOK UP TABLE..........................................................................61

8.4 SIMULATION RESULT..................................................................................62

8.5 WAVE FORM...................................................................................................63

8.6 GRAPHICAL REPRESENTATION……………………………………….…63

CHAPTER - 9……………………………………………………………………64
CONCLUSION…………………………………………………………………...…64

CHAPTER – 10…………………………………………………………………..65
REFERENCES………………………………………………………………………65
LIST OF FIGURES
 ABSTRACT

One of the important aspects of Very Large Scale Integration (VLSI) is the power
dissipation as the number of devices integrated on a single chip increases progressively. In order
to overcome the difficulties of high power consumption of a single chip, it is necessary to
introduce reversible logic. Reversible logic allows complete reproduction of the inputs from
outputs. As there is no bit or information loss, reversible logic leads to zero heat dissipation. The
potential applications of reversible logic include Quantum computing, DNA computing,
Nanotechnology, Op to electronics and many more. Counter circuit stores the number of times of
occurrence of a particular event based on the clock pulse. An efficient reversible binary up/down
counter has been proposed in this paper implementing an efficient algorithm. MSH gate has been
used as D-latch, HNG gate and TS3 gate has been used for incremental count. The proposed
counter circuit has 31.25% improvement in terms of quantum cost and delay, 58.82%
improvement in terms of ancillary input and 5.8% improvement in terms of garbage output
compared to existing best known circuits.

Keywords—Reversible gate, D-latch, full-adder, counter, quantum cost, garbage output, delay.
 CHAPTER – 1

INTRODUCTION

Regular computing devices use irreversible logic where input bits can not be recovered from
the output bits and thus, loss of bit results in heat dissipation. The heat loss equation can be
written as KTln2 where K = 1.38060 ∗ 10 − 23J/K (the Boltzmann’s constant) and T is the
absolute temperature in Kelvin . Reversible computation was first proposed by Bennett . The
construction of reversible logic gates includes equal number of inputs and outputs. Specifically,
there must be a one to one mapping between the input and output. The qualitative parameters
often associated with reversible logic are Quantum Cost(QC), Garbage Outputs (GO), Constant
Inputs (CI) and Delay (D). An optimized reversible binary counter has been proposed using D-
latch. An efficient algorithm has been proposed which is implemented for constructing the circuit.
MSH gate [3] has been used as D-latch. As incremental approach has been followed for count
purpose, one TS-3 gate and three HNG gates have been used. HNG gate has been used as full-
adder whereas TS-3 gate has been used as the topmost adder for reset purpose, as the last carry
bit is not stored. The count increases with every clock signal. The circuit is optimized in terms of
different quantum parameters. The main contributions of the proposed reversible counter are in
the following parameters:

• Efficient reversible counter circuit with minimum number of ancillary input and garbage output.

• Least number of reversible gates are required for the proposed counter circuit.

• Minimum quantum cost and hardware complexity which ensures minimum number of
operations.

• Fastest reversible binary counter circuit till now in the literature as the circuit delay is minimum.

The paper is organized as follows:Section II introduces the basic terminologies needed to

understand the proposed methodology; Section III presents the best known works;Section IV
discusses the proposed method, the proposed circuit and the algorithm; Section V presents the
performance analysis and the paper is concluded in Section VI.

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Bidirectional counters are capable of counting in either the up direction or the down direction
through any given count sequence As well as counting “up” from zero and increasing or
incrementing to some preset value, it is sometimes necessary to count “down” from a
predetermined value to zero allowing us to produce an output that activates when the zero count
or some other pre-set value is reached.

This type of counter is normally referred to as a Down Counter, (CTD). In a binary or BCD
down counter, the count decreases by one for each external clock pulse from some preset value.
Special dual purpose IC’s such as the TTL 74LS193 or CMOS CD4510 are 4-bit binary Up or
Down counters which have an additional input pin to select either the up or down count mode.

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 CHAPTER - 2

LITERATURE SURVEY

In 2010, Lihui Nietal [3] presented a general method of constructing the reversible full adder.
A range of reversible full adders with only two reversible gates and two garbage outputs were
realized using this approach. This approach had progress in the gate count, garbage count and
quantum cost. In 2011, Nagapavanietal [4] presented a paper that proposed a design of a
reversible 4-bit shift registers which were compared with previous design. For this proposed
designs Reversible edge triggered D flip-flop such as SISO, SIPO, PISO and PIPO. These designs
have the applications to perform serial-to-parallel and parallel-to-serial conversions. In 2011,
Zhijin Guanetal [5] presented a design of Arithmetic Logic Unit based on reversible logic gates.
This paper presents that the minimum number of information bits were required for designing
reversible Arithmetic Logic Unit. This design has low power consumption and reduces the loss
by reusing information bits. In 2012, T. Naga Babuetal [6] presented reversible adder/subtractor
circuits using reversible logic gates like DKG and TSG gate. The proposed designs were better
than the previous designs in terms of hardware complexity, number of gates, garbage outputs and
constant inputs. In 2012, Xueyun Cheng et.al [7] presented a simplification algorithm for
reversible logic networks of positive/ negative control gates. This algorithm can lessen the gate
count as well as number of control bits. This simplified algorithm required only 8.10 average
numbers of control bits and 11 gate counts. In 2013 Rakshith Saligram et.al [8] presented a design
of low logical cost adders using novel parity conserving Toffoli gate. In this design parity
preserving gate had itself been used to work as a Toffoli gate. This proposed design has a
slightest logical cost. This design has 22.22% enhancement for quantum cost. In 2013, Mr.
M.Saravanan et.al [9] presented a design of energy efficient code converters using reversible
logic gates. This paper describes the various code converters such as grey to binary, binary to
grey, BCD to excess-3 using reversible logic gates. These converters have low power
consumption and higher efficiency as compared with conventional logic circuits. In 2014,

Page 3
Avinash G.Keskar et.al [10] presented a design of eight bit novel reversible arithmetic and logic
unit. This design can be used to realize large reversible systems. A reversible implementation of
eight bit arithmetic and logic unit required less number of gates and garbage outputs. In 2014,
R.Jayashree et.al [11] proposed that flip flops such as D flip-flop, T flip-flop and JK flip-flop
were designed using various previous reversible gates and their truth table were verified by
simulation. These proposed designs were compared in terms of average power consumption,
garbage outputs and constant inputs. In 2014, Asima Jamal et.al [12] proposed a design of sixteen
bit binary sequential counter using Feynman and Fredkin gates. The Up/Down operation of this
design was controlled by the control input UP/DOWN. The control input should be 1 for UP
operation and the control input should be 0 for down operation. In 2014, Ankur Sarker et.al [13]
presented a design that performs addition/ subtraction operations using parity preserving and fault
tolerant reversible gates. This circuit not only reduced the number of logic gates but also reduced
the quantum cost and garbage outputs. The highest improvements of the presented design were
33.33% for garbage output, 26.66% for quantum cost and 50% for gate count. In 2015, Sayyad
khaja Moinuddin et.al [14] proposed 2:4 reversible decoder using two Feynman and two Fredkin
gates. The proposed reversible decoder can be used in active high as well as in active low mode
of operation which depends upon the select lines. The proposed design has low quantum cost and
this design can be extended to 3:8 decoders. In 2015, Md. Samiur Rahman et.al [15] proposed an
Optimized Design of Full-Subtractor Using New SRG Reversible Logic Gates and VHDL
Simulation. In this proposed design SRG gate worked singly as a Full-subtractor circuit. This
proposed work can be used for designing nanotechnology based large reversible systems. In
2015, Avishek Bose et.al [16] presented a design of compact reversible online testable ripple
carry adder. The main property of this design is that one input line of the adder has no control on
the other input line. This design has improvement of 25% on number of gates, 42.30% on
quantum cost and 50% on number of constant inputs. In 2016, Umesh Kumar et.al [17] proposed
a paper that describes the performance evaluation of reversible logic gates. In this paper classical
gates and quantum gates are compared on the various parameters. It is analyzed that power
consumption, heat dissipation can be minimized using various reversible logic gates such as
Toffoli, Fredkin and Peres gate. In 2016, Deeptha A et.al [18] proposed a design of Reversible 8-
bit ALU by cascading 1-bit ALUs. Control unit and the adder unit were the major units of 1-bit

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ALUs. Control Output Gate (COG) and Haghparast Navi Gate (HNG) have been used for control
unit and adder unit respectively. The proposed design was compared with the previous design and
has lesser propagation delay. In 2016, MojtabaValinataj et.al [19] proposed a design of a new
low-cost gate with the quantum cost of 10. This new low-cost gate was used as a parity
preserving full adder with the minimum hardware complexity. Some new low-cost fault-tolerant
adders are carry skip, carry look-ahead and BCD adders which are highly proficient in terms of
quantum cost, total logical calculation and transistor count as compared to the previous designs In
2017, A.V.Ananthalakshmi et.al [20] proposed a design of Reversible floating-point square root
using modified non-restoring algorithm. Non-restoring method consumed less number of logical
resources and the remainder was not restored in each step. GST algorithm was used for this
floating-point square root which has reduced the area and power consumption. This design is
efficient in terms of number of reversible gates, constant inputs, garbage outputs and quantum
cost. In 2017, A.Kamaraj et.al [21] presented a design of Arithmetic Logic Unit using Novel
reversible gates and it was evaluated in Quantum Cellular Automata. This Arithmetic Logic Unit
can be used for low power applications. This design mitigates quantum cost, garbage outputs. It
has improvement of 50% on constant inputs, 58.3% on gate counts and 62% on number of cells.
In 2017, Dhoumendra Mandal et.al [22] presented a design of all optical one bit binary
comparator using reversible logic gates. In this design, reversible logic gates based on frequency
encoded data were used for designing one bit comparator. This comparator circuit can be used to
propose all optical Arithmetic Logic Unit.

Page 5
 CHAPTER – 3

PROJECT DISCRIPTION

The basis of the reversible binary counter of this invention is a plurality of binary elements each
having at least one input circuit and each capable of a first and a secodstable condition of
operation which may be produced alternately in response to the application thereto of a selected
polarity trigger signal.

While any binary element device may be employed for this purpose, for illustration only and
with no intention or inference that this invention be limited hereto, these binary elements may be
single input bistable multivibrator circuits which have two stable conditions of operation which
may be alternately produced through the application of successivesignals to the single input
circuit thereof and of the proper polarity to which the circuit is designed to be responsive.

These circuits are indicated by reference numerals 10, '11, 12 and 13.

The detailed circuitry of multivibrator has'herein been shown; however, since the details of the
remainder are identical, in the interest of drawing simplicity, they have herein been indicated in
block form.

Multivibrator circuits of this type are known as flip-flops, and as'such will hereinafter be
referred.

To provide the counting feature in any counting circuit comprising a chain of flip-flops, it is
necessary that the proper polarity trigger signals produced by either collector in each flip-lop of
the chain with every other reversal of condition of operation of any of the flip-flops in the chain
be applied to the next succeeding flip-flop to reverse its condition of operation, thereby indicating
the count of two For forward counting, the reversal of the condition of operation of any of the
flip-flops from the 1 condition to the 0 condition of operation should produce a signal of the
proper polarity to trigger the next succeeding flip-flop of the chain.

A reversible counter comprising a plurality of first means each having an input responsive.

A first potential in response to alternate pulses applied to the input, thereof and producing a
second potential in response to pulses intermediate said alternate pulses applied to the input
thereof, a pulse source for applying a series of pulses of said given polarity to the input of a first
one of said first means, and second means interposed between the output of each first means The

Page 6
reversible counter defined in claim 1, wherein said shunting means includes a first unidirectional
conducting device connected to said first input of said amplifier and a second unidirectional
conducting device connected to said second input of said amplifier, and switch The reversible
counter defined in claim 2, wherein said given polarity of said pulses is positive, wherein said
amplifier is a P-N-P transistor having an emitter, a base and a collector, wherein said first
differentiating circuit includes a first capacitance connected between the output of the preceding
first means and said emitter and a first resistance connected between said emitter and a point of
reference potential, wherein said second differentiating circuit includes a second capacitance
connected between the output of the preceding first mean and said base and a second resistance
connected between said base and said point of reference potential.

Page 7
 CHAPTER-4

CONCEPT OF PROJECT

One of the important aspects of Very Large Scale Integration (VLSI) is the power dissipation as
the number of devices integrated on a single chip increases progressively. In order to overcome
the difficulties of high power consumption of a single chip, it is necessary to introduce reversible
logic. Reversible logic allows complete reproduction of the inputs from outputs. As there is no bit
or information loss, reversible logic leads to zero heat dissipation. The potential applications of
reversible logic include Quantum computing, DNA computing, Nanotechnology, Optoelectronics
and many more. Counter circuit stores the number of times of occurrence of a particular event
based on the clock pulse. An efficient reversible binary up/down counter has been proposed in

Page 8
this paper implementing an efficient algorithm. MSH gate has been used as D-latch, HNG gate
and TS3 gate has been used for incremental count.

In this section, the basic defifinitions and properties required to present our proposed
methodologies are explained.

A. Ancillary Input

The ancillary input which is also known as Constant Input (CI) means setting the input fixed
beforehand. In a reversible circuit, the number of ancillary input should be minimal.

B. Garbage Output

The output which is neither used further in the circuit is called the Garbage Output (GO).

C. Quantum Cost

The Quantum Cost (QC) of a reversible circuit is defined as the number of elementary gates
needed to realize the circuit. The most used elementary gates are: NOT gate, Controlled

NOT (CNOT), Controlled-V gate and Controlled-V + gate.

D. Delay

Delay is the count of the maximum number of operations from input to output in a circuit. The
lower delay ensures a faster circuit.

E. Hardware Complexity

Hardware Complexity of a circuit is denoted by aα+bβ+cγ, where, α denotes the number of EX-
OR operations, β denotes operations, γ denotes NOT operations.

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F. HNG Gate (Haghparast-Navi Gate)

HNG gate is a 4×4 gate. Quantum cost of HNG gate is 6 and hardware complexity is 4α + 2β.
The gate is represented in Fig. 1

G. TS-3 Gate

It is a 3 × 3 gate and can act as a Full-Adder. Quantum cost of this gate is 2 and hardware
complexity is 2α. Fig. 2 represents the quantum realization of TS-3 gate.

H. MSH (Mubin-Sworna-Hasan) Gate

It is a 4×4 gate and can act as a D-latch [3]. Quantum cost of this gate is 6 and hardware
complexity is 3α + 2β + 1γ. Fig. 3 represents the block diagram of MSH gate.

Page 10
4.1 Related work

Counters are a vital component to digital circuits. Flip flops and latches are principal building
blocks of counters. Several categories of counters are compared in terms of quantum costs,
garbage outputs, constant inputs, delay and total logical calculation.

Joshi et al. proposed a 4 bit Asynchronous Up and Down Counter using reversible T-flip flop
which is constructed of two SGG and one Feynman gate [4].

This design can be utilized in reversible processor and reversible ALU. A design of Sequential
Counters using novel RM gate was proposed in [5].

Here, 4 × 4 RM gate along with Feynman gate forms a T-Flip flop which is used to design
asynchronous up and down Counter. A method of synchronous cyclic code counters by a
SMBD(Shefali Mamataj Biswajit Das) gate was introduced in [6].

The SMBD gate was used to design sequential circuit elements such as flip flops and latches.

A 4-bit synchronous gray code decade counter and 4-bit synchronous gray cyclic counter was
constructed using reversible T flip flop.

Again, the authors of paper [7] use different reversible decoders to construct combinational
circuits. Here, the concept of duplicating a single output is utilized by using Feynman Gate.

A 4 × 16 decoder was designed using Fredkin Gate, CNOT and Peres gates.

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Combinational circuits like full adder, subtractor, comparator, multiplexer are constructed using
these decoders.

Xuemei et al. proposed an innovative T-flip flop gate for the BCD ripple counter and controlled
Up/Down Synchronous Counter in [8]. A 4 × 4 quantum reversible T Flip-flop gate is proposed.

A reversible 4-Bit BCD ripple counter consists of T flip flops, JK Flip flops, Feynman Gate and
Tofoli gate.

The function of Flip flops is to trigger the outputs with negative pulse and gates are responsible
for copying the outputs.

A reversible 4- bit Synchronous Up/Down Counter is also proposed which contains T Flip flops,
Peres gate and Modified Toffoli Gate.

A nanometric reversible 4-bit binary counter with parallel load was implemented in [9].

The essential circuit components are D Flip flop, Peres gate, Fredkin gate and Feynman gate.

The quantum cost can be further minimized by applying generic algorithm.

This approach can be utilized to design complex quantum system.

Authors in paper [10] used Peres, Feynman, Sayem and Fredkin gate to construct the reversible
binary up/down counters.

They also construct a new reversible gate which is used for copying bit multiple times.

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 CHAPTER-5

CONCEPT OF METHODOLOGY

In this section the proposed reversible binary up/down counters are expounded with necessary
fifigures and algorithms. In the Fig. 4, the gates HNG and TS-3 work as full-adder. MSH gate [3]
has been used as the reversible D-latch.

R = A ⊕B ⊕C (1)

S = (A ⊕ B)C ⊕ AB ⊕ D (2)

HNG gate is used as a full-adder where 3 rd and 4 th output R and S has been used as sum and
carry, respectively. Equation 1 denotes the output function for sum and Equation 2 denotes the
output function for carry

R = A ⊕B ⊕C (3)

As for the last full-adder, TS-3 gate has been used because the carry of the last addition is not of
any further use. The 3 rd output R of TS-3 produces the required sum. Equation 3 denotes the
output function for producing sum by using TS-3 gate. The rest of the full-adders are working as
follows: 1 st and 2 nd output which is P and Q, respectively are garbage outputs. The 3 rd output
R (the sum) is fed to the reversible D-latch as data and the 4th output S (the carry) is propagated
to the the next full-adder above itself as input.

R = A0 C ⊕ AB (4)

S = A0 C ⊕ AB ⊕ D (5)

MSH gate has been used as the reversible d-latch [3] which is a 4 × 4 gate. It produces 2 garbage
outputs. The 3 rd output R is fed to itself and the function is denoted by Equation 4. The 4 th
output S is fed to the the full-adder beside it as the 1 st input A and the function is denoted by
Equation 5

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 CHAPTER - 6

ALGORITHMS AND DATA FLOW DIAGRAMS

6.1 A. Proposed Algorithm

Initially Q3Q2Q1Q0 are 0000. After iteration-1 Q3Q2Q1Q0 become 0001. After iteration-2
Q3Q2Q1Q0 become 0010 and so on. After iteration-15 Q3Q2Q1Q0 are 1111.

As the carry bit for the adder is not stored, the next iteration performs the reset operation and
Q3Q2Q1Q0 are again set to 0000 and the counter comes back to its initial stage.

The process is depicted in Algorithm 1.Algorithm 1: Proposed Algorithm for the 4-bit Reversible
Binary Counter.

Result: {|Q3 >, |Q2 >, |Q1 >, |Q0 >}

1 Set Q3Q2Q1Q0 → 0000;

2 Q0 := Q0 + 1;

3 Q1 := Q1 + Step 1’s carry;

4 Q2 := Q2 + Step 2’s carry;

5 Q3 := Q3 + Step 3’s carry;

6 Go to Step 2nd and repeat the process

6.2 B. Proposed Circuit

The Proposed circuit needs 3 full-adders with sum bit and carry bit and 1 full-adder with only
sum bit and thus, after 16 iterations the counter resets by itself. It also needs 4 D-latches where
the final output of the counter circuit is obtained.

1) NOT gate: NOT gate has been used to invert the Up Down input and then used as the 3 rd
input for the bottom most full-adder in circuit as shown in Figure. 4.

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2) TS-3 gate as full-adder: TS-3 gate can be used as full adder without producing carry.
Here the sum of A, B and carry input C is obtained in the 3rd output (R) which is represented in
Equation 3.

3)HNG gate as Full-adder: HNG gate can be used as full adder. For HNG gate to work as
full-adder the 4th input (D) must be always zero. Here the sum of A, B and carry input C
isobtained in R in Equation 1 and carry of their sum in Equation 2.

4)MSH gate as D-latch: MSH gate is to be used as the reversible D-latch and the 4th input
(D) must be set to zero. the 3 rd output R is pulled back to its 3 rd input C and the required bit is
obtained in 4th output S whose function is denoted in Equation 5.

5) Binary counter using reversible D-latch: The proposed counter circuit is denoted in
Fig 4. After giving the clock input the counter starts. The Up Down input is provided by using a
NOT gate to the bottom most HNG gate. The last output of each HNG gate is the carry bit which
is used as the 4th input to immediately upper HNG gate or TS-3 gate. The 3rd output of each of
the HNG and TS-3 gate is fed to each of the MSH gate’s 2nd input which performs as the D-latch.
The final output is denoted by Q3Q2Q1Q0 which is the 4th input of MSH gate. The complete
circuit is shown in Fig 4.

Page 15
6.3 Data flow diagram

Fig.6.1 Block diagram of a compact quantum cost-efficient design of a reversible binary counter

Page 16
 CHAPTER - 7

INTRODUCTION TO VLSI

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by

combining thousands of transistors into a single chip. VLSI began in the 1970s when
complex semiconductor and communication technologies were being developed.
The microprocessor is a VLSI device.

Before the introduction of VLSI technology, most ICs had a limited set of functions they
could perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic.
VLSI lets IC designers add all of these into one chip.

The electronics industry has achieved a phenomenal growth over the last few decades,
mainly due to the rapid advances in large scale integration technologies and system design
applications. With the advent of very large scale integration (VLSI) designs, the number of
applications of integrated circuits (ICs) in high-performance computing, controls,
telecommunications, image and video processing, and consumer electronics has been rising at a
very fast pace.

Page 17
 The current cutting-edge technologies such as high resolution and low bit-rate video and
cellular communications provide the end-users a marvelous amount of applications, processing
power and portability. This trend is expected to grow rapidly, with very important implications
on VLSI design and systems design.

The VLSI IC circuits design flow is shown in the figure below. The various levels of
design are numbered and the blocks show processes in the design flow.

Specifications comes first, they describe abstractly, the functionality, interface, and the
architecture of the digital IC circuit to be designed.

Behavioral description is then created to analyze the design in terms of functionality,

performance, compliance to given standards, and other specifications.

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RTL description is done using HDLs. This RTL description is simulated to test functionality.
From here onwards we need the help of EDA tools.

RTL description is then converted to a gate-level netlist using logic synthesis tools. A gatelevel
netlist is a description of the circuit in terms of gates and connections between them, which are
made in such a way that they meet the timing, power and area specifications.

Finally, a physical layout is made, which will be verified and then sent to fabrication.

7.1 FPGA DESIGN FLOW

FPGA contains a two dimensional arrays of logic blocks and interconnections between logic
blocks. Both the logic blocks and interconnects are programmable. Logic blocks are
programmed to implement a desired function and the interconnects are programmed using the
switch boxes to connect the logic blocks. To be more clear, if we want to implement a
complex design (CPU for instance), then the design is divided into small sub functions and
each sub function is implemented using one logic block. Now, to get our desired design
(CPU), all the sub functions implemented in logic blocks must be connected and this is done
by programming the interconnects.
Internal structure of an FPGA is depicted in the following figure.

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Fig:-7.1

FPGAs, alternative to the custom ICs, can be used to implement an entire System On one Chip
(SOC). The main advantage of FPGA is ability to reprogram. User can reprogram an FPGA to
implement a design and this is done after the FPGA is manufactured. This brings the name
“Field Programmable.”
Custom ICs are expensive and takes long time to design so they are useful when produced in
bulk amounts. But FPGAs are easy to implement with in a short time with the help of
Computer Aided Designing (CAD) tools (because there is no physical layout process, no mask
making, and no IC manufacturing).
Some disadvantages of FPGAs are, they are slow compared to custom ICs as they can’t handle
vary complex designs and also they draw more power.
Xilinx logic block consists of one Look Up Table (LUT) and one FlipFlop. An LUT is used to
implement number of different functionality. The input lines to the logic block go into the
LUT and enable it. The output of the LUT gives the result of the logic function that it
implements and the output of logic block is registered or unregistered out put from the LUT.

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SRAM is used to implement a LUT.A k-input logic function is implemented using 2^k * 1 size
SRAM. Number of different possible functions for k input LUT is 2^2^k. Advantage of such
an architecture is that it supports implementation of so many logic functions, however the
disadvantage is unusually large number of memory cells required to implement such a logic
block in case number of inputs is large.

Fig:-7.2 a 4-input LUT based implementation of logic block.

LUT based design provides for better logic block utilization. A k-input LUT based logic block
can be implemented in number of different ways with trade off between performance and logic
density.
An n-LUT can be shown as a direct implementation of a function truth-table. Each of the latch
holds the value of the function corresponding to one input combination. For Example: 2-LUT
can be used to implement 16 types of functions like AND , OR, A+not B .... etc.

Page 21
A B AND OR NAND ...... ....

0 0 0 0 1

0 1 0 1 1

1 0 0 1 1

1 1 1 1 0

Interconnects

A wire segment can be described as two end points of an interconnect with no programmable
switch between them. A sequence of one or more wire segments in an FPGA can be termed as
a track.
Typically an FPGA has logic blocks, interconnects and switch blocks (Input/Output blocks).
Switch blocks lie in the periphery of logic blocks and interconnect. Wire segments are
connected to logic blocks through switch blocks. Depending on the required design, one logic
block is connected to another and so on.

FPGA DESIGN FLOW

In this part of tutorial we are going to have a short intro on FPGA design flow. A simplified
version of design flow is given in the flowing diagram.

Page 22
Fig:-7.3

7.1.1 Design Entry

There are different techniques for design entry. Schematic based, Hardware Description
Language and combination of both etc. . Selection of a method depends on the design and
designer. If the designer wants to deal more with Hardware, then Schematic entry is the better
choice. When the design is complex or the designer thinks the design in an algorithmic way
then HDL is the better choice. Language based entry is faster but lag in performance and
density.
HDLs represent a level of abstraction that can isolate the designers from the details of the
hardware implementation. Schematic based entry gives designers much more visibility into
the hardware. It is the better choice for those who are hardware oriented. Another method but
rarely used is state-machines. It is the better choice for the designers who think the design as a

Page 23
series of states. But the tools for state machine entry are limited. In this documentation we are
going to deal with the HDL based design entry.

7.1.2 Synthesis
The process which translates VHDL or Verilog code into a device netlist formate. i.e a
complete circuit with logical elements( gates, flip flops, etc…) for the design.If the design
contains more than one sub designs, ex. to implement a processor, we need a CPU as one
design element and RAM as another and so on, then the synthesis process generates netlist for
each design element
Synthesis process will check code syntax and analyze the hierarchy of the design which
ensures that the design is optimized for the design architecture, the designer has selected. The
resulting netlist(s) is saved to an NGC( Native Generic Circuit) file (for Xilinx® Synthesis
Technology (XST)).

Fig:-7.1.2

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7.1.3. Implementation
This process consists a sequence of three steps
1. Translate
2. Map
3. Place and Route

7.1.3.1 Translate
This process combines all the input netlists and constraints to a logic design file. This
information is saved as a NGD (Native Generic Database) file. This can be done using NGD
Build program. Here, defining constraints is nothing but, assigning the ports in the design to
the physical elements (ex. pins, switches, buttons etc) of the targeted device and specifying
time requirements of the design. This information is stored in a file named UCF (User
Constraints File). Tools used to create or modify the UCF are PACE, Constraint Editor etc.

Fig:-7.1.3.1

7.1.3.2 Map

This process divides the whole circuit with logical elements into sub blocks such that they can
be fit into the FPGA logic blocks. That means map process fits the logic defined by the NGD

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file into the targeted FPGA elements (Combinational Logic Blocks (CLB), Input Output
Blocks (IOB)) and generates an NCD (Native Circuit Description) file which physically
represents the design mapped to the components of FPGA. MAP program is used for this
purpose.

7.1.3.3 Place and Route

PAR program is used for this process. The place and route process places the sub blocks from
the map process into logic blocks according to the constraints and connects the logic blocks.
Ex. if a sub block is placed in a logic block which is very near to IO pin, then it may save the
time but it may effect some other constraint. So trade off between all the constraints is taken
account by the place and route process. The PAR tool takes the mapped NCD file as input and
produces a completely routed NCD file as output. Output NCD file consists the routing
information.

Fig:-7.1.3.3

Place and Route PAR program is used for this process. The place and route process places the
sub blocks from the map process into logic blocks according to the constraints and connects
the logic blocks. Ex. if a sub block is placed in a logic block which is very near to IO pin, then

Page 26
it may save the time but it may effect some other constraint. So trade off between all the
constraints is taken account by the place and route process. The PAR tool takes the mapped
NCD file as input and produces a completely routed NCD file as output. Output NCD file
consists the routing information.

Fig - 7.1.3.4

7.1.4 Device Programming

Now the design must be loaded on the FPGA. But the design must be converted to a format so
that the FPGA can accept it. BITGEN program deals with the conversion. The routed NCD file
is then given to the BITGEN program to generate a bit stream (a .BIT file) which can be used
to configure the target FPGA device. This can be done using a cable. Selection of cable
depends on the design.

7.1.5 Design Verification

Verification can be done at different stages of the process steps.

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7.1.6 Behavioral Simulation (RTL Simulation) This is first of all simulation steps; those are
encountered throughout the hierarchy of the design flow. This simulation is performed before
synthesis process to verify RTL (behavioral) code and to confirm that the design is functioning
as intended. Behavioral simulation can be performed on either VHDL or Verilog designs. In
this process, signals and variables are observed, procedures and functions are traced and
breakpoints are set. This is a very fast simulation and so allows the designer to change the
HDL code if the required functionality is not met with in a short time period. Since the design
is not yet synthesized to gate level, timing and resource usage properties are still unknown.

7.1.7 Functional simulation (Post Translate Simulation) Functional simulation gives

information about the logic operation of the circuit. Designer can verify the functionality of the
design using this process after the Translate process. If the functionality is not as expected,
then the designer has to made changes in the code and again follow the design flow steps.

7.1.8. Static Timing Analysis This can be done after MAP or PAR processes Post MAP
timing report lists signal path delays of the design derived from the design logic. Post Place
and Route timing report incorporates timing delay information to provide a comprehensive
timing summary of the design.

7.2 Introduction to Verilog

In the semiconductor and electronic design industry, Verilog is a hardware description

language(HDL) used to model electronic systems. Verilog HDL, not to be confused
with VHDL (a competing language), is most commonly used in the design, verification, and
implementation ofdigital logic chips at the register-transfer level of abstraction. It is also used
in the verification ofanalog and mixed-signal circuits.

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7.2.1 Overview
Hardware description languages such as Verilog differ from software programming
languages because they include ways of describing the propagation of time and signal
dependencies (sensitivity). There are two assignment operators, a blocking assignment (=), and
a non-blocking (<=) assignment. The non-blocking assignment allows designers to describe a
state-machine update without needing to declare and use temporary storage variables (in any
general programming language we need to define some temporary storage spaces for the
operands to be operated on subsequently; those are temporary storage variables). Since these
concepts are part of Verilog's language semantics, designers could quickly write descriptions of
large circuits in a relatively compact and concise form. At the time of Verilog's introduction
(1984), Verilog represented a tremendous productivity improvement for circuit designers who
were already using graphical schematic capturesoftware and specially-written software
programs to document and simulate electronic circuits.

The designers of Verilog wanted a language with syntax similar to the C programming
language, which was already widely used in engineering software development. Verilog
is case-sensitive, has a basic preprocessor (though less sophisticated than that of ANSI C/C++),
and equivalent control flow keywords (if/else, for, while, case, etc.), and compatible operator
precedence. Syntactic differences include variable declaration (Verilog requires bit-widths on
net/reg types[clarification needed]
), demarcation of procedural blocks (begin/end instead of curly
braces {}), and many other minor differences.

A Verilog design consists of a hierarchy of modules. Modules encapsulate design

hierarchy, and communicate with other modules through a set of declared input, output, and
bidirectional ports. Internally, a module can contain any combination of the following:
net/variable declarations (wire, reg, integer, etc.), concurrent and sequential statement blocks,
and instances of other modules (sub-hierarchies). Sequential statements are placed inside a
begin/end block and executed in sequential order within the block. But the blocks themselves
are executed concurrently, qualifying Verilog as a dataflow language.

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 Verilog's concept of 'wire' consists of both signal values (4-state: "1, 0, floating,
undefined") and strengths (strong, weak, etc.). This system allows abstract modeling of shared
signal lines, where multiple sources drive a common net. When a wire has multiple drivers, the
wire's (readable) value is resolved by a function of the source drivers and their strengths.

A subset of statements in the Verilog language is synthesizable. Verilog modules that

conform to a synthesizable coding style, known as RTL (register-transfer level), can be
physically realized by synthesis software. Synthesis software algorithmically transforms the
(abstract) Verilog source into a net list, a logically equivalent description consisting only of
elementary logic primitives (AND, OR, NOT, flip-flops, etc.) that are available in a
specific FPGA or VLSI technology. Further manipulations to the net list ultimately lead to a
circuit fabrication blueprint (such as a photo mask set for an ASIC or a bit stream file for
an FPGA).

7.3 History

7.3.1 Beginning
Verilog was the first modern hardware description language to be invented. It was
created by Phil Moorby and Prabhu Goel during the winter of 1983/1984. The wording for this
process was "Automated Integrated Design Systems" (later renamed to Gateway Design
Automation in 1985) as a hardware modeling language. Gateway Design Automation was
purchased by Cadence Design Systems in 1990. Cadence now has full proprietary rights to
Gateway's Verilog and the Verilog-XL, the HDL-simulator that would become the de-facto
standard (of Verilog logic simulators) for the next decade. Originally, Verilog was intended to
describe and allow simulation; only afterwards was support for synthesis added.

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7.3.2 Verilog-95
With the increasing success of VHDL at the time, Cadence decided to make the
language available for open standardization. Cadence transferred Verilog into the public
domain under the Open Verilog International (OVI) (now known as Accellera) organization.
Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly
referred to as Verilog-95.

In the same time frame Cadence initiated the creation of Verilog-A to put standards
support behind its analog simulator Spectre. Verilog-A was never intended to be a standalone
language and is a subset of Verilog-AMS which encompassed Verilog-95.

7.3.3 V erilog 2001

Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that
users had found in the original Verilog standard. These extensions became IEEE Standard
1364-2001 known as Verilog-2001.

Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support for
(2's complement) signed nets and variables. Previously, code authors had to perform signed
operations using awkward bit-level manipulations (for example, the carry-out bit of a simple 8-
bit addition required an explicit description of the Boolean algebra to determine its correct
value). The same function under Verilog-2001 can be more succinctly described by one of the
built-in operators: +, -, /, *, >>>. A generate/endgenerate construct (similar to VHDL's
generate/endgenerate) allows Verilog-2001 to control instance and statement instantiation
through normal decision operators (case/if/else). Using generate/endgenerate, Verilog-2001 can
instantiate an array of instances, with control over the connectivity of the individual instances.
File I/O has been improved by several new system tasks. And finally, a few syntax additions
were introduced to improve code readability (e.g. always @*, named parameter override, C-
style function/task/module header declaration).

Verilog-2001 is the dominant flavor of Verilog supported by the majority of

commercial EDA software packages.

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7.3.4 Verilog 2005
Not to be confused with SystemVerilog, Verilog 2005 (IEEE Standard 1364-2005) consists of
minor corrections, spec clarifications, and a few new language features (such as the uwire
keyword).

A separate part of the Verilog standard, Verilog-AMS, attempts to integrate analog and mixed
signal modeling with traditional Verilog.

7.3.5 SystemVerilog
SystemVerilog is a superset of Verilog-2005, with many new features and capabilities to aid
design verification and design modeling. As of 2009, the SystemVerilog and Verilog language
standards were merged into SystemVerilog 2009 (IEEE Standard 1800-2009).

The advent of hardware verification languages such as OpenVera, and Verisity's e

language encouraged the development of Superlog by Co-Design Automation Inc. Co-Design
Automation Inc was later purchased by Synopsys. The foundations of Superlog and Vera were
donated to Accellera, which later became the IEEE standard P1800-2005: SystemVerilog.

In the late 1990s, the Verilog Hardware Description Language (HDL) became the most
widely used language for describing hardware for simulation and synthesis. However, the first
two versions standardized by the IEEE (1364-1995 and 1364-2001) had only simple constructs
for creating tests. As design sizes outgrew the verification capabilities of the language,
commercial Hardware Verification Languages (HVL) such as Open Vera and e were created.
Companies that did not want to pay for these tools instead spent hundreds of man-years
creating their own custom tools. This productivity crisis (along with a similar one on the
design side) led to the creation of Accellera, a consortium of EDA companies and users who
wanted to create the next generation of Verilog. The donation of the Open-Vera language
formed the basis for the HVL features of SystemVerilog.Accellera’s goal was met in
November 2005 with the adoption of the IEEE standard P1800-2005 for SystemVerilog, IEEE
(2005).

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 The most valuable benefit of SystemVerilog is that it allows the user to construct
reliable, repeatable verification environments, in a consistent syntax, that can be used across
multiple projects
Some of the typical features of an HVL that distinguish it from a Hardware Description
Language such as Verilog or VHDL are
 Constrained-random stimulus generation
 Functional coverage
 Higher-level structures, especially Object Oriented Programming
 Multi-threading and interprocess communication
 Support for HDL types such as Verilog’s 4-state values
 Tight integration with event-simulator for control of the design
There are many other useful features, but these allow you to create test benches at a
higher level of abstraction than you are able to achieve with an HDL or a programming
language such as C.
System Verilog provides the best framework to achieve coverage-driven verification
(CDV). CDV combines automatic test generation, self-checking testbenches, and coverage
metrics to significantly reduce the time spent verifying a design. The purpose of CDV is to:

 Eliminate the effort and time spent creating hundreds of tests.

 Ensure thorough verification using up-front goal setting.

 Receive early error notifications and deploy run-time checking and error analysis to simplify
debugging.

6.3Examples

Ex1: A hello world program looks like this:

module main;
initial
begin

Page 33
 $display("Hello world!");
$finish;
end
endmodule

Ex2: A simple example of two flip-flops follows:

module toplevel(clock,reset);
input clock;
input reset;

reg flop1;
reg flop2;

always @ (posedge reset or posedge clock)

if (reset)
begin
flop1 <= 0;
flop2 <= 1;
end
else
begin
flop1 <= flop2;
flop2 <= flop1;
end
endmodule

The "<=" operator in Verilog is another aspect of its being a hardware description
language as opposed to a normal procedural language. This is known as a "non-blocking"
assignment. Its action doesn't register until the next clock cycle. This means that the order of
the assignments are irrelevant and will produce the same result: flop1 and flop2 will swap
values every clock.

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 The other assignment operator, "=", is referred to as a blocking assignment. When "="
assignment is used, for the purposes of logic, the target variable is updated immediately. In the
above example, had the statements used the "=" blocking operator instead of "<=", flop1 and
flop2 would not have been swapped. Instead, as in traditional programming, the compiler
would understand to simply set flop1 equal to flop2 (and subsequently ignore the redundant
logic to set flop2 equal to flop1.)

Ex3: An example counter circuit follows:

module Div20x (rst, clk, cet, cep, count, tc);

// TITLE 'Divide-by-20 Counter with enables'
// enable CEP is a clock enable only
// enable CET is a clock enable and
// enables the TC output
// a counter using the Verilog language

parameter size = 5;
parameter length = 20;

input rst; // These inputs/outputs represent

input clk; // connections to the module.
input cet;
input cep;

output [size-1:0] count;

output tc;

reg [size-1:0] count; // Signals assigned

// within an always
// (or initial)block
// must be of type reg

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wire tc; // Other signals are of type wire

// The always statement below is a parallel

// execution statement that
// executes any time the signals
// rst or clk transition from low to high

always @ (posedge clk or posedge rst)

if (rst) // This causes reset of the cntr
count <= {size{1'b0}};
else
if (cet && cep) // Enables both true
begin
if (count == length-1)
count <= {size{1'b0}};
else
count <= count + 1'b1;
end

// the value of tc is continuously assigned

// the value of the expression
assign tc = (cet && (count == length-1));

endmodule

Ex4: An example of delays:

...
reg a, b, c, d;
wire e;
...
always @(b or e)

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 begin
a = b & e;
b = a | b;
#5 c = b;
d = #6 c ^ e;
end

The always clause above illustrates the other type of method of use, i.e. the always
clause executes any time any of the entities in the list change, i.e. the b or e change. When one
of these changes, immediately a is assigned a new value, and due to the blocking assignment b
is assigned a new value afterward (taking into account the new value of a.) After a delay of 5
time units, c is assigned the value of b and the value of c ^ e is tucked away in an invisible
store. Then after 6 more time units, d is assigned the value that was tucked away.

Signals that are driven from within a process (an initial or always block) must be of type reg.
Signals that are driven from outside a process must be of type wire. The keyword reg does not
necessarily imply a hardware register.

7.3.6 Constants
The definition of constants in Verilog supports the addition of a width parameter. The basic
syntax is:

<Width in bits>'<base letter><number>

Examples:

 12'h123 - Hexadecimal 123 (using 12 bits)

 20'd44 - Decimal 44 (using 20 bits - 0 extension is automatic)
 4'b1010 - Binary 1010 (using 4 bits)
 6'o77 - Octal 77 (using 6 bits)

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7.3.7 Synthesizable Constructs
There are several statements in Verilog that have no analog in real hardware, e.g.
$display. Consequently, much of the language can not be used to describe hardware. The
examples presented here are the classic subset of the language that has a direct mapping to real
gates.

// Mux examples - Three ways to do the same thing.

// The first example uses continuous assignment
wire out;
assign out = sel ? a : b;
// the second example uses a procedure
// to accomplish the same thing.
reg out;
always @(a or b or sel)
begin
case(sel)
1'b0: out = b;
1'b1: out = a;
endcase
end
// Finally - you can use if/else in a
// procedural structure.
reg out;
always @(a or b or sel)
if (sel)
out = a;
else
out = b;

The next interesting structure is a transparent latch it will pass the input to the output
when the gate signal is set for "pass-through", and captures the input and stores it upon

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transition of the gate signal to "hold". The output will remain stable regardless of the input
signal while the gate is set to "hold". In the example below the "pass-through" level of the gate
would be when the value of the if clause is true, i.e. gate = 1. This is read "if gate is true, the
din is fed to latch_out continuously." Once the if clause is false, the last value at latch_out will
remain and is independent of the value of din.

EX6: // Transparent latch example

reg out;
always @(gate or din)
if(gate)
out = din; // Pass through state
// Note that the else isn't required here. The variable
// out will follow the value of din while gate is high.
// When gate goes low, out will remain constant.

The flip-flop is the next significant template; in Verilog, the D-flop is the simplest, and it can
be modeled as:

reg q;
always @(posedge clk)
q <= d;

The significant thing to notice in the example is the use of the non-blocking assignment.
A basic rule of thumb is to use <= when there is a posedge or negedge statement within the
always clause.

A variant of the D-flop is one with an asynchronous reset; there is a convention that the
reset state will be the first if clause within the statement.

reg q;
always @(posedge clk or posedge reset)
if(reset)
q <= 0;
else
q <= d;

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The next variant is including both an asynchronous reset and asynchronous set condition; again
the convention comes into play, i.e. the reset term is followed by the set term.

reg q;
always @(posedge clk or posedge reset or posedge set)
if(reset)
q <= 0;
else
if(set)
q <= 1;
else
q <= d;

Note: If this model is used to model a Set/Reset flip flop then simulation errors can
result. Consider the following test sequence of events. 1) reset goes high 2) clk goes high 3) set
goes high 4) clk goes high again 5) reset goes low followed by 6) set going low. Assume no
setup and hold violations.

In this example the always @ statement would first execute when the rising edge of
reset occurs which would place q to a value of 0. The next time the always block executes
would be the rising edge of clk which again would keep q at a value of 0. The always block
then executes when set goes high which because reset is high forces q to remain at 0. This
condition may or may not be correct depending on the actual flip flop. However, this is not the
main problem with this model. Notice that when reset goes low, that set is still high. In a real
flip flop this will cause the output to go to a 1. However, in this model it will not occur because
the always block is triggered by rising edges of set and reset - not levels. A different approach
may be necessary for set/reset flip flops.

Note that there are no "initial" blocks mentioned in this description. There is a split
between FPGA and ASIC synthesis tools on this structure. FPGA tools allow initial blocks
where reg values are established instead of using a "reset" signal. ASIC synthesis tools don't
support such a statement. The reason is that an FPGA's initial state is something that is

Page 40
downloaded into the memory tables of the FPGA. An ASIC is an actual hardware
implementation.

7.3.8 Initial Vs Always:

There are two separate ways of declaring a Verilog process. These are the always and
the initial keywords. The always keyword indicates a free-running process.
The initial keyword indicates a process executes exactly once. Both constructs begin execution
at simulator time 0, and both execute until the end of the block. Once an always block has
reached its end, it is rescheduled (again). It is a common misconception to believe that an initial
block will execute before an always block. In fact, it is better to think of the initial-block as a
special-case of the always-block, one which terminates after it completes for the first time.

//Examples:
initial
begin
a = 1; // Assign a value to reg a at time 0
#1; // Wait 1 time unit
b = a; // Assign the value of reg a to reg b
end

always @(a or b) // Any time a or b CHANGE, run the process

begin
if (a)
c = b;
else
d = ~b;
end // Done with this block, now return to the top (i.e. the @ event-control)

always @(posedge a)// Run whenever reg a has a low to high change
a <= b;

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 These are the classic uses for these two keywords, but there are two significant
additional uses. The most common of these is an alwayskeyword without the @(...) sensitivity
list. It is possible to use always as shown below:

always
begin // Always begins executing at time 0 and NEVER stops
clk = 0; // Set clk to 0
#1; // Wait for 1 time unit
clk = 1; // Set clk to 1
#1; // Wait 1 time unit
end // Keeps executing - so continue back at the top of the begin

The always keyword acts similar to the "C" construct while(1) {..} in the sense that it
will execute forever.

The other interesting exception is the use of the initial keyword with the addition of
the forever keyword.

7.3.9 Race Condition

The order of execution isn't always guaranteed within Verilog. This can best be
illustrated by a classic example. Consider the code snippet below:

initial
a = 0;
initial
b = a;
initial
begin
#1;
$display("Value a=%b Value of b=%b",a,b);
end

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What will be printed out for the values of a and b? Depending on the order of execution of the
initial blocks, it could be zero and zero, or alternately zero and some other arbitrary
uninitialized value. The $display statement will always execute after both assignment blocks
have completed, due to the #1 delay.

7.3.10 Operators

Note: These operators are not shown in order of precedence.

Op Operator Operation performed

era symbols
~ Bitwise NOT (1's complement)
tor
typ & Bitwise AND
Bitwis
e
e | Bitwise OR

^ Bitwise XOR

~^ or ^~ Bitwise XNOR

! NOT
Logica
l && AND

|| OR

& Reduction AND

Reduct ~& Reduction NAND

ion
| Reduction OR

~| Reduction NOR

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 ^ Reduction XOR

~^ or ^~ Reduction XNOR

+ Addition

- Subtraction

Arith - 2's complement

metic
* Multiplication

/ Division

** Exponentiation (*Verilog-2001)

> Greater than

< Less than

>= Greater than or equal to

Relati <= Less than or equal to

onal
== Logical equality (bit-value 1'bX is removed from
comparison)
!= Logical inequality (bit-value 1'bX is removed from
comparison)
=== 4-state logical equality (bit-value 1'bX is taken as literal)

!== 4-state logical inequality (bit-value 1'bX is taken as literal)

>> Logical right shift

<< Logical left shift

Shift

>>> Arithmetic right shift (*Verilog-2001)

<<< Arithmetic left shift (*Verilog-2001)

Page 44
 Concat { , } Concatenation
enatio
Replic {n{m}} Replicate value m for n times
n
ation
Condit ? : Conditional
ional

7.3.11 System Tasks:

System tasks are available to handle simple I/O, and various design measurement functions. All
system tasks are prefixed with $ to distinguish them from user tasks and functions. This section
presents a short list of the most often used tasks. It is by no means a comprehensive list.

 $display - Print to screen a line followed by an automatic newline.

 $write - Write to screen a line without the newline.
 $s write - Print to variable a line without the newline.
 $s scan f - Read from variable a format-specified string. (*Verilog-2001)
 $f open - Open a handle to a file (read or write)
 $f display - Write to file a line followed by an automatic newline.
 $f write - Write to file a line without the newline.
 $f scan f - Read from file a format-specified string. (*Verilog-2001)
 $f close - Close and release an open file handle.
 $readmemh - Read hex file content into a memory array.
 $readmemb - Read binary file content into a memory array.
 $monitor - Print out all the listed variables when any change value.
 $time - Value of current simulation time.
 $dump file - Declare the VCD (Value Change Dump) format output file name.

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 $dump vars - Turn on and dump the variables.
 $dump ports - Turn on and dump the variables in Extended-VCD format.

 $random - Return a random value.

7.4 SOFTWARE DESCRIPTION

Software used:

• HDL Design.

7.4.1 Introduction of HDL Design:

What is “HDL”?

• HDL = Hardware Description Language.

• A text-based method for describing hardware to a synthesis tool.

Traditionally, digital design was done with schematic entry. In today’s competitive business
environment, building cost effective products quickly is best done with a top down
methodology utilizing hardware description languages (HDLs) and synthesis. Schematic entry
still used at the board level, but this will probably also change. As a first example of the power
of using HDLs, consider the code below. It implements an 8-bit shift register with enable. It is
easily changed to about any width with a few quick key strokes. In the amount of time it takes
to sneeze, it can be synthesized into the schematic on the next page.

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 HDLs - Motivation Increased productivity shorter development cycles, more features,
but........ still shorter time-to-market, 10-20K gates/day/engineer Flexible modelling
capabilities. can represent designs of gates or systems description can be very abstract or very
structural Design reuse is enabled. packages, libraries, support reusable, portable code Design
changes are fast and easily done convert an 8-bit register to 64-bits........ four key strokes, and
its done! exploration of alternative architectures can be done quickly Use of various design
methodologies. top-down, bottom-up, complexity hiding (abstraction) Technology and vendor
independence. same code can be targeted to CMOS, ECL, GaAs same code for: TI, NEC, LSI,
TMSC same code for: .5um, .35um, .25um, .18um Enables use of logic synthesis which allows
an investigation of the area and timing space. ripple adder or CLA? How many stages of look
ahead? HDLs can leverage software design environment tools. vi, emacs, cvs, lint, grep, make

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files Using a standard language promotes clear communication of ideas and designs. schematic
standards?... what’s that... a tower of Babel.

HDLs - What are they? How do we use them?

A Hardware Description Language (HDL) is a programming language used to model the

intended operation of a piece of hardware.

An HDL can facilitate: abstract behavioural modelling -no structural or design aspect involved
hardware structure modelling -a hardware structure is explicitly implied.

In this class we will use an HDL to describe the structure of a hardware design.

When we use an HDL to create hardware by logic synthesis, we will write code at the Register
Transfer Language (RTL) level.

At this level we are implying certain hardware structures when we understand apriority.

When programming at the RTL level, we are not describing an algorithm which some
hardware will execute, we are describing a hardware structure.

Without knowing beforehand what the structure is we want to build, use of an HDL will
probably produce a steaming pile (think manure) of gates which may or may not function as
desired.

You must know what you want to build before you describe it in an HDL.

Knowing an HDL does not relieve you of thoroughly understanding digital design.

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7.5 INTRODUCTION TO XILINX

7.5.1 Migrating Projects from Previous ISE Software Releases:

When you open a project file from a previous release, the ISE® software prompts you to
migrate your project. If you click Backup and Migrate or Migrate Only, the software
automatically converts your project file to the current release. If you click Cancel, the software
does not convert your project and, instead, opens Project Navigator with no project loaded.
Note: After you convert your project, you cannot open it in previous versions of the ISE
software, such as the ISE 11 software. However, you can optionally create a backup of the
original project as part of project migration, as described below.

To Migrate a Project

1. In the ISE 12 Project Navigator, select File > Open Project.

2. In the Open Project dialog box, select the .xise file to migrate. Note You may need to
change the extension in the Files of type field to display .npl (ISE 5 and ISE 6 software) or .ise
(ISE 7 through ISE 10 software) project files.

3. In the dialog box that appears, select Backup and Migrate or Migrate Only.

4. The ISE software automatically converts your project to an ISE 12 project. Note If you
chose to Backup and Migrate, a backup of the original project is created at
project_name_ise12migration.zip.

5. Implement the design using the new version of the software. Note Implementation status is
not maintained after migration.

7.5.2 Properties:

For information on properties that have changed in the ISE 12 software, see ISE 11 to ISE 12
Properties Conversion

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7.5.3 IP Modules:

If your design includes IP modules that were created using CORE Generator™ software or
Xilinx® Platform Studio (XPS) and you need to modify these modules, you may be required
to update the core. However, if the core netlist is present and you do not need to modify the
core, updates are not required and the existing netlist is used during implementation.

7.5.4 Obsolete Source File Types:

The ISE 12 software supports all of the source types that were supported in the ISE 11
software. If you are working with projects from previous releases, state diagram source files
(.dia), ABEL source files (.abl), and test bench waveform source files (.tbw) are no longer
supported. For state diagram and ABEL source files, the software finds an associated HDL file
and adds it to the project, if possible. For test bench waveform files, the software automatically
converts the TBW file to an HDL test bench and adds it to the project. To convert a TBW file
after project migration, see Converting a TBW File to an HDL Test Bench.

7.5.5 Using ISE Example Projects:

To help familiarize you with the ISE® software and with FPGA and CPLD designs, a set of
example designs is provided with Project Navigator. The examples show different design
techniques and source types, such as VHDL, Verilog, schematic, or EDIF, and include
different constraints and IP.

To Open an Example

1. Select File > Open Example.

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2. In the Open Example dialog box, select the Sample Project Name. Note To help you choose
an example project, the Project Description field describes each project. In addition, you can
scroll to the right to see additional fields, which provide details about the project.

3. In the Destination Directory field, enter a directory name or browse to the directory.

4. Click OK. The example project is extracted to the directory you specified in the Destination
Directory field and is automatically opened in Project Navigator. You can then run processes
on the example project and save any changes. Note If you modified an example project and
want to overwrite it with the original example project, select File > Open Example, select the
Sample Project Name, and specify the same Destination Directory you originally used. In the
dialog box that appears, select Overwrite the existing project and click OK.

7.5.6 Creating a Project:

Project Navigator allows you to manage your FPGA and CPLD designs using an ISE®
project, which contains all the source files and settings specific to your design. First, you must
create a project and then, add source files, and set process properties. After you create a
project, you can run processes to implement, constrain, and analyze your design. Project
Navigator provides a wizard to help you create a project as follows. Note If you prefer, you
can create a project using the New Project dialog box instead of the New Project Wizard. To
use the New Project dialog box, deselect the Use New Project wizard option in the ISE
General page of the Preferences dialog box. To Create a Project

1. Select File > New Project to launch the New Project Wizard.

2. In the Create New Project page, set the name, location, and project type, and click Next.

3. For EDIF or NGC/NGO projects only: In the Import EDIF/NGC Project page, select the
input and constraint file for the project, and click Next.

4. In the Project Settings page, set the device and project properties, and click Next.

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5. In the Project Summary page, review the information, and click Finish to create the project
Project Navigator creates the project file (project_name.xise) in the directory you specified.
After you add source files to the project, the files appear in the Hierarchy pane of the

7.5.7 Design panel:

Project Navigator manages your project based on the design properties (toplevel module type,
device type, synthesis tool, and language) you selected when you created the project. It
organizes all the parts of your design and keeps track of the processes necessary to move the
design from design entry through implementation to programming the targeted Xilinx®
device. Note For information on changing design properties, see Changing Design Properties.
You can now perform any of the following:

• Create new source files for your project.

• Add existing source files to your project.

• Run processes on your source files. Modify process properties.

7.5.8 Creating a Copy of a Project: You can create a copy of a project to experiment with
different source options and implementations. Depending on your needs, the design source
files for the copied project and their location can vary as follows:

• Design source files are left in their existing location, and the copied project points to these
files.

• Design source files, including generated files, are copied and placed in a specified directory.

• Design source files, excluding generated files, are copied and placed in a specified directory.
Copied projects are the same as other projects in both form and function. For example, you can
do the following with copied projects:

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• Open the copied project using the File > Open Project menu command.

• View, modify, and implement the copied project.

• Use the Project Browser to view key summary data for the copied project and then, open the
copied project for further analysis and implementation, as described.

7.5.9 Using the Project Browser:

Alternatively, you can create an archive of your project, which puts all of the project contents
into a ZIP file. Archived projects must be unzipped before being opened in Project Navigator.
For information on archiving, see Creating a Project Archive.

To Create a Copy of a Project

1. Select File > Copy Project.

2. In the Copy Project dialog box, enter the Name for the copy. Note The name for the copy
can be the same as the name for the project, as long as you specify a different location.

3. Enter a directory Location to store the copied project.

4. Optionally, enter a Working directory. By default, this is blank, and the working directory is
the same as the project directory. However, you can specify a working directory if you want to
keep your ISE® project file (.xies extension) separate from your working area.

5. Optionally, enter a Description for the copy. The description can be useful in identifying key
traits of the project for reference later.

6. In the Source options area, do the following: Select one of the following options:

• Keep sources in their current locations - to leave the design source files in their existing
location. If you select this option, the copied project points to the files in their existing
location. If you edit the files in the copied project, the changes also appear in the original
project, because the source files are shared between the two projects.

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• Copy sources to the new location - to make a copy of all the design source files and place them
in the specified Location directory.

• If you select this option, the copied project points to the files in the specified directory. If you
edit the files in the copied project, the changes do not appear in the original project, because the
source files are not shared between the two projects.

• Optionally, select Copy files from Macro Search Path directories to copy files from the
directories you specify in the Macro Search Path property in the Translate Properties dialog box.
All files from the specified directories are copied, not just the files used by the design.

• Note: If you added a net list source file directly to the project as described in Working with Net
list-Based IP, the file is automatically copied as part of Copy Project because it is a project source
file. Adding net list source files to the project is the preferred method for incorporating net list
modules into your design, because the files are managed automatically by Project Navigator.

• Optionally, click Copy Additional Files to copy files that were not included in the original
project. In the Copy Additional Files dialog box, use the Add Files and Remove Files buttons to
update the list of additional files to copy.

• Additional files are copied to the copied project location after all other files are copied.To
exclude generated files from the copy, such as implementation results and reports, select.

7.5.10 Exclude generated files from the copy:

When you select this option, the copied project opens in a state in which processes have not yet
been run. 7.

To automatically open the copy after creating it, select Open the copied project. Note By default,
this option is disabled. If you leave this option disabled, the original project remains open after
the copy is made. Click OK.

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7.5.11 Creating a Project Archive:

A project archive is a single, compressed ZIP file with a .zip extension. By default, it contains all
project files, source files, and generated files, including the following:

• User-added sources and associated files

• Remote sources

• Verilog include files

• Files in the macro search path

• Generated files

• Non-project files

7.5.12 o Archive a Project:

1. Select Project > Archive.

2. In the Project Archive dialog box, specify a file name and directory for the ZIP file.

3. Optionally, select Exclude generated files from the archive to exclude generated files and
non-project files from the archive.

4. Click OK. A ZIP file is created in the specified directory.

To open the archived project, you must first unzip the ZIP file, and then, you can open the
project. Note Sources that reside outside of the project directory are copied into a remote_sources
subdirectory in the project archive.

When the archive is unzipped and opened, you must either specify the location of these files in
the remote_sources subdirectory for the unzipped project, or manually copy the sources into their
original location.

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 CHAPTER - 8

SAMPLE CODING AND RESULT

8.1 Code of “MSH gate”

Fig – 8.1 code of MSH gate

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8.2 Code of “HNG gate”

Fig – code of HNG gate

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8.3 Code of “look up table”

Fig – code of look up table

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8.4 Simulations Result

The simulated results are carried out in a dual core CPU, 4 GHz clock cycle, 4 Gigabytes of RAM
and 64-bit operating system by using Microwind DSCH. The simulation environment has been
specified with the time unit as nanoseconds (ns), default gate delay has been considered as 0.030
ns, default wire delay as 0.070 ns, voltage supply has been considered as 1.200 V and the
elementary gate current has been chosen as 500.00 mA. Moreover, CMOS 0.12 µm technology
has been selected as the logic simulation options.

The MOS length is 0.12 µm, where as the nmos width is 1.0 µm and pmos width Fig. 4. Proposed
Reversible Binary Counter using Reversible D-Latch is 2.0 µm.

The simulation result is depicted in Fig. 5. When Up Down value is 0, it counts upward. The
counter counts downward when the input Up Down value is set to 1 as shown in Fig. 5. The
proposed circuit has better performance than existing circuits in terms of quantum cost, total gate
count, ancillary input, garbage output, delay and hardware complexity which is given in Table I
and Fig. 6. Lemma 1 and its proof shows the calculation of the different comparison parameters.
Table II shows the improvement ratio with respect to [8] and [10] which is a clear indication of
the superiority of the proposed design.

Lemma 1. In the proposed binary counter circuit, the number of ancillary input is 7, the quantum
cost is 44, the number of garbage output is 16, the gates count is 9 and the hardware complexity
is 26α + 14β + 5γ Proof. The proposed circuit requires one not gate, one TS-3 gate, three HNG
gates, four MSH gates, as depicted in Fig. 4. So, total gate count is 1 + 1 + 3 + 4 = 9. As both the
HNG gate’s 4th input and MSH gate’s 4th input must be set to zero to perform as full-adder, the
number of ancillary input can be calculated as 3 ∗ 1 + 4 ∗ 1 = 7. The quantum cost of Not gate,
TS-3 gate, HNG gate and MSH gate is 0, 2, 6 and 6, respectively. Therefore, the total quantum
cost of the circuit is 0 ∗ 1 + 1 ∗ 2 + 3 ∗ 6 + 4 ∗ 6 = 44. As each of the TS-3 gate, HNG gate and
MSH gate produce two garbage outputs, the total number of garbage output is 2 ∗ 1 + 2 ∗ 3 + 2
∗ 4 = 16. The hardware complexity of NOT, TS-3, HNG and MSH gate is γ, 2α, 4α + 2β and 3α
+ 2β + γ accordingly. Hence the hardware complexity of the circuit = 1 ∗ γ + 1 ∗ 2α + 3(4α + 2β)
+ 4(3α + 2β + γ) = 26α + 14β + 5γ. Our proposed circuit has 31.25% improvement in terms of
quantum cost and delay, 58.82% improvement in terms of ancillary input and 5.8% improvement
in terms of garbage output, which denotes a huge improvement in comparison with the existing
best known work [8].

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8.5 Wave form

Fig – wave form of reversible binary counter

8.6 Graphical representation

Fig.6 Graphical representation of comparison parameters between existing [10] and proposed
circuit

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 CHAPTER - 9

CONCLUSION

Future computing devices are estimated to be reversible due to its optimum energy
consumption and minimum bit loss features. Counters are useful for digital clocks and timers, and
in frequency division, sequence generation and many more. In this paper, the design methodology
of a novel reversible binary counter circuit is proposed. The circuit is constructed with one NOT
gate, three HNG gates and one TS-3 gate which perform as full-adder and four MSH gates. MSH
gate is used as D-latch and every clock signal increments the output value of the counter. The
proposed circuit has a significant improvement in its quantum metrices and can be used in
counting number of pulses, count state decoding, quantum arithmetic logic unit as it is optimized
in terms of gate count, quantum cost, delay, ancillary input, garbage output and hardware
complexity.

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 CHAPTER – 10

REFERENCES

[1] R. Landauer, “Irreversibility and heat generation in the computing process,” IBM Journal of
Research and Development, vol. 44, no. 1/2, p. 261, 2000.

[2] C. H. Bennett, “Logical reversibility of computation,” IBM journal of Research and

Development, vol. 17, no. 6, pp. 525–532, 1973.

[3] M. U. Haque, Z. T. Sworna, and H. M. H. Babu, “An improved design of a reversible fault
tolerant lut-based fpga,” in 2016 29th International Conference on VLSI Design and 2016
15th International Conference on Embedded Systems (VLSID), pp. 445–450, IEEE, 2016.

[4] P. Joshi and I. Sahu, “A review paper on design of an asynchronous counter using novel
reversible sg gate,” in 2017 International Conference on Innovative Mechanisms for Industry
Applications (ICIMIA), pp. 617– 621, Feb 2017.

[5] R. Singh and M. K. Pandey, “Design and optimization of sequential counters using a novel
reversible gate,” in 2016 International Conference on Computing, Communication and
Automation (ICCCA), pp. 1393– 1398, April 2016.

[6] S. Mamataj and B. Das, “Effificient designing approach of different synchronous cyclic code
counters by sequential circuit elements of a novel reversible gate,” in 2014 International
Conference on Computational Intelligence and Communication Networks, pp. 1031–1036,
Nov 2014.

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[7] G. C. Naguboina and K. Anusudha, “Design and synthesis of combinational circuits using
reversible decoder in xilinx,” in 2017 International Conference on Computer, Communication
and Signal Processing (ICCCSP), pp. 1–6, Jan 2017.

[8] X. Qi, H. Zhu, F. Chen, J. Zhu, and Z. Zhang, “Novel designs of quantum reversible counters,”
International Journal of Theoretical Physics, vol. 55, no. 11, pp. 4987–4998, 2016.

[9] M. Haghparast and M. Samadi Gharajeh, “Design of a nanometric reversible 4-bit binary
counter with parallel load,” Australian Journal of Basic and Applied Sciences, vol. 5, pp. 63–
71, 07 2011.

[10] A. Bolhassani and M. Haghparast, “Optimised reversible divider circuit,” International

Journal of Innovative Computing and Applications, vol. 7, no. 1, pp. 13–33, 2016.

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