MARIA COLLEGE OF ENGINEERING & TECHNOLOGY- ATTOOR.

DEPARTMENT OF ECE
MODEL EXAM
EC8095- VLSI Design

MAX MARKS: 100 TIME : 3 Hrs YEAR: III ECE

PART -A(10 x 2=20)

1. Compare nMOS and pMOS transistor?
2. Draw the 3-input NOR gate using CMOS Logic with truth
table.?
3. What is meant by bubble pushing?
4. Design a circuit to compute F=AB+CD using NANDs and NORs.?
5. Mention the advantages of pipelined operation?
6. Deduce the properties of Schmitt trigger.?
7. List out the components of Data path.?
8. Define Clock gating.?
9. State the features of boundary scan method.?
10. Name the two different types of routing in FPGA.?

PART-B (5 x 13=65)
11.a) Ilustrate with necessary diagrams
(i) Ideal I-V characteristics of MOS transistors, (6)
(ii) C-V characteristics of MOS transistors. (7))
(or)
b) (i) Describe in detail about Layout design rules. (7)
(ii) Draw the stick diagram and layout design for the CMOS gate computing. Y = ( A +B+C )⋅D (6)

12.a) Write short notes on

(i) Domino logic, (7)
(ii) Dual-rail Domino Logic. (6)
(or)
b) Classify the types of power dissipation and manipulate each in detail. (13)
13.a) Analyze the basics of synchronous timing, clock skew, clock jitter and combined impact of skew
and jitter. (13)
(or)
b) Examine t h e M o n o s t a b l e S e q u e n t i a l c i r c u i t s a n d a s t a b l e circuits with neat an
example (13)

14.a) Examine the concept of carry look ahead adder and discuss its types. (13)
(or)

b) Analyse the operation of booth multiplication with suitable example. (13)

15.a) Describe the various types of ad hoc testing techniques with neat diagram. (13)
(or)
 b) Draw and explain the building blocks of FPGA ? (13)

PART – C(1 x 15=15)

16 . a) Discuss in detail about different types of scan design method and explain with neat diagram.
(or)
b) Evaluate the Master-Slave Edge-Triggered register with its timing properties and Non-ideal clock
signals.