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Advanced Digital Systems Design 09
Advanced Digital Systems Design 09
INSTITUTION
ELECTRICAL AND ELECTRONIC
DEPARTMENT ENGINEERING
EENG424
MODULE CODE
PROF JONAS A S REDWOOD-
MODULE LECTURER SAWYERR
Mobile : +232 76 670904, +232 88
001019, +232 25 273401
Email : jonas.redwood-
CONTACTS sawyerrd@usl.edu.sl,
osehsylrs1952@gmail.com,
jredwood_sawyerr@yahoo.com
References
1. http://www.reliabilityeducation
.com/ReliabilityPredictionBasic
s.pdf
2. http://www.mtl-
inst.com/images/uploads/datas
heets/App_Notes/AN9030.pdf
3. http://en.wikipedia.org/wiki/Fail
ure_rate
4. G C Loveday,1989. Electronic
SUGGESTED READINGREFERENCE Testing and Fault Diagnosis.
Longman Scientific &
TEXTS/MANUALS/WEBSITES
Technical. ISBN 0-582-03865-
0
5. Holdsworth, B. Digital Logic
Design. Butterworth
Heineman. 1987. ISBN 0 7506
0501 4
6. Loveday, G C. Electronic
testing and Fault Diagnosis.
Longman Scientific &
Technical. 1992. ISBN 0-582-
03865-0
09– Design using programmable
LECTURE NUMBER logic devices (PLD)
LECTURE DURATION (HOURS) 01
At the end of this lecture the students
should be able to :
1. Revise SR counters
SPECIFIC INSTRUCTIONAL OBJECTIVES AND 2. Identify and differentiate PLDs
LEARNING OUTCOMES 3. Design sequential circuits using
ROMS and PLAs
4. Solve numerical design
problems using PLDs
PART 3
Use of shift registers and the Universal State Diagram (USD) or deBruign diagram
Fig. 9.1. Two state USD S1
01
S0 S3
00
11
Lock-in Lock-in state on receipt of 11
state on receipt
00 10
S2
001 011
S2
010
S5
100 110
S4 S6
Recap
PLDs are devices that are programmable such as ROMs, PLAs and PALs
These have similar basic building blocks but with different degrees of programmable characteristics.
AND OR
Array Array
Programming Characteristics
PLD AND OR
ROM Fixed (using Programmable
decoders)
Programmable Programmable Programmable
Logic Array
(PLA)
Programmable Programmable Fixed
Array Logic
(PAL)
(Class exercise – revision) Design example
A logic circuit having two inputs, produces an output which is the square of its inputs. Design the circuit
using a ROM showing the sequence table and the ROM connection matrix of the circuit.
Solution
Sequence Table
Dec. A B W X Y Z
0 0 0 0 0 0 1
1 0 1 0 0 0 1
2 1 0 0 1 0 0
3 1 1 1 0 0 1
Here we note
Z = A’B + AB
Y=0
X = AB’
W = AB
A 0 (A’B’)
2x4
1 (A’B)
Decoder
2 (AB’}
B 3 (AB)
WX Y Z
Design of sequential circuits using ROMS
ROMs can be used in the implementation of clock-driven sequential circuits because of their capability to
operate as function generators. The principles of logic design are used and the implementation draws from
knowledge of the architecture of ROMS. The two-dimensional ROM structure will be used in the
implementation of the sequential equations derived making use of additional circuits and a clock for
synchronisation.
𝑍1 = 𝑃2 + 𝑃5 + 𝑃7
and
𝑍2 = 𝑃0 + 𝑃3 + 𝑃4 + 𝑃6
P0
P1
P2
P3 Word lines
P4
P5 Bit capacity = 8 x 2 = 16 bits. No of connections = 10
P6
P7
Z1 Z2
Output functions
𝑍1 = 𝑃2 + 𝑃5 + 𝑃7
and
𝑍2 = 𝑃0 + 𝑃3 + 𝑃4 + 𝑃6
Here the p-terms are first factorised with C as a prime factor to implement the 2D addressing technique
e.g.
𝑍1 = 𝐴̅𝐵𝐶̅ + 𝐴𝐵̅ 𝐶 + 𝐴𝐵𝐶
Similarly we note
𝑍2 = 𝐴̅𝐵̅ 𝐶̅ + 𝐴̅𝐵𝐶 + 𝐴𝐵̅ 𝐶̅ + 𝐴𝐵𝐶̅
𝐴̅𝐵̅
𝐴̅𝐵
ROM ( 16 bit capacity )
𝐴𝐵̅
𝐴𝐵
External i/ps 𝐶
𝐶̅
AND/OR Circuit
providing access to
C and 𝐶̅
Z1 Z2
Illustrative Example
Solution
I/O diagram
X
Logic
Z
Circuit
Clock
X : .. 0 1 1 1 0 1 1 0 1 0 1 1 0....
Z: 1 1 1
There are two models used in solving sequential circuits, referred to as the Moore and Mealy models or
machines. We shall use the Moore model.
𝑋̅
S0
AB
00 X 𝑋̅
X S1 X
01
𝑋̅
S2
11
𝑋̅ X
Z=1
10
S3
For the ROM design all possible transitions are programmed on the chip
Table 1. State table.
Realisation of circuit
𝐴̅𝐵̅
𝐴̅𝐵
ROM (4 x 4 bits)
𝐴𝐵̅
𝐴𝐵
X
𝑋̅
DA DB
Note:
X
16-bit
ROM Z Z = 𝐴𝐵̅
A A
B B AFF
Synch clock
BFF
PLAs offer optimal use of storage compared to ROMs in terms of the available addresses and what may be
required in a given design. Quite often only a small percentage of the available storage capacity in ROMS is
used.
PLAs consist of basically two separate ROMS, one being the AND ROM or logical product generator, and
the other the OR ROM or logical sum generator. This structure therefore lends itself to the PLA being
used as a function generator. Note that both arrays are programmable. The block schematic and
connection matrix for the implementation of two functions f1 and f2 are shown in the Figure.
I/Ps A
AND Logical Product Generator
ROM
B
P0 P3
f1 = P2+P3
OR
Logical Sum ROM
Generator f2 = P0 + P3
Fig. 9.10. Block schematic of simple PLA
Po P2 P3
A
AND ROM
f1
OR ROM
f2
We note that the number of vertical lines in the AND array indicates the number of AND or p-terms that
are generated for the design while the number of horizontal lines in the OR array indicates the number of
output functions required. Also the output functions are generated in the two-level SOP form and both
elementary and canonical terms can be generated by the PLA.
1 2 3 4
f1 = ABCD’EF’ + AEF’ + ACD + B’D’
5 6 4 7
f2 = ABE’F’ +AC’D’ + B’D’ + EF
8 9 10 11
f3 = ACDEF’ + ABC’D’ + A’C’D + ABD
12 13 4 14 7
f4 = ABC’D’E’ + A’EF’ + B’D’ + CD’ + EF
AND array
For six variable inputs and 14 product terms we obtain 6 x 2 x 14 = 168 bits
OR array
ROM design
Also for 4 o/p functions we obtain a total capacity of 26 x 4 = 256 bit storage capacity. This can be reduced
by using a multiplexed or 2D configuration of ROMs
Diode connections are available for both the variable and its complement. Programming entails either
blowing the fusible nichrome links or retaining them. Discuss printed diagrams.
Illustrative example
Design a hexadecimal counter using a PLA and D-type Flip flop for synchronisation. The output of the
counter is decoded to give a visual seven-segment decimal display.
Sequence Tables, State diagrams and Connection matrix of the design will be distributed
during the lecture.
Output equations for the inputs into the DFFs
𝐷𝐷 = 𝐶̅ 𝐷 + 𝐵̅ 𝐷 + 𝐴̅𝐷 + 𝐴𝐵𝐶𝐷
̅
𝐷𝐶 = 𝐴𝐵𝐶̅ + 𝐴̅𝐶 + 𝐵̅ 𝐶
𝐷𝐵 = 𝐴𝐵̅ + 𝐴̅𝐵
𝐷𝐴 = 𝐴̅
Pelly has just bought a new car and wanted to display its registration number electronically using seven segment displays
at night. Design a logic circuit using PLA and D-type flip flops for synchronisation to serially and cyclically display the
registration number shown below.
PELLY34
The segments of the LED are as shown below.
p
u q
v
t r
s
Letter to be displayed Energised segments
Y q-r-s-u-v
The other letters follow the arrangements of the segments to depict them. Neatly show the connection matrix and the
block schematic of the system.
Assignment
i. A synchronous counter is controlled by a signal A. If A = 0, the counter operates as a scale-of-four counter, and
if A = 1, the counter operates as a scale-of-eight counter.
a) Design the circuit (using any design method) and implement using 2 dimensional ROMs, and synchronising
D-type flip-flops.
b) Show the block schematic and connection matrix of the system.
c) Repeat part a using a PLA