FOURAH BAY COLLEGE

INSTITUTION
ELECTRICAL AND ELECTRONIC
DEPARTMENT ENGINEERING

DIGITAL SYSTEMS DESIGN

MODULE TITLE

EENG424
MODULE CODE
PROF JONAS A S REDWOOD-
MODULE LECTURER SAWYERR
Mobile : +232 76 670904, +232 88
001019, +232 25 273401
Email : jonas.redwood-
CONTACTS sawyerrd@usl.edu.sl,
osehsylrs1952@gmail.com,
jredwood_sawyerr@yahoo.com

3-0-3
LECTURE HOURS/LAB. PRACTICALS/CREDIT HOURS
ASSESSMENT Examination will account for 70% of the
overall grade whilst continuous
 assessment will account for 30%.
Question sets at the end of each lecture
must be returned for grading one week
after receipt of lectures and will account
for 10% of the continuous assessment
grade.
This module draws from a number of
concepts met in earlier years of the
programme and seeks to show how these
engineering tools can be used in digital
systems design. You may wish to revise
Modules in Digital Systems at Year IV so
as to better cope with the discussions as
OBJECTIVES AND OUTCOMES these concepts will be assumed during our
lectures.

References have been made to a number

of text books which are listed in the
section for Further Reading, and
modifications made for a coherent and
reader-friendly presentation with worked
examples and assignments provided.
MODULE DESCRIPTION
Below is a list of the topics to be covered.

 Review of Shift Register in digital

systems design and the Universal State
or DeBruign Diagram
  Design using PROMS and
Programmable Logic Arrays (PLAs)

References
1. http://
www.reliabilityeducation.com/
ReliabilityPredictionBasics.pdf
2. http://www.mtl-inst.com/
images/uploads/datasheets/
App_Notes/AN9030.pdf
3. http://en.wikipedia.org/wiki/
Failure_rate
4. G C Loveday,1989. Electronic
Testing and Fault Diagnosis.
SUGGESTED READINGREFERENCE
Longman Scientific &
TEXTS/MANUALS/WEBSITES Technical. ISBN 0-582-03865-
0
5. Holdsworth, B. Digital Logic
Design. Butterworth
Heineman. 1987. ISBN 0
7506 0501 4
6. Loveday, G C. Electronic
testing and Fault Diagnosis.
Longman Scientific &
Technical. 1992. ISBN 0-582-
03865-0

09– Design using programmable logic

LECTURE NUMBER devices (PLD)
 LECTURE DURATION (HOURS) 01
At the end of this lecture the students
should be able to :
1. Revise SR counters
SPECIFIC INSTRUCTIONAL OBJECTIVES AND 2. Identify and differentiate PLDs
LEARNING OUTCOMES 3. Design sequential circuits
using ROMS and PLAs
4. Solve numerical design
problems using PLDs

PART 3

Design using medium scale integration circuits

Revision of Shift register theory and the USD.

Use of shift registers and the Universal State Diagram (USD) or deBruign diagram

Fig. 9.1. Two state USD S1

 01
S0 S3

00
11
Lock-in Lock-in state on receipt of 11
state on receipt
00 10
S2

Fig. 9.2. Three variable USD S1 S3

001 011

S2

010

S0 000 111 Lock-in at S0

and S7
101 S7

S5
100 110

S4 S6

Refer to 4-state USD print-out

Design of sequential circuits using PLDs

Recap

What are PLDs?

PLDs are devices that are programmable such as ROMs, PLAs and PALs
These have similar basic building blocks but with different degrees of programmable characteristics.

Basic building blocks

AND OR
Array Array

Programming Characteristics

PLD AND OR
ROM Fixed (using Programmable
decoders)
Programmab Programmable Programmable
le Logic
Array (PLA)
Programmab Programmable Fixed
le Array
Logic (PAL)

(Class exercise – revision) Design example

A logic circuit having two inputs, produces an output which is the square of its inputs. Design the circuit
using a ROM showing the sequence table and the ROM connection matrix of the circuit.
Solution

Sequence Table
 Dec. A B W X Y Z
0 0 0 0 0 0 1
1 0 1 0 0 0 1
2 1 0 0 1 0 0
3 1 1 1 0 0 1

Here we note
Z = A’B + AB
Y=0
X = AB’
W = AB

ROM connection matrix

A 2 x 4 0 (A’B’)
Decoder 1 (A’B)
2 (AB’}
B 3 (AB)

WX Y Z

Design of sequential circuits using ROMS

ROMs can be used in the implementation of clock-driven sequential circuits because of their capability to
operate as function generators. The principles of logic design are used and the implementation draws from
knowledge of the architecture of ROMS. The two-dimensional ROM structure will be used in the
implementation of the sequential equations derived making use of additional circuits and a clock for
synchronisation.

Revision of ROMs as function generators

Consider the functions

Z1 =P 2+ P5 + P7
and
Z2 =P0 + P3+ P 4 + P6

Implement using the ID and 2D addressing format.

ABC
o/p of a
3 to 8
Decoder Bit lines

P0
P1
P2
P3 Word lines
P4
P5 Bit capacity = 8 x 2 = 16 bits. No of connections = 10
P6
P7

Z1 Z2

Output functions

Fig. 9.3. 1D sketch of a ROM

2D design
 Z1 =P 2+ P5 + P7
and
Z2 =P0 + P3+ P 4 + P6

Here the p-terms are first factorised with C as a prime factor to implement the 2D addressing technique
e.g.
Z1 =A B C+ A B C+ ABC

¿ C [ A B]+C [ A B+ AB]

Similarly we note
Z2 =A B C+ A BC + A B C+ AB C

¿ C [ A B+ A B+ AB]+ C[ A B ]

Fig. 9.4. A two dimensional ROM matrix

 AB
AB
ROM ( 16 bit capacity )
AB

AB

External i/ps C
C

AND/OR Circuit
providing access to
C and C

Z1 Z2

Illustrative Example

Consider the following sequential synchronous logic design

Serial binary data is received on line X of a logic circuit, in pulse form, each bit of the input data being
synchronised with an incoming clock pulse. An output Z=1 is generated when the sequence X = 1 0 1 is
detected including overlapping sequences. Design this circuit using ROMs and D-type flip-flops for
synchronisation.
Solution

I/O diagram

X Logic
Circuit Z

Clock

X : .. 0 1 1 1 0 1 1 0 1 0 1 1 0....

Z: 1 1 1

Fig. 9.5. I/O diagram

There are two models used in solving sequential circuits, referred to as the Moore and Mealy models or
machines. We shall use the Moore model.

The Moore machine solution.

Here the output is a function of the flip flop states only.

Fig. 9.6. Moore State diagram

AB
00 X X

X X
01
X

11
X X

10
S3

Here we note that Z=A B

Sequence Table using the Moore machine

For the ROM design all possible transitions are programmed on the chip
Table 1. State table.

Present state Next state Output word Comments

A B X A B DA DB Z
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 1 1 1 0
0 1 1 0 1 0 1 0
Unused 1 0 0 1 1 1 1 0 Stays at S3 unless
states 1 0 1 0 0 0 0 0 receipt of X’
when it moves to
S0
1 1 0 0 0 0 0 0
1 1 1 1 0 1 0 1

Output equations for the design implementation

D A =A B X + A B X + ABX

DB = A B X + A B X + A B X + A B X= X [ A B+ A B ] + X [ A B+ A B]

Realisation of circuit
 AB
AB
ROM (4 x 4 bits)
AB

AB

X
X

DA DB

Fig. 9.8. Connection matrix for the sequence detector

Note:

D A =A B X + A B X + ABX

DB = A B X + A B X + A B X + A B X= X [ A B+ A B ] + X [ A B+ A B]
 X
Z Z= AB
A A
B B AFF

Synch clock

BFF

Fig. 9.9. Block schematic of the ROM implementation

NB
i. ROMs do not have clock facilities
ii. The A & B outputs from the ROM, i.e. the output word determined by DA and DB are fed back into
the ROM as the Next states on receipt of the clock pulse through the use of synchronising D-type Flip
Flops.
 iii. It is assumed that the ROM has an internal decoder
iv. Additional logic is provided to generate the output Z with its clock input synchronising pulse.

Design of sequential circuits using PLAs

PLAs offer optimal use of storage compared to ROMs in terms of the available addresses and what may be
required in a given design. Quite often only a small percentage of the available storage capacity in ROMS is
used.
PLAs consist of basically two separate ROMS, one being the AND ROM or logical product generator, and
the other the OR ROM or logical sum generator. This structure therefore lends itself to the PLA being used
as a function generator. Note that both arrays are programmable. The block schematic and connection
matrix for the implementation of two functions f1 and f2 are shown in the Figure.

I/Ps A
AND
ROM
Logical Product Generator
B

P0 P3

OR f1 = P2+P3
Logical Sum ROM
Generator f2 = P 0 + P 3
Fig. 9.10. Block schematic of simple PLA

Po P2 P3
A

AND ROM

f1
OR ROM
f2

Fig. Connection matrix of the PLA Implementation

We note that the number of vertical lines in the AND array indicates the number of AND or p-terms that are
generated for the design while the number of horizontal lines in the OR array indicates the number of output
functions required. Also the output functions are generated in the two-level SOP form and both elementary
and canonical terms can be generated by the PLA.

Refer to diode-resistor logic representing the AND and OR arrays of a PLA

Illustrative example. Use of a PLA as a function generator

Let us consider four six-variable functions as given below

f1 = ABCD’EF’ + AEF’ + ACD + B’D’

f2 = ABE’F’ +AC’D’ + B’D’ + EF

f3 = ACDEF’ + ABC’D’ + A’C’D + ABD

f4 = ABC’D’E’ + A’EF’ + B’D’ + CD’ + EF

Discuss reduction of connections by identifying common p-terms

See implementation print-out.

Memory comparison between ROM and PLA design

PLA design

AND array

For six variable inputs and 14 product terms we obtain 6 x 2 x 14 = 168 bits

OR array
For 4 o/p functions and 14 product terms we obtain 4 x 14 = 56 bits
Total capacity = 168 + 56 = 224 bits

ROM design

Here for a 6 variable input we require 26 bit locations using a 1D structure.

Also for 4 o/p functions we obtain a total capacity of 26 x 4 = 256 bit storage capacity. This can be reduced
by using a multiplexed or 2D configuration of ROMs

Field programmable PLAs (FPLAs)

Diode connections are available for both the variable and its complement. Programming entails either
blowing the fusible nichrome links or retaining them. Discuss printed diagrams.

Illustrative example

Design a hexadecimal counter using a PLA and D-type Flip flop for synchronisation. The output of the
counter is decoded to give a visual seven-segment decimal display.

Sequence Tables, State diagrams and Connection matrix of the design will be distributed during the
lecture.

Output equations for the inputs into the DFFs

D D=C D+ B D+ A D+ ABC D

D C = AB C+ A C+ B C

DB = A B+ A B
 D A =A

MODE AND DEADLINE FOR SUBMISSION OF ASSIGNMENT Not applicable