Final Report (2) - 1

Chapter 1
INTRODUCTION
1.1. General:
Multilevel inverters (MLI) have become preferred alternative in high and medium power
applications. MLI offers more levels at the output phase voltage which results in several
advantages over conventional 2-level Multi level inverters (MLI) have become preferred
alternative in high and medium power applications. MLI offers more levels at the output phase
voltage which results in several advantages over conventional 2-level inverter. Some of them are
reduced dv/dt in the phase voltage, reduced switching frequency, reduced EMI, improved
current and voltage THD, etc. A high voltage MLI can be realized by using easily available low
voltage devices which are of low cost. Due to reduced device stress and reduced switching
frequency, switching losses are reduced.
Multilevel converters are finding increased attention in industry and academia as one of
the preferred choices of electronic power conversion for high-power applications. They have
successfully made their way into the industry and therefore can be considered a mature and
proven technology. Currently, they are commercialized in standard and customized products that
power a wide range of applications, such as compressors, extruders, pumps, fans, grinding mills,
rolling mills, conveyors, crushers, blast furnace blowers, gas turbine starters, mixers, mine hoists,
reactive power compensation, marine propulsion, high-voltage direct-current (HVDC)
transmission, hydro pumped storage, wind energy conversion, and railway traction, to name a
few. Although it is an enabling and already proven technology, multilevel converters present a
great deal of challenges, and even more importantly, they offer such a wide range of possibilities
that their research and development is still growing in depth and width. Researchers all over the
world are contributing to further improve energy efficiency, reliability, power density, simplicity,
A SEVEN-LEVEL INVERTER USING LOW VOLTAGE DEVICES AND OPERRATION WITH SINGLE DC-LINK 1
and cost of multilevel converters, and broaden their application field as they become more
attractive and competitive than classic topologies.
Recently, many publications have addressed multilevel converter technology and

stressed the growing importance of multilevel converters for high-power applications [4]–[9].
These works have a survey and tutorial nature and cover in depth traditional and well-established
multilevel converter topologies, such as the neutral point clamped (NPC), cascaded H-bridge
(CHB), and flying capacitor (FC), as well as the most used modulation methods. Instead, this
paper presents a technology review, which is focused mainly on the most recent advances made
in this field in the past few years, covering new promising topologies, modulations, controls, and
operational issues. In addition, one of the most interesting topics in multilevel converter
technology is the rapidly increasing and diverse application field, which is addressed in this work
as well. In addition, emerging trends, challenges, and possible future directions of the
development in multilevel converter technology are out lined to motivate further work in this
field.
1.2. Aim of Project:

A Seven–level inverter using low voltage device and operation with single DC-link
1.3. Problem Formulation:

1.3.1. Existing systems:
This topology uses less number of switches as compared with conventional
topology, where it reduces the complexity and overall size of the system which in turn reduces
the harmonics and cost of the entire system. It is a hybrid topology formed by cascading a 5-
level ANPC with a 3-level T-type converter. It is obtained using low voltage semiconductor
devices with voltage blocking capability. The topology uses three floating capacitors per
phase which are balanced within a PWM switching duration using switching state
redundancies for each pole voltage level. Topology forms two stacks at the front-end which
requires individual symmetrical DC source. The switching loss and conduction loss analysis is
performed and compared with some of the existing 7-level multilevel level inverters (MLI).
Further, the single DC source operation with two stacked capacitors and closed loop control
of neutral point voltage using symmetrical 6-phase induction motor is proposed.
1.3.2 Problems in Existing System:
 This topology required more number of components compared to conventional topology.
 It required higher number of semiconductor switches.
 Does not have self - balancing property.
 Required bulky and costly isolated transformers for each cell (In power conversion).
 It will have worse power quality.
 Also the complex control method to balance the voltage of dc-link capacitor.
1.3.3 Proposed System:

So, in view of all the above problems with traditional approaches we came here
7-level inverter topology for induction motor drives. It is a hybrid topology formed by
cascading a 5-level ANPC with a 3-level T-type converter. It is obtained using low voltage
semiconductor devices with voltage blocking capability. The topology uses three floating
capacitors per phase which are balanced within a PWM switching duration using switching
state redundancies for each pole voltage level. The switching loss and conduction loss analysis
is performed and compared with some of the existing 7-level multilevel level inverters (MLI)
reported in various literatures to show the advantages of proposed topology. Further, the
single DC source operation with two stacked capacitors and closed loop control of neutral
point voltage using symmetrical 6-phase induction motor is proposed.
1.4. Objectives of Project:
 The main objective of this project is to obtain the simple hybrid modulation method
(fundamental frequency switching for high - voltage device + phase -shifted PWM for the
flying- capacitor cells ) can be applied reducing the switching losses and achieving natural
balancing of floating of floating voltages with superior harmonic performance.
 Increasing the power rating by minimizing switching frequency while still maintaining
reasonable power quality is an important requirement and a persistent challenge for the
industry.
 It is a simple topology structure formed by the connection of an active NPC + flying capacitor
cells per phase, easily extendable to achive a large number of output voltage levels.
1.5. Limitations:
 Maintenance cost is more.
 Cost of system is more.
 Requires greater technical skill to install and set up.
1.6. Layout of Project:

 Chapter 1: This chapter includes introduction and background of the thesis. It also relates with
aim of project, objectives of project, limitations and contribution in this research. This chapter is
finishes with layout of thesis.
 Chapter 2: This chapter gives overview of seven-level inverter using low voltage device
operation with single Dc-Link.
 Chapter 3: This chapter deals with system description and working of system.
 Chapter 4: In this chapter detail calculation.
 Chapter 5: This chapter deals simulated results with different modulation methods.
 Chapter 6: This chapter includes development of prototype hardware.
Chapter 2
LITERATURE SURVEY
2.1. Literature review
Samir Kouro, Mariusz Malinowski, K. Gopakumar, This paper first presents

a brief overview of well-established multilevel converters strongly oriented to their current
state in industrial applications to then center the discussion on the new converters that have
made their way into the industry. In addition, new promising topologies are discussed.
Recent advances made in modulation and control of multilevel converters are also
addressed. A great part of this paper is devoted to show nontraditional applications
powered by multilevel converters and how multilevel converters are becoming an enabling
technology in many industrial sectors [1].
Jose I. L eon, sergio Vazquez, L eopoldo g. Franquelo, In the last decades,

multilevel converters have been developed usually for medium-voltage high-power
applications. They have become a mature solution for the increasing power demand of
multiple applications such as renewable energy system, power quality improvement, and
motor drives. In this paper, the operation of multilevel converters is addressed focusing on
control and modulation techniques for different well known applications [2].
Haitham Abu-Rub, Joachim Holtz, Jose Rodriguez , This paper gives an

overview of medium-voltage (MV) multilevel converters with a focus on achieving minimum
harmonic distortion and high efficiency at low switching frequency operation. Increasing the
power rating by minimizing switching frequency while still maintaining reasonable power
quality is an important requirement and a persistent challenge for the industry. [ 3 ].
Mario Schweizer, Johann W. Kolar, The demand for light weight converters
with high control performance and low acoustic noise led to an increase in switching
frequencies of hard switched two-level low-voltage 3-phase converters over the last years. For
high switching frequencies, converter efficiency suffers and can be kept high only by
employing cost intensive switch technology such as Si C diodes or Cool MOS switches there
for, conventional IGBT technology still prevails In this paper, the alternative of using three-level
converters for low voltage applications is addressed [ 4 ].
T. Bruckner. S. Bernet This paper investigates the use of active neutral point
clamp switches in the three-level NPC voltage source inverter to balance the losses among
the semiconductors. Both control structure and algorithm are proposed which enable a
substantially increased output power of the inverter and an improved performance at zero
speed.[ 5 ].
Peter Barbosal, Peter Steimer, Jorgen Steinke, Manfred Winkehn

kemperl this paper proposes a multilevel power conversion concept based on the
combination of neutral-point-clamped (NPC) and floating capacitor converters. In the
proposed scheme, the voltage balancing across the floating capacitors is achieved by using
a proper selection of redundant switching states, and the neutral-point voltage is controlled
by the classical de offset injection. Experimental results are illustrated in the paper to
demonstrate the system operation.[ 6 ]
Weihui. Sheng, Qiongxuan. Ge, Traditional seven-level Active Neutral-point-

clamped (ANPC-7L) converters suffer from the problems of dynamic voltage balancing in
series switches and multi levels voltage jumping of phase output voltage during switching
states transition. This paper presents a novel ANPC-7L topology with auxiliary commutating
branches and elaborates on its commutating strategies. The presented topology and its
commutating strategies resolve the two problems mentioned above completely. The validity
of the presented topology and its commutating strategies are verified by experimental
results from a 380 V/5 kW ANPC-7L converter [ 7 ].
P. Roshankumar, P.P.Raj evan,K.Mathew, In this paper, a new three-phase,
five-level inverter topology with a single-dc source is presented. The proposed topology is
obtained by cascading a three-level flying capacitor inverter with a flying H-bridge power
cell in each phase. This topology has redundant switching states for generating different
pole voltages. By selecting appropriate switching states, the capacitor voltages can be
balanced instantaneously (as compared to the fundamental) in any direction of the current,
irrespective of the load power factor. Another important feature of this topology is that if
any H-bridge fails, it can be bypassed and the configuration can still operate as a three-level
inverter at its full power rating. [ 8 ].
Mariusz Malinowski, K. Gopakumar, Cascaded multilevel inverters synthesize a

medium voltage output based on a series connection of power cells which use standard
low-voltage component configurations. This characteristic allows one to achieve high-quality
output voltages and input currents and also outstanding availability due to their intrinsic
component redundancy. Due to these features, the cascaded multilevel inverter has been
recognized as an important alternative in the medium-voltage inverter market [ 9 ].
Maryam Saeedifard, Peter Mantovanelli Barbosa , This paper introduces a novel

hybrid seven-level converter that is based on the upgrade of the five-level active neutral
point-clamped converter concept and is suitable for high-power applications. The paper
provides a comprehensive analysis for the operation of the converter. Based on the analysis,
a space vector modulation (SVM)-based switching strategy that takes advantage of
redundant switching vectors of the SVM strategy to counteract the voltage drift
phenomenon of the proposed converter is proposed. The limit to the range of operation of
the seven-level converter based on the proposed SVM strategy is also presented. It is shown
that the ability to stabilize the dc-link capacitor voltages and the per-phase flying capacitors
is a function of the converter operating indicate ie the load power factor and modulation
index [ 10 ].
Hao Tian, Yuzhuo Li, This paper proposes a novel seven-level (7L) hybrid-
clamped converter, which has competitive performance and lower device count compared
to existing topologies. It can easily balance the floating capacitor voltage at the switching
frequency, and therefore ensure low capacitor voltage ripples even under very low
fundamental frequencies. Both multi-pulse diode front end and active front end structures
can be used with the proposed 7L converter, where the 7L active front end has the ability to
balance the DC link capacitors [ 11 ].
Josep Pou, Rafael Pindado, Dushan Boroyevich , The nearest vectors to the
reference vector are commonly used in space-vector modulation (SVM) strategies. The main
advantages of these modulation strategies are the low switching frequencies of the devices,
the good output voltage spectra, and the low electromagnetic interference. However, when
these techniques are applied to the three-level neutral-point (NP)-clamped inverter, low-
frequency oscillations appear in the NP voltage for some operating conditions [ 12 ].
Josep Pou, Rafael Pindado, Dushan Boroyevich , This paper explores the
limits of neutral-point current control in back-to-back connected three-level converters. The
theoretical analysis used is based on a mathematical neutral-point current model, which can
be extended to apply to converters with higher numbers of levels. The low-frequency ripple,
which appears in the neutral-point voltage for some operation conditions, can be removed
for an extended operating area when two converters are connected back to back to the
same dc bus[ 13 ].
Iraide López, Salvador Ceballos, Josep Pou, Jordi Zaragoza , This paper
presents a generalized PWM-based control algorithm for multiphase neutral-point-clamped
(NPC) converters. The proposed algorithm provides a zero-sequence to be added to the
reference voltages that contributes to improve the performance of the converter by: i)
regulating the neutral point (NP) current to eliminate/attenuate the low-frequency NP
voltage ripples, ii) reducing the switching losses of the power semiconductors and iii)
maximizing the range of modulation indices for linear operation mode. The control method
is formulated following a carrier-based PWM approach [ 14 ].
Apurv Kumar Yadav, K. Gopakumar, Krishna Raj R, This paper proposes a

novel method for instantaneous balancing of neutral point voltages with stacked multilevel
inverters (MLI) for variable speed drives. The stacked MLI uses series connected DC sources
and neutral points (connecting points of DC sources) to obtain the desired levels. The
balancing of neutral point (NP) voltages are obtained by using low voltage capacitor fed
cascaded H-bridge (CHB) per phase of symmetrical 6-phase induction machine (IM), which
ensures zero current drawn from NP (at any given instant). Since no current is drawn from
NPs, the single DC-link operation with stacked capacitors is also possible. The scheme is
suitable for applications where low voltage DC sources and batteries are stacked to form
DC-link [ 15 ].
Viju Nair R, Arun Rahul S, Sumit Pramanick, This paper proposes a novel
6-phase stacked multilevel inverter drive with only one DC source for a 6-phase IM with
symmetrically placed windings (600 apart). Using one DC source allows direct ac to ac
conversion and the inverter can feed the power back to the grid at any power factor. This
paper presents a systematic approach to use one DC source for the 6phase stacked
multilevel inverter fed symmetric IM drive. Here the individual DC supply is realised by series
connected (split) capacitors with inherent balancing of the neutral point (DC link capacitor
midpoint) current within a switching cycle [ 16 ].
Kaibalya Prasad Panda, Prabhat Ranjan Bana , Switched-capacitor based

multilevel inverters (SC MLIs) have received a great deal of interest that reduces the dc
source requirement and improves the power quality. However, multiple dc sources and
requirement of a large number of switches to generate a high-quality boost output are the
fundamental issues in the SC MLIs. This paper presents a step up 17-level SC MLI using
reduced number of switches, three capacitors and a single dc source. The steady-state
voltage across the capacitors is maintained in the ratio 1:2:0.5 that contributes to quadruple
boosting ability without using any auxiliary capacitor voltage balancing circuit. Besides, lower
switch count in the conduction path and operation of 50 % of the switches at fundamental
frequency ensures total power loss reduction in the proposed circuit [ 17 ].
Sandeep. N, Udaykumar R Yaragatti, This paper proposes a new nine-level

(9L) inverter for medium and high-power applications. The proposed topology comprises of
a three-level (3L) active neutral-point-clamped (ANPC) inverter connected in series with a
floating capacitor (FC) fed H-bridge. Besides, two additional switches operating at line
frequency are appended across the dc-link of the 3L ANPC structure. Compared to
conventional hybrid cascaded inverters, the primary advantage of this addition is doubling of
the resulting RMS output voltage. This amelioration is achieved while preserving the
standard 3L ANPC and H-bridge structures with minimum topological modification. A simple
logic-gate based (LGB) voltage balancing scheme is developed to regulate the FC voltage.
The proposed voltage balancing method is independent of load power factor, inverter
modulation index and can balance the voltage across FC instantaneously [ 18 ].
Annette von Jouanne,Haoran Zhang, This paper presents a dual-bridge

inverter approach to eliminate the motor common-mode voltage and resulting bearing and
leakage currents. The novel dual-bridge inverter is controlled to generate balanced
excitation of the induction motor under pulse width modulation (PWM) inverter operation.
Theoretical analysis, simulation results, and experimental results are presented to verify this
concept [ 19 ].
Di Han, Woongkul Lee, Silong Li, This paper introduces a new concept of
common mode voltage cancellation for pulse width modulated motor drives, aiming at
solving issues such as ground leakage current, common mode electromagnetic interference,
and bearing current. The balanced inverter topology and dual-winding stator configuration
is proposed as a practical realization. Implementation considerations on the influence of
circuit asymmetry are also investigated. Finally, a GANHEMT based induction motor drive
prototype is built and tested to evaluate the performance of the cancellation concept in a
practical situation [ 20 ].
Rahul Kanchan, M.R. Baiju, K. Gopakumar, A pulse width modulation

(PWM) scheme for multilevel inverters is proposed. The proposed PWM scheme generates
the inverter leg switching times, from the sampled reference phase voltage amplitudes and
centre the switching times for the middle vectors, in a sampling interval, as in the case of
conventional space vector PWM (SVPWM). The SVPWM scheme, presented for multilevel
inverters, can also work in the over modulation range, using only the sampled amplitudes of
reference phase voltages. The present PWM technique does not involve any sector
identification and considerably reduces the computation time when compared to the
conventional space vector PWM technique. The present PWM signal generation scheme can
be used for any multilevel inverter configuration. A five-level inverter configuration, using an
open ended winding induction motor drive, is used to verify the SVPWM generation scheme
experimentally [ 21 ].
2.2. Summary of Literature Review:
2.2.1. Recent Advances and Industrial Applications of Multilevel Converters

Recent Advances and Industrial Applications of Multilevel
Title Converters
Samir Kouro, Member, IEEE, Mariusz Malinowski, Senior Member,

Name Of Author
IEEE, K. Gopakumar, Senior Member, IEEE
Year of Publishing 2010
Publisher IEEE
Multilevel converters have been under research and development

for more than three decades and have found successful industrial
application. However, this is still a technology under development,
and many new contributions and new commercial topologies
Details have been reported in the last few years. The aim of this paper is
to group and review these recent contributions, in order to
establish the current state of the art and trends of the technology,
to provide readers with a comprehensive and insightful review of
where multilevel converter technology stands and is heading. This
paper
first presents a brief overview of well-established multilevel
converters strongly oriented to their current state in industrial
applications to then center the discussion on the new converters
that have made their way into the industry.
2.2.2. Multilevel Converters: Control and Modulation Techniques for Their Operation and
Industrial Applications
Multilevel Converters: Control and Modulation Techniques for
Title
Their Operation and Industrial Applications
Name Of Author C.Thulasi yammal and S Sutha
Publisher IEEE
In the last decades, multilevel converters have been developed
usually for medium-voltage high-power applications. They have
become a mature solution for the increasing power demand of
multiple applications such as renewable energy systems, power
quality improvement, and motor drives. In this paper, the
Details
operation of multilevel converters is addressed focusing on control
and modulation techniques for different well known applications.
The new developments are presented as an extension of
conventional methods for two-level voltage-source converters
which are still the mainstream solution for most cases.
2.2.3. Medium-Voltage Multilevel Converters—State of the Art, Challenges, and Requirements in

Industrial Applications
Medium-Voltage Multilevel Converters—State of the Art,
Title Challenges, and Requirements in Industrial Applications
Name Of Author Bolivar Alvarez, Alberto S´anchez and Omar Aguirre
Publisher IEEE
This paper gives an overview of medium-voltage (MV) multilevel
converters with a focus on achieving minimum harmonic
distortion and high efficiency at low switching frequency
operation. Increasing the power rating by minimizing switching
frequency while still maintaining reasonable power quality is an
important requirement and a persistent challenge for the
industry. Existing solutions are discussed and analyzed based on
Details their topologies, limitations, and control techniques. As a

preferred option for future research and application, an inverter
configuration based on three-level building blocks to generate
five-level voltage waveforms is suggested. This paper shows that
such an inverter
may be operated at a very low switching frequency to achieve
minimum ON-state and dynamic device losses for highly efficient
MV drive applications while maintaining low harmonic distortion.
2.2.4. Design and Implementation of a Highly Efficient Three-Level T-Type
Converter for Low-Voltage Applications
Design and Implementation of a Highly Efficient Three-Level T-

Title
Type Converter for Low-Voltage Applications
Mario Schweizer, Student Member, IEEE, and Johann W. Kolar,

Name Of Author
Fellow, IEEE
Publisher IEEE
The demand for lightweight converters with high control
Details performance and low acoustic noise led to an increase in switching
frequencies of hard switched two-level low-voltage 3-phase
Converters over the last years. For high switching frequencies,
converter efficiency suffers and can be kept high only by employing
cost intensive switch technology such as SiC diodes or Coo lMOS
switches therefore, conventional IGBT technology still prevails. In
this paper, the alternative of using three-level converters for low
voltage applications is addressed.
2.2.5. Loss Balancing in Three-Level Voltage Source Inverters applying Active NPC
Switches
Loss Balancing in Three-Level Voltage Source Inverters applying
Title
Active NPC Switches
Name Of Author T. Bruckner, S. Bernet
Publisher IEEE
This paper investigates the use of active neutral point clamp
switches in the three-level NPC voltage source inverter to balance
the loss amoung the semiconductor both control structure and
Details algoritham are proposed which enable a substantially increased
output power of the inverter and improved performance at zero
speed
2.2.6. Active-Neutral-Point-Clamped (ANPC) Multilevel Converter Technology
Active-Neutral-Point-Clamped (ANPC) Multilevel Converter

Title
Technology
Peter Barbosal, Peter Steimer2, Jorgen Steinke2, Manfred
Name Of Author
Winkehnkemperl, and Nikola Celanovic'
Publisher IEEE
This paper proposes a multilevel power conversion concept based
on the combination of neutral-point-clamped (NPC) and floating
capacitor converters. In the proposed scheme, the voltage
balancing across the floating capacitors is achieved by using a
Details
proper selection of redundant switching states, and the neutral-
point voltage is controlled by the classical de offset injection.
Experimental results are illustrated in the paper to demonstrate the
system operation.
2.2.7. A Novel Seven-level ANPC Converter Topology and Its Commutating Strategies
A Novel Seven-level ANPC Converter Topology and Its

Title
Commutating Strategies
Name Of Author Weihui. Sheng, Member, IEEE, and Qiongxuan. Ge, Member, IEEE
Publisher IEEE
Traditional seven-level Active Neutral-point-clamped (ANPC-7L)
converters suffer from the problems of dynamic voltage balancing
in series switches and multi levels voltage jumping of phase output
voltage during switching states transition. This paper presents a
novel ANPC-7L topology with auxiliary commutating branches and
elaborates on its commutating strategies. The presented topology
Details
and its commutating strategies resolve the two problems
mentioned above completely. The validity of the presented
topology and its commutating strategies are verified by
experimental results from a 380 V/5 kW ANPC-7L
converter
2.2.8. A Five-Level Inverter Topology with Single-DC Supply by Cascading a Flying
Capacitor Inverter and an H-Bridge
A Five-Level Inverter Topology with Single-DC

Title
Supply by Cascading a Flying Capacitor Inverter and an H-Bridge
P. Roshankumar, Student Member, IEEE, P. P. Rajeevan, K.Mathew,

Name Of Author Student Member, IEEE, K. Gopakumar, Fellow, IEEE,
Publisher IEEE
In this paper, a new three-phase, five-level inverter topology with a
single-dc source is presented. The proposed topology is obtained
by cascading a three-level flying capacitor inverter with a flying H-
bridge power cell in each phase. This topology has redundant
switching states for generating different pole voltages. By selecting
appropriate switching states, the capacitor voltages can be
Details
balanced instantaneously (as compared to the fundamental) in any
direction of the current, irrespective of the load power factor.
Another important feature of this topology is that if any H-bridge
fails, it can be bypassed and the configuration can still operate as a
three-level inverter at its full power rating.
2.2.9. A Survey on Cascaded Multilevel Inverters
Title A Survey on Cascaded Multilevel Inverters

Mariusz Malinowski, Senior Member, IEEE, K. Gopakumar, Senior
Name Of Author
Member, IEEE,
Publisher IEEE
Details Cascaded multilevel inverters synthesize a medium voltage output

based on a series connection of power cells which allows one to
achieve high-quality output voltages and input currents and also
outstanding availability due to their intrinsic component
redundancy. Due to these features, the cascaded
multilevel inverter has been recognized as an important alternative
in the medium-voltage inverter market. This paper presents a
survey of different topologies, control strategies and modulation
techniques used by these inverters. Regenerative and advanced
topologies are also discussed. Applications where the mentioned
features play a key role are shown. Finally, future developments are
addressed
2.2.10. Operation and Control of a Hybrid Seven-Level Converter

Operation and Control of a Hybrid Seven-Level Converter
Title
Maryam Saeedifard, Senior Member, IEEE, Peter Mantovanelli

Name Of Author
Barbosa, Senior Member, IEEE
Publisher IEEE Journal

Details This paper introduces a novel hybrid seven-level converter
that is based on the upgrade of the five-level active neutralpoint-
clamped converter concept and is suitable for high-power
applications. The paper provides a comprehensive analysis for the
operation of the converter. Based on the analysis, a space vector
modulation (SVM)-based switching strategy that takes advantage
of redundant switching vectors of the SVM strategy to counteract
the voltage drift phenomenon of the proposed converter is
proposed. The limit to the range of operation of the seven-level
converter based on the proposed SVM strategy is also presented.
It is shown that the ability to stabilize the dc-link capacitor voltages
and the per-phase flying capacitors is a function of the converter
operating indices, i.e., the load power factor and modulation index
.
2.2.11. A Novel Seven-Level Hybrid-Clamped (HC) Topology for Medium Voltage

Motor Drives
A Novel Seven-Level Hybrid-Clamped (HC) Topology for Medium

Title
Voltage Motor Drives
Name Of Author Hao Tian, Student Member, IEEE, Yuzhuo Li, Student Member, IEEE,
Publisher IEEE
This paper proposes a novel seven-level (7L) hybrid-clamped

converter, which has competitive performance and lower device
count compared to existing topologies. It can easily balance the
floating capacitor voltage at the switching frequency, and therefore
ensure low capacitor voltage ripples even under very low
Details
fundamental frequencies. Both multi-pulse diode front end and
active front end structures can be used with the proposed 7L
converter, where the 7L active front end has the ability to balance
the DC link capacitors.
2.2.12. Evaluation of the Low-Frequency Neutral-Point Voltage Oscillations in the Three-

Level Inverter
Evaluation of the Low-Frequency Neutral-Point Voltage Oscillations
Title
in the Three-Level Inverter
Josep Pou, Member, IEEE, Rafael Pindado, Member, IEEE, Dushan
Name Of Author
Boroyevich, Senior Member, IEEE,
Publisher IEEE
The nearest vectors to the reference vector are commonly

Details used in space-vector modulation (SVM) strategies. The
main advantages of these modulation strategies are the low

switching frequencies of the devices, the good output voltage
spectra, and the low electromagnetic interference. However, when
these techniques are applied to the three-level neutral-point (NP)-
clamped inverter, low-frequency oscillations appear in the NP
voltage for some operating conditions. As a result, the value of the
dc-link capacitors must be increased in order to attenuate such
oscillations. In this paper, these amplitudes are quantified for two
modulation strategies that use nearest vectors to the reference
vector. Owing to the non dimensional variables used in the analysis,
the information provided will help for the calculation of the dc-link
capacitors in a given specific application. Simulated and
experimental examples
are presented
2.2.13. Limits of the Neutral-Point Balance in Back-to-Back-Connected Three-Level

Converters
Limits of the Neutral-Point Balance in Back-to-Back-Connected
Title
Three-Level Converters
Josep Pou, Member, IEEE, Rafael Pindado, Member, IEEE, Dushan
Name Of Author
Boroyevich, Member, IEEE,
Publisher IEEE
This paper explores the limits of neutral-point current

control in back-to-back connected three-level converters. The
Details theoretical analysis used is based on a mathematical neutral-point
current model, which can be extended to apply to converters with
higher numbers of levels. The low-frequency ripple, which appears
in the neutral-point voltage for some operation conditions, can be
removed for an extended operating area when two converters are

connected back to back to the same dc bus. As a consequence, a
lower voltage is applied to the devices, and the value of the
capacitors can also be significantly reduced. Some practical
graphics are given to represent the design according to the
specifications of the application.
2.2.14. Generalized PWM-Based Method for Multiphase Neutral-Point-Clamped
Converters with Capacitor Voltage Balance Capability
Generalized PWM-Based Method for Multiphase

Title Neutral-Point-Clamped Converters with Capacitor Voltage Balance
Capability
Iraide López, Salvador Ceballos, Josep Pou, Senior Member, IEEE,
Name Of Author
Jordi Zaragoza, Member, IEEE,
Publisher IEEE
This paper presents a generalized PWM-based control algorithm

for multiphase neutral-point-clamped (NPC) converters. The
proposed algorithm provides a zero-sequence to be added to the
reference voltages that contributes to improve the performance of
the converter by regulating the neutral point(NP) current to
eliminate/attenuate the low-frequency NP voltage ripples, ii)
Details reducing the switching losses of the power
semiconductors and iii) maximizing the range of modulation indices
for linear operation mode. The control method is formulated
following a carrier-based PWM approach. Hence, dealing with
complex space-vector diagrams to solve the modulation problem
for multiphase converters is avoided.
2.2.15. Instantaneous Balancing of Neutral Point Voltages for Stacked DC-link

Capacitors Of Multilevel Inverter for Dual Inverter fed Induction Motor Drives
Instantaneous Balancing of Neutral Point
Title Voltages for Stacked DC-link Capacitors of Multilevel Inverter for
Dual Inverter fed Induction Motor Drives
Apurv Kumar Yadav, Student Member, IEEE, K. Gopalkumar,
Name Of Author Fellow, IEEE, Krishna Raj R, Student Member,
IEEE,
Publisher IEEE
This paper proposes a novel method for instantaneous

balancing of neutral point voltages with stacked multilevel
inverters (MLI) for variable speed drives. The stacked MLI uses
series connected DC sources and neutral points (connecting points
of DC sources) to obtain the desired levels. The balancing of
neutral point (NP) voltages are obtained by using low voltage
capacitor fed cascaded H-bridge (CHB) per phase of symmetrical
6-phase induction machine (IM), which ensures zero current
Details
drawn from NP (at any given instant). Since no current is drawn
from NPs, the single DC-link operation with stacked capacitors
is also possible. The scheme is suitable for applications where low
voltage DC sources and batteries are stacked to form DC-link. A
variable speed operation is done using 7-level inverter scheme
for symmetrical 6-phase IM, which is formed by three DC link
stacked capacitors cascaded with two low voltage capacitor
fed CHBs per phase.
2.2.16. Novel Symmetric 6-Phase Induction Motor Drive Using Stacked Multilevel
Inverters with a Single DC Link and Neutral Point Voltage Balancing
Novel Symmetric 6-Phase Induction Motor Drive
Title Using Stacked Multilevel Inverters with a Single DC Link and Neutral
Point Voltage Balancing
Viju Nair R, Student Member, IEEE, Arun Rahul S, Sumit Pramanick,
Name Of Author
Student Member, IEEE,
Publisher IEEE
This paper proposes a novel 6-phase stacked multilevel inverter drive

with only one DC source for a 6-phase IM with symmetrically placed
windings (600 apart). Using one DC source allows direct ac to ac
conversion and the inverter can feed the power back to the grid at
any power factor. This paper presents a systematic approach to use
one DC source for the 6- phase stacked multilevel inverter fed
symmetric IM drive. Here the individual DC supply is realised by
Details
series connected (split) capacitors with inherent balancing of the
neutral point (DC link capacitor mid point) current within a switching
cycle. This also helps in reducing the DC link capacitor size. To verify
the concept experimentally, a 6-phase stacked nine level inverter is
developed in the laboratory for a symmetric 6-phase IM and it is run
with V/f control. Detailed experimental results are presented to
validate the concept.
2.2.17. A Single-Source Switched-Capacitor Based Step-Up Multilevel Inverter with
Reduced Components
Single-Source Switched-Capacitor Based Step-UpMultilevel

Title Inverter with Reduced Components
Kaibalya Prasad Panda, Student Member, IEEE, Prabhat Ranjan

Name Of Author
Bana, Student Member, IEEE,
Publisher IEEE
Switched-capacitor based multilevel inverters (SC MLIs) have

received a great deal of interest that reduces the dc source
requirement and improves the power quality. However,
multiple dc sources and requirement of a large number of
switches to generate a high-quality boost output are the
Details fundamental issues in the SC MLIs. This paper presents a step
up 17-level SC MLI using reduced number of switches, three
capacitors and a single dc source. The steady-state voltage
across the capacitors is maintained in the ratio 1:2:0.5 that
contributes to quadruple boosting ability without using any
auxiliary capacitor voltage balancing circuit..
2.2.18. Operation and Control of an Improved Hybrid Nine-Level Inverter
Title Operation and Control of an Improved Hybrid Nine-Level Inverter
Sandeep. N, Student Member, IEEE and Udaykumar R Yaragatti,
Name Of Author
Senior Member, IEEE
Publisher IEEE
This paper proposes a new nine-level (9L) inverter

for medium and high-power applications. The proposed topology
comprises of a three-level (3L) active neutral-point-clamped
(ANPC) inverter connected in series with a floating capacitor
(FC) fed H-bridge. Besides, two additional switches operating
Details at line frequency are appended across the dc-link of the 3L
ANPC structure. Compared to conventional hybrid cascaded
inverters, the primary advantage of this addition is doubling of
the resulting rms output voltage. This amelioration is achieved
while preserving the standard 3L ANPC and H-bridge structures
with minimum topological modification.
2.2.19. A Dual-Bridge Inverter Approach to Eliminating Common-Mode Voltages and Bearing and
Leakage Currents
A Dual-Bridge Inverter Approach to Eliminating Common-Mode
Title
Voltages and Bearing and Leakage Currents
Annette von Jouanne, Member, IEEE, and Haoran Zhang, Student
Name Of Author
Member, IEEE
Publisher IEEE
This paper presents a dual-bridge inverter approach

to eliminate the motor common-mode voltage and resulting
bearing
and leakage currents. The novel dual-bridge inverter is
Details controlled to generate balanced excitation of the induction motor
under pulse width modulation (PWM) inverter operation.
Theoretical
analysis, simulation results, and experimental results are
presented to verify this concept.
2.2.20. A New Method for Common Mode Voltage Cancellation in Motor Drives:
Concept, Realization, and Asymmetry Influence
A New Method for Common Mode Voltage Cancellation in Motor

Title
Drives: Concept, Realization, and Asymmetry Influence
Di Han, Student Member, IEEE, Woongkul Lee, Student Member,
Name Of Author
IEEE,
Publisher IEEE
This paper introduces a new concept of common mode voltage

cancellation for pulse width modulated motor drives aiming at
solving issues such as ground leakage current, common mode
electromagnetic interference, and bearing current. The balanced
Details
inverter topology and dual-winding stator configuration is
proposed as a practical realization. Implementation considerations
on the influence of circuit asymmetry are also investigated. Finally,
HEMT based induction motor drive.
Chapter 3
BRIEF INFORMATION
3.1. Inverter
A dc-to-ac converter whose output is of desired output Voltage and frequency is called an
inverter. Based on their operation the inverters can be broadly classified into two types.
 Voltage Source Inverters(VSI)

 Current Source Inverters(CSI)
A voltage source inverter is one where the independently controlled ac output is a voltage
waveform.
A current source inverter is one where the independently controlled ac output is a current
waveform.
On the basis of connections of semiconductor devices, inverters are classified as below.
 Bridge inverters
 Series inverters
 Parallel inverters
Some industrial applications of inverters are for adjustable speed ac drives, induction heating,
standby air-craft power supplies, UPS (uninterruptible power supplies) for computers, HVDC
transmission lines etc.
3.2 Multilevel inverter
Among MLCs the following three topologies have been successfully implemented
as standard products for MV industrial drives The basic MLI are 3-level neutral point clamped
(NPC), 3-level flying capacitor (FC) and 3-level cascaded H-bridge (CHB) inverters
3.3. Brief Information
3.3.1 Neutral Point Clamped ( NPC )
The 3-level NPC are most commonly used MLI which require additional clamping
diodes and multiple isolated DC sources. For NPC inverter topology the midpoint potential
of a capacitive voltage divider in the dc link is used to stabilize the voltage distribution
between devices with the help of clamping diodes, e.g., D1 and D2 in Fig. 2. The topology
adds the zero level to the output voltage waveform and, thus, also serves to reduce its
harmonic content. The 3L inverter topology permits operation at double voltage, which also
doubles the maximum output power. Furthermore, the capacitors can be pre charged as a
group. The concept can be extended to any number of levels by increasing the number of
capacitors and diodes. However, due to capacitor voltage balancing issues, the NPC inverter
implementation has been mostly limited to the 3L inverter. This type of inverter is widely
used in MV applications and is one of the most commonly applied topologies. It
characterizes a relatively small dc-link capacitor, a simple power circuit topology, a low
component count, and straightforward protection and modulation schemes. Therefore, the
3L-NPC VSC is a competitive topology for a large variety of low and medium switching
frequency applications. Additionally, the 3L-NPC VSC has the highest converter efficiency
among the available solution
Fig. 3.3.1. Three-level inverter. (a) Circuit diagram. (b) Symbolic representation.
The NPC has found an important market in more conventional high-power ac motor drive
applications like conveyors, pumps, fans, and mills, among others, which offer solutions for
industries including the oil and gas, metal, power, mining, water, marine, and chemical industries.
Because all of the phases share a common dc bus, the capacitance requirements of the converter
are minimized. For this reason, a back-to-back topology is possible. This configuration for
regenerative applications has also been a major benefit, for example, in regenerative conveyors
for the mining industry or grid interfacing of renewable energy sources like wind power. Although
this topology has a simple circuit, usually, it needs a large inductive capacitive output filter to
operate standard motors.
3.3.2. Capacitor-Clamped Inverter (Flying Capacitor)

A typical the 3-level FC inverter uses only single isolated DC source. But as the number of
levels increased, the number of floating capacitor increases. Another popular voltage source MLI
uses the flying capacitor topology.
Fig. 3.3.2. Four-level inverter with flying capacitors and voltage dividers.
This topology offers the advantages of MLCs. However, the needs to balance the capacitors’
voltages and pre charge the capacitors at the start time, in addition to a larger number of
capacitors are the disadvantages of this topology the high capacitance values and stored energies
of the flying capacitors limit the use of 3L- and 4L-FLC to high switching frequency applications. In
the FLC, the load current charges every capacitor; hence, the respective capacitor voltages
change. The resulting changes must be maintained within permissible limits. Thus, the required
capacitance increases approximately in inverse proportion to the switching frequency. This makes
the FLC topology impractical at very low switching frequencies. Therefore, the stored energy of
the flying capacitors and the dimension of the LC inverter output filter is increased by a factor of
about 10 (for 3L-FLC) and 20 (for 4L-FLC) in comparison to 3L-NPC. The high cost of flying
capacitors at low and medium
3.3.3. Series-Connected H-bridge Inverter

The series H-bridge inverter appeared in mid 1970s and several recent works were
registered since this topology consists of series power conversion cells, the voltage and power
level may easily be scaled. However, a disadvantage is the large number of required isolated
power supplies. However, the cells can be supplied by phase-shifted transformers (an
expensive solution) in order to provide high power quality at the utility side the 5L-SCHB VSC
requires the lowest switch power rating and stored energy of the LC filter. Compared to the 3L-
NPC VSC, the installed switch power and the stored energy are significantly reduced (even up
to 80%). However, a complicated grid transformer, increased dc-link capacitance compared to
the 3L-NPC, and the high number of semiconductor devices are its draw backs. The absence of
a common dc voltage bus is an additional disadvantage of the 5L-SCHB VSC.
The cascaded H-bridge VSC has been applied for high-power and power-quality
industrial requirements due to its series expansion capability. This topology has also been
used for active filter and reactive power compensation. Electrical vehicles photovoltaic power
conversion uninterruptible power supplies (UPSs), and magnetic resonance imaging etc. A
hybrid asymmetric MLC is constructed by combining the SCHB with the NPC topologies [5].
Such a combination produces more output voltage levels with the same number of
components as a symmetric MLC. Although an H-bridge cell and a leg of the NPC converter
provide the same output voltage levels, the hybrid asymmetric ML topology requires a smaller
number of separate dc sources and H-bridge cells for the same output voltage levels.
Fig 3.3.3. Tree-level CHB featuring LV-IGBTs.
This topology can be operated with different switching frequencies and for different
applications. However, the need for a complex input transformer remains and its control is
complicated, therefore, it is not commercially offered [10], [68]. This is also true for the 9L-
SCHB, although it is a good topology for manifold MV drives, e.g., high-speed drives By
combining the basic NPC and half-bridge principles, a five-level topology was proposed; where
each phase of the inverter consists of two 3L-NPC half-bridges connected in series. One arm is
connected to the output terminal and the other is connected to the neutral point. The half
bridges are supplied by isolated dc sources, which are often composed of multi pulse diode
rectifiers.
3.3.4. Classification
Fig.3.3.4. Tree diagram of different classifications of MLIs.
These multilevel voltage source converter topologies belong to medium-voltage–high-power
converter family, whose classification is shown in Fig. 1.
3.3.5. Merit and Demerit of Multilevel Inverter

The topology combines the merits of low conduction losses in a two-level converter and
output quality in a three-level converter
 If a standard two-level voltage source converter (VSC) built with 1200-V IGBTs is
to a three-level neutral point clamped (NPC) converter built with 600-V devices, the
efficiency of the three-level converter can be better if the switching frequency is higher
than 10 kHz.
 The T type employs an active bidirectional switch to the dc-link voltage midpoint and
gets along with two diodes less per bridge leg.
 It is an alternative to more complex three-level topologies such as active neutral point
clamped converters or split-inductor converters.
 The 3LT2 C basically combines the positive aspects of the two-level converter such as
low conduction losses small part count and a simple operation principle with the
advantages of the three-level converter such as low switching losses and superior output
voltage quality.
 The hardware prototype has the ability to change its switching frequency and to switch
between two-level and three level modulation during operation. Accordingly, the impact
on the losses of passive components such as the load machine or the EMI filter can
directly be evaluated.
3.3.6. Active neutral point clamped Five-Level (ANPC5L)

It uses one four quadrant switch per phase to connect the DC-link midpoint ‘O’ to the
inverter output. Further, active neutral point clamped (ANPC) inverter. Incremental the
proposed concept is shown in Figure (a), which is named active-neutral-point-clamped five-
level (ANPC5L) converter. As can be seen, the proposed converter is an arrangement of
two-level inverters connected in series. Two of such subsystems are connected in parallel
with the dc-link capacitors. The first subsystem is comprised of S 5, S6, S9, Slo, and C2, while the
second subsystem is comprised of S 7, S8, Sll, S12, and C3. A third subsystem (S l, S2, S3, S4, and
Cl) is then used to connect the converter to the output phase.
(a)
Fig 3.3.6. Active-neutral-point-clamped five-level (ANPC5L) converter.
In general, an N-level converter can be obtained by cascading (N-1)/2 two-level inverters per
subsystem accordimg to Figure 2(a). A carrier-based PWM strategy can be used to generate
the pulse pattern, as shown in Figure 2(b) Four triangular carriers are used and phase-shifted
by 90. The first carrier generates pulses to SI and S2, the second carrier to S3 and S4, the third
carrier to S5, S6, S7, and S8, and the fourth cau Tier to S9, S1o. Si, and S12. It is worth
mentioning that the switches S5 and S7 are operated in phase, and while S6 and S8 are also in
phase, they are complementary to S5 and S7. A similar sequence is applied to S9, Smo, SIi, and
S12.
Fig 3.3.6. Carrier based PWM and Normalized phase voltage
The resulting nonrmalized phase voltage (nonrmalized with respect to half of the dc-link voltage)
is also illustrated in Figure 2(b), and it contains five different voltage levels as shown. For an N-
level converter, it would be necessary (N-1) carrier waveforms phase-shifted by 360°/ (N-1).
3.3.7. Asymmetric/hybrid cascaded circuit topology

Fractional a further optimization in terms of input current harmonics can be done
when a multipulse transformer is used to provide the isolated dc sources. By using a different
phase angle for each group of secondaries, i.e., secondaries that fed the inverters of each output
phase, it is possible to eliminate characteristic harmonics produced by the diode-based rectifiers
These phase angles can be calculated using Δϕ=π/3Ninv……………………. (2)
Where Δϕ is the relative angle between Group of secondaries. When single phase rectifiers are
used the secondaries must be arranged in a more complex structure.
The use of a cascaded five-level NPC inverter instead of a three-level inverter has received an
increased attention [12]–[15], due to the possibility to increase the total number of output voltage
levels by keeping a fixed number of inverters. Moreover, the NPC topology has become an
established technology in power electronics inverters. The total number of levels using cascaded
five-level NPC inverters is
Given by LphNPC = 4NPC+1………………(3)
Where NNPC is the number of NPC inverters connected in series. By using the same principle, there
is a possibility to connect in series two or more FC inverters in order to increase the number of
output voltage levels. Two FC inverters are connected in series to obtain a 13-level output
voltage. Usually, cascaded multilevel inverters use the same dc-link voltage value for every cell.
However, using different dc-link voltages, it is possible to increase the maximum number of
output voltage levels. The topologies that have different dc-link voltages are called in the
literature as asymmetric cascaded inverter. The relationship among the dc-link voltages to
provide a regularly stepped output voltage waveform could be binary (power of two) or trinary
(power of three).
Fig. 3.3.7. Asymmetric/hybrid cascaded circuit topology.
The maximum numbers of output voltage levels are given by
bin (Ninv+1) Ninv…………………(4)

L ph =2 − 1 L ph tri = 3
The asymmetric inverter configuration in Fig. 3 shows a cascaded-inverter-driven induction

machine using asymmetry and three inverters per phase [17], [18]. It is possible to note that,
although the dc voltages have a proportion of 9/3/1, the nominal power driven by each inverter
has a different proportion, where the high-voltage cell manages the major part (89%) of the output
power [19]. Due to this power distribution, these kinds of inverters can be designed with different
switch technologies like integrated gate commutated thyristor for high power inverters, high-
voltage insulated-gate bipolar transistor for medium-power inverters, and low- voltage insulated-
gate bipolar transistor for low-power inverters. Cascaded multilevel inverters that use different
switch technologies are also called the literature as hybrid cascaded inverters.
3.3.8. Hybrid seven-level converter.
Recently, hybrid multilevel converter configurations based on the combinations and
variations of the well-known topologies have been proposed and investigated as competitive
solutions. The active neutral point clamped (ANPC) converter is a newly introduced hybrid multilevel
converter topology which combines the flexibility of an FCC with a DCC to generate a multilevel
voltage waveform. Conceptually, an ANPC does not have the drawbacks of the FCC and DCC
converters.
Three-level and five-level ANPCs have been studied/investigated in the technical literature
and their salient features, i.e., reduced switching losses and improved voltage balancing
capability, as compared with the DCC and FCC have been highlighted. However, as of now an
ANPC with a number of levels more than five has neither been comprehensively analyzed nor its
control strategies and operational characteristics been investigated.
Fig. 3.3.8. Circuit diagram of the proposed hybrid seven-level converter.
3.3.9. Seven-Level Hybrid-Clamped (HC)
Microcontrollers A novel seven-level hybrid-clamped (7L-HC) topology, as shown in
Fig.1 (a), is proposed for medium voltage VFD applications. The voltage stress on S1- S4, S1-
S4, and C2 is Vdc/3 while it is Vdc/6 on S5- S6, S5- S6 and capacitor C1. Such a VFD system
can have multi-pulse diode front end (DFE) (Fig. 1(b)) or active front end (AFE) with
regeneration Capability (Fig. 1 (c)
Fig 3.3.9. 7L-HC topology and examples of front ends in VFD.

(a) 7L-HC converter.
(b) DFE constructed by the multi-winding transformer and diode rectifier.
(c) AFE constructed by 7L-HC.
As the DFE can balance the DC link capacitors, only one floating capacitor per phase (C1 in Fig.
1(a) is required when the 7L-HC topology operates as the inverter. The simplified topology can
generate 7L voltage output and achieve floating capacitor C1 voltage balancing at switching.
Frequency, which ensures low floating capacitor voltage ripple under low-speed motor operation.
This makes it a very suitable inverter for VFD systems with wide speed ranges. When the 7L-HC
topology is applied as AFE, floating capacitor C2 is needed to obtain more redundant switching
states, enabling the converter to balance both the floating capacitor voltages and DC link
capacitor voltages. In this case, the 7L-HC inverter still does not require C2. Uses three isolated
power supplies. The research is still focused on developing new MLI topologies to obtain fine
space vector structure with optimal number of component counts like power semiconductor
switches, floating capacitors and isolated power supplies. The NPC, ANPC and stacked MLI
require multiple isolated DC power supplies to generate multilevel.
The NPC, ANPC and stacked MLI require multiple isolated DC power supplies to
generate multilevel. These MLI can be made to operate with single DC-link operation and stacked
capacitor but suffers from neutral point voltage (NPV) fluctuations which causes imbalance in the
DC-link stacked capacitor voltages. This paper is focused on those cases in which the NP of the
three-level converter is floating, and voltage balancing between the capacitors should be
controlled by the converter itself. Several publications discuss ways to solve this balance problem
however, this objective may be unattainable when operating with high modulation indices. In
such conditions, a low-frequency ripple appears in the NP potential. Because of this oscillation,
the output line-to-line voltages will also contain low-frequency harmonics [9], and additionally,
the devices of the bridge and the capacitors themselves must withstand higher voltages than
when balance is achieved.
3.3.10. Three-level NPC converter

Fig. 1 shows the topology of the three-level neutral-point-clamped (NPC) converter,
which in recent years has attracted attention for its potential use in high-power applications. To
take full advantage of this converter, the voltages of the two series-connected dc-link capacitors
must be confined to one half the level of the dc-link voltage. Several publications discuss ways to
solve this balance problem however, this objective cannot be achieved when operating with a
high modulation index and a low power-factor (PF) load is connected to it Under these
conditions, the average value of the neutral-point (NP) current calculated over a modulation
period cannot be maintained at zero, and thus appears as a low-frequency ripple in the NP
potential. As a result of this oscillation, the output line-to-line voltages will also contain low-
frequency harmonics, and the devices and capacitors themselves must additionally support
voltages that are higher than those that occur when balance is achieved. Larger capacitor can
attenuate the amplitude of this oscillation, but as it increases the cost of the whole system this
solution is best
Fig 3.3.10. Topology of the three-level NPC converter.
Avoided. Other approaches suggest allowing the NP voltage to oscillate and then compensating
for the effects of the oscillation in the output voltages with a proper feed forward modulation [7]–
[9]. Nevertheless, these proposals do not reduce the voltage applied to the devices, and some
instability may appear when the system operates as a rectifier [8], [9]. In many applications, two
NPC converters are connected back-to-back. Some examples can be found in bi-directional
motor drive applications [10]–[13], as well as in high voltage dc (HVDC) link [14]. In those cases
the task of balancing the NP voltage can be distributed between the converters. Hence, better
balancing results can be achieved. Nevertheless, any study has been carried out with the
objective of quantifying NP balancing improvement so far.
3.3.11. Method Of Control NPV
Multiple control methods to regulate the NP voltage in three-phase NPC converters following a
CBPWM approach have been proposed in the technical literature. These methods can be classified
into three categories.
 Firstly, there are those methods that use an external linear or nonlinear controller to
determine the zero-sequence voltage used to balance the NP voltage.
 Secondly, there are those methods in which the zero-sequence voltage calculation is
embedded into the modulation method In particular establishes a correlation between
SVPWM and CBPWM, and based on that correlation, a method to directly determine the
zero-sequence voltage injection is proposed
 Thirdly, there are those methods where some phases of the converter are forced to
commutate between multiple voltage levels in each modulation period to achieve NP
voltage balance
These methods are able to completely cancel the low-frequency NP voltage oscillations; however,
this is achieved at the cost of decreasing the efficiency of the converter and the quality of the
output voltage waveforms.
A new method to balance multiple (more than one) NPV instantaneously irrespective of
load power factor and throughout the linear modulation range using symmetrical 6-phase IM. The
same method is extended to obtain the CME multilevel structure using single DC source for OEIM,
for the first time. The scheme is implemented with 7-level (7L) structure formed by three stacked
DC-link capacitors cascaded with two capacitor fed CHBs per phase. The capacitors in two CHBs
are maintained at voltages of Vdc/12 and Vdc/6 using pole voltage redundancies. The neutral points
are used only as tapping points to generate different output voltage levels, with no net current
drawn from it and there by maintaining the NPV balanced. Switching loss in the power circuit is
also analyzed in the paper. The generalization of the proposed method to any stacked MLI with
any number of stacks is also discussed. The Method uses the symmetrical 6-phase induction motor
(IM) and connect the equal and opposite phases to the same neutral point. But this method of
NPV control is open-loop and will not able to control the NPV deviation in case of disturbance,
non-idealities, etc. This paper presents a new hybrid inverter topology capable of generating 7-
levels at the output. It is formed by cascading a 3-level T-type and 5-level ANPC inverter. It
combines the advantages associated with both ANPC and T-type inverter. The topology is realize
by using low voltage devices and capacitors of rating Vdc/3 and Vdc/6. The topology uses three
floating capacitors per phase which can be balanced in each sampling duration using pole voltage
redundancy. The topology requires two symmetrical DC sources corresponds to each stack for the
3-phase system. Further, the single DC-link operation with closed loop control of NPV for the
proposed topology is obtained using the symmetrical 6-phase IM with inverter feeding all the 6-
phases.
3.3.12. Topology:
The power circuit topology for proposed hybrid 7-level inverter is shown in Fig. 1(a). It
is formed by cascading 3-level T-type inverter with a 5-level ANPC. It consists of 12 switches per
phase where switches Sxy (x= 1, 4, 5, 6, 7, 8; y= A, B or C) have to block a voltage of Vdc/3 while
switches Sxy (x= 2, 3, 9, 10, 11, 12; y= A,B or C) have to block a voltage of Vdc/6. The switches
(S1, S2), (S3,S4), (S5,S6), (S7,S8), (S9,10) and (S11,S12) are complementary to each other.
Fig. 3.3.12. Power circuit topology
The topology also uses 3 floating capacitors per phase, two out of which are maintained at a
voltage of Vdc/3, while one is maintained at a voltage of V dc/6. The topology generates 7 pole
voltage levels along with redundancies which is indicated in Table I. The redundancies are then
used to balance all the floating capacitor voltages during each PWM switching cycle. This
balancing is independent of load power factor and modulation index. The topologies forms two
stacks at the front end which require individual DC sources of V dc/2. Table I shows the terminal in
the DC-link which is used to generate the pole voltage by the use of proper addition and
subtraction of floating capacitor voltages.
3.3.13. Capacitor Voltage Balancing:
Table I shows the switching states for various switches. It can be seen that generation
of level ‘-2’, ‘-1’ uses voltages from C2x and C3x (x = A, B, C) and thus the corresponding
capacitor (C2x and C3x) voltages will get deviated. Similarly, the generation of level ‘2’, ‘1’ uses
voltages from C1x and C3x
(x = A, B, C) and thus, will deviate the corresponding capacitor (C1x and C3x) voltages. While, the
levels ‘-3’, ‘0’and ‘3’ uses DC-link terminals to apply appropriate voltages from phase terminals
and thus, all the floating capacitors are bypassed. The current through the floating capacitors are
given as
TABLE I. 3.3.13. Inverter levels and pole voltage redundancies for the proposed scheme
IC1x = (S1x * (S5x _ S9x)) Ix ; x = A, B, C……………………..(1)
IC2x = (S4x * (S8x _ S10x)) Ix ; x = A, B, C……………………(2)
IC3x = (S9x * S11x)Ix ; x = A, B, C………………(3)
Where, Ix are the phase currents, while the Syx (y = 1, 4, 5, 8, 9, 10, 11) are the switching states.
This affects the capacitor voltages and appropriate switching state combination can be used to
keep the capacitors within the hysterises band. The Table I depicts all the possible redundancies
to obtain the pole voltage levels. These pole voltage redundancies for each pole voltage is
sufficient to bring back the floating capacitor C1x, C2x, C3x (x = A, B, C) voltages in all the phases
within the hysteresis band, if they deviate out of band. This balancing is independent of load
power factor and modulation index.
3.3.14. Extension of proposed topology:
The porposed topology can be extended to obtain 13, 25, 49,....(6(n+1)+1) (‘n’ is the
number of CHBs) levels by adding capacitor fed CHBs in each phase as shown in Fig.1(b).In this,
the CHB capacitor can be balanced using switching state redundancies for each pole voltage
levels and this balancing is independent of modulation index and load power factor. For example,
13-levels can be obtained by cascading one CHB per phase with capacitor maintained at a
voltage of Vdc/12 by using switching state redundancies. The topology can generate 13 pole
voltage levels which are (VxO; x: A, B or C) -V dc/2, -5Vdc=12, -4Vdc/12, -3Vdc/12, -2Vdc/12, -Vdc/12,
0, Vdc/12, 2Vdc/12, 3Vdc/12, 4Vdc/12, 5Vdc/12 and Vdc/2 from each of the phase terminals. Similarly,
the 25-level operation can be obtained by using two additional capacitor fed CHBs in each phase
with CHB capacitors maintained at Vdc/12 and Vdc/24.
Likewise, 49-level MLI can be obtained using three CHBs in each phase with CHB capacitor
voltages maintained at Vdc/12, Vdc/24 and Vdc/48.
3.4. Comparison:
3.4.1. Component Counts
Table II shows the comparison of proposed 7-level inverter topology with some of the existing 7-
level topologies reported in literatures. The comparison is made based on the component count
such as number of switches, isolated power supplies, clamping diodes and floating capacitors
required to realize the topology. Table II also compares the voltage ratings of different
components used.
TABLE II. 3.4.1. Comparison of proposed 3-phase 7-level inverter with other MLI topologies
1. A 7-level NPC inverter uses 90 clamping diodes (equal rating) and 6 isolated power
supplies of Vdc/6.
2. A 7-level FC inverter uses 45 floating capacitors of rating Vdc/6.
3. A 7-level CHB inverter uses 9 isolated power supplies, which makes the systems bulkier
and costly.
4. The 7-level ANPC topology uses 2 isolated power supply and 54 low voltage switches with
voltage blocking capability of Vdc/6. It also uses auxiliary circuit for commutating the series
connected switches.
5. The 7-level topology is realized by using devices with less blocking voltage but requires 42
devices and 3 isolated power supplies. It also needs 6 floating capacitor of voltage ratings
Vdc/6 to obtain the 7-level operation.
6. The 7-level topology uses devices with less blocking voltage but needs 3 isolated power
supplies.
7. A new 9-level topology using reduced number of switches but uses six isolated power
supplies for 3-phase system and also the capacitor in the half bridge needs to be designed
for fundamental frequency. In this topology needs 12 switches, 1 floating capacitor and 2
isolated DC sources to obtain 9-level operation.
This results in using six isolated DC sources for 3-phase system. The device count of proposed 7-
level inverter is highlighted in Table II. It uses only two symmetrical isolated power supplies for the
3-phase system. It uses 9 low voltage (Vdc/3 and Vdc/6) floating capacitors per phase but all the
floating capacitors need to be designed for one PWM switching duration using switching state
redundancies of Table II. Thus, low value of capacitance can be used as floating capacitors.
3.4.2. Switching and conduction Losses:
During PWM operation of inverter, the switches in the proposed inverter (Fig. 1(a)),
switches at different frequency. The average switching frequency of individual switches over a
fundamental cycle depends on the floating capacitor value, magnitude of phase current, time
duration of fundamental cycle and sampling frequency. The average switching frequency over a
fundamental cycle of various switches with fundamental frequency is shown in Fig. 2(a). The
switching loss comparison for some of the 7-level inverter topology mentioned in literature is
shown in Fig .2(b). It shows the switching losses of the topologies mentioned in row 4, 5, 6 and 9
of the Table II.
Fig. 3.4.2. Switching frequency and switching loss Comparision.
(a) Average switching frequency (Hz) of switches :(1) S9 x and S10x, (2) S11x and S12x, (3) S1x and S2x, (4)
S3x and S4x, (5) S5x, S6x, S7x and S8x (where, x: A,B or C)
(b)Switching loss comparison of proposed topology with other existing 7-level topologies in literature
The switching losses are calculated analytically for 15kW, 415V, 3-phase drive system. It
corresponds to Vdc of 550V and peak phase current of 30A. The switching loss is obtained by
calculating the switching energy during each transition and then averaging it over a fundamental
cycle, for MOSFETs switching loss (Psw) is Given as Pswitching = P
n VI ( ton+toff ) / 2 *ffund.
Where, n is the number of switching transitions, fund is the fundamental frequency, V and I are
the voltage stress and current through the switches respectively, ton and t off are the turn-on
and turn-off time respectively. Farnell FQL50N40 (50A, 400V) MOSFETs are used as switches for
calculating switching loss in the inverters.
The switching losses comparison show that proposed topology has relatively lower switching loss
as compared to other topologies especially at the higher modulation index. It is because, in
proposed topology, at lower modulation index the inverter will be in the middle pole voltage
levels (‘-2’, ‘-1’, ‘0’, ‘1’, ‘2’ from Table I) which results in more switching of S5, S6, S7, S8 switches
(having blocking voltage of Vdc/3) which is also shown in trace 5 of Fig.2(a). Further, middle levels
causes switching of 5 switches as the neutral point ‘O’ (Fig 1(a)) is used to obtain desired level at
the phase terminal (Table I).
The conduction loss comparison for the 7-level topologies available in literature is
shown in Fig.3. The conduction loss is calculated analytically for 15kW, 415V, 3-phase drive
system. The average conduction loss (Pcon) for MOSFET during fundamental period is given as
Pcon = I2 R
rms dson Where, Rdson is the on state resistance of the switch which can be obtained from the
datasheet. Irms is the rms value of currents flowing through the switch during the entire
fundamental period. Farnell FQL50N40 (50A, 400V) are used as switches for calculating
conduction losses in the inverter.
Fig.3.4.2. Conduction loss comparison of proposed topology with other existing 7-level topologies in literature
(1) Proposed 7-level inverter.
(2) 7-levelANPC.
(3) 7-level Topology.
(4) 7-level Topology.
The proposed topology uses 4 or 5 devices in the conduction path while generating
the desired level as also shown in Table I. 5 devices are used when neutral point ‘O’ is used to
generate pole voltage level. Thus, during lower speed operation, the inverter will be in middle
levels for more time and uses 5 switches in conduction path. This results in more conduction loss
at lower speed of operations.
Chapter 4
SYSTEM DESCRIPTION
4.1. BASIC BLOCK DIAGRAM:
DC SOURCE LEVEL POLARITY OUTPUT

GENRATION GENRATION VOLTAGE
PART PART
LOAD
CONTROL
Fig 4.1. Basic Block Diagram of System
4.2. SINGLE DC-LINK OPERATION
The proposed topology (Fig 1(a)) uses two symmetrical isolated DC-sources due to
which four quadrant operations are not possible and also it makes the system bulkier. This can be
avoided by using single isolated DC source with two stacked capacitor. But, the inverter may use
mid-point or neutral point ‘O’ (Fig 1(a)) while applying the desired pole voltage level from phase
terminals in order to balance floating capacitor voltages (as per Table I). This results in drawing
non-zero currents from the neutral point, and thus results in NPV deviation. The method results in
instantaneous balancing of NPV irrespective of loading, load power factor and modulation index.
In this method, a symmetrical 6-phase IM is used along with proposed inverters feeding all the 6-
phases as shown in Fig.4. A symmetrical 6-phase IM has 6-phase windings displaced by 60 0 from
each other. This forms three sets of opposite phase pairs A-A’, B-B’, C-C’. In order to aid the air
gap flux of IM the opposite phase pairs will have to apply exactly opposite pole voltage levels. For
example, if A-phase is in the upper pole voltage levels ‘1’, ‘2’ or ‘3’, then the opposite phase A’
will have to apply lower pole voltage levels ‘-1’, ‘-2’ or ‘-3’ respectively. Since the opposite phases
applies opposite pole voltage levels, the currents in both the phases are equal and opposite.
Thus, when one phase is connected to neutral point ‘O’ (Fig.4), the opposite phase is forced to
connect to the same neutral point. As a result there is net zero current drawn from the neutral
point ‘O’ and thus the instantaneous balancing of NPV is ensured.
During each sampling duration one of the inverter from INV1 and INV2 (Fig.4) are
assigned as master inverter, while the other one is assigned as slave inverter. Based on the
floating capacitor voltage status and current status in the phase of master inverter, the switching
states are chosen from Table I. During this instant, if the chosen switching state in a phase of
master inverter uses neutral point ‘O’, then the opposite phase pair in slave inverter is forced to
use the neutral point ‘O’ by choosing appropriate switching state from Table I. This may deviate
the floating capacitor voltages in the phases of slave inverter, which can be brought back within
the hysteresis band by making the slave inverter as master in next sampling duration. Thus, each
floating capacitors need to be designed for two sampling durations. Further, due to use of
symmetrical 6-phase IM, DC-link requirement is reduced to half and accordingly all the floating
capacitors voltages are scaled by half. Common-mode (CM) voltage Multilevel converters
produce smaller CM voltage therefore, the stress in the bearings of a motor connected to a
multilevel motor drive can be reduced. Furthermore, CM voltage can be eliminated by using
advanced modulation strategies with dual inverter system, the common mode voltage (V cm) for
six-phase system is
Given as Vcm = VAO + VBO + VCO + VA’O + VB’O + VC’O/6……. (4)
Where, VAO, VBO, VCO, VA’O, VB’O and VC’O are the pole voltages applied from A, B, C, A’, B’ and C’
phase terminals respectively. Since, opposite pole voltage levels are applied from opposite phase
pair to aid the air gap flux, the VAO = - VA’O, VBO = - VB’O, VCO = -VC’O at every instant of time.
Fig. 4.2. Proposed 7-level topology with single DC-link using symmetrical 6-phase IM
This results in Vcm = 0 from eqn. (4). Due to zero common mode voltage, the motor bearing
currents will get eliminated thus reducing the bearing failure.
Since, the neutral n and n’ (Fig.4) are isolated from each other and are not connected to the DC
bus neutral point voltage ‘O’, the eqn. (4) can be written as V cm = VnO + Vn’O/2 ……. (5)
Where, VnO = VAO+VBO+VCO/3 , Vn’O= VA’O+VBO+VCO/3
4.2. Closed Loop Control of Neutral Point Voltage:
In steady state and normal operation, the neutral point voltage is balanced or
maintained at Vdc/4 (as the DC-link is Vdc/2 due to use of 6-phase IM) by drawing net zero
current from the neutral point ‘O’ at all the instant. But, if the neutral point voltage deviates due
to fault, disturbance or Non idealities, it can be brought back to its nominal value by using closed
loop control of DC-link capacitor voltages. In this the DC-link capacitor voltage is sensed and sent
for PWM. Then, the NPV deviation can be nullified by intentionally connecting one of the
opposite phase pairs to neutral point ‘O’ and other to either DC-link positive or negative terminal
using switching state redundancies (Table. I). This occurs, when the phase of the master inverter
uses neutral point ‘O’ to balance its floating capacitors while generating particular pole voltage
level and slave inverter is forced to connect to neutral point (normal case), while generating
opposite pole voltage level. There are 8 possibilities in which DC-link capacitor can be charged or
discharged by intentionally not connecting one of the phase to the neutral point. These
possibilities are shown in Fig.5 with INV1 as master and INV2 as slave inverter. The possibilities in
Fig.5(a), (b), (c), (d) arise when phase of master inverter is in levels ‘-1’ or ‘-2’, while phase of slave
inverter is in levels ‘1’ or ‘2’. Similarly, possibilities in Fig.5(e), (f), (g), (h) arise when phase of master
inverter is in levels ‘1’ or ‘2’, while phase of slave inverter is in levels ‘-1’ or ‘-2’. Similarly, the DC-
link capacitor (Ca, Cb) can be charged or discharged with INV2 act as master and INV1 act as
slave inverter.
Fig. 4.2. Effect on DC-link capacitor charge when opposite phase pair (A-A’) does not connect to the neutral point
‘O’ of Fig.4.2
Based on the status of DC-link capacitor (Ca, Cb) voltage and phase current direction, the
switching state for the opposite phase pairs are chosen. This will affect the DC-link capacitor (Ca,
Cb) voltage and bring it back to the nominal voltage. During this instant, the floating capacitors in
the opposite phase (which is using neutral point and DC-link terminals) may get deviated. Hence,
in the first sampling duration the
DC-link capacitor is given preference, in the second, floating capacitor of phase in master inverter
is given preference and in the third, floating capacitor of opposite phase in slave inverter is given
preference to balance. The floating capacitor ripple will be more than the normal case, but it can
be balanced in three sampling durations. Once, the disturbance vanishes, the normal operation
resumes and floating capacitors in INV1 and INV2 are balanced in two sampling duration by
making each inverter master and slave alternatively.
For example, assume that the A-phase is in voltage level level ‘2’ as per Table. I and A’-phase is
in voltage level level ‘-2’ as per Table. I. Thus, when NPV is balanced, the switching states of
opposite phases are selected (based on floating capacitor voltage status) such that both A, A’
phase are connected to neutral point, if neutral point is used to generate the pole voltage levels.
As a result, a net zero current is drawn from the neutral point. In case of non-idealities or
disturbance, when NPV goes out of band, one phase out of A or A’ can be connected (based on
phase current direction) such that the switching state brings back the NPV within the band For
example, assume A-phase current is positive and A’-phase current is negative. If Cb capacitor
voltage (Fig. 5) needs to be charged, the switching state from Table. I is chosen such that A’-
phase current (which is negative) is drawn from ‘O’ point and A-phase current (which is positive)
is drawn from DC-link positive terminal as shown in Fig5 (g). This result in charging of the Cb
capacitor and NPV is brought to its nominal value. Similarly if Cb capacitor voltage needs to be
discharged, the switching states from Table I is chosen such that the A-phase current (which is
positive) is drawn from neutral point ‘O’ and A’-phase current (which is negative) is drawn from
DC-link negative terminal as shown in Fig.5(f), which led to discharging of Cb capacitor voltages.
Similarly, B-B’ and C-C’ phase pairs can also be used to correct the NPV deviation. Once, the
neutral point voltages are brought to its nominal value, normal operation is resumed. In this case,
DC-link capacitor voltage sensing is must throughout the modulation index for proper closed
loop control of DC-link capacitor voltages.
Chapter 5
CALCULATION FOR HARDWARE & SIMULINK MODEL RESULTS
5.1. Specifications
1. Symmetrical 6 phase Induction Motor
Motor Power Pm = 15kW
Motor rated voltage, Vll =415V
Motor rated frequency, F = 50Hz
Stator resistance, Rs = 1
Rotor resistance, Rr = 1.932
Magnetizing inductance, Lm = 260mH
Stator leakage inductance, Lls = 9.13mH
Rotor leakage inductance, Llr = 9.13mH
Mechanical time constant, JB = 18sec
2. Display
Two DSPs ( TMS320F28335 ) and FPGAs ( Spartan3XC3S200 )
3. MOSFET IRF240N (50A, 200V).
4. Floating Capacitor of 4400 mF, Capacitor of 2200 mF
5.2. Switching loss :
Formula for calculating filter switching loss is
P switching = En VI ( Ton+Toff ) * F fund
2
Where, n is the number of switching transitions,
F fund is the fundamental frequency,
V is the Voltage stress,
I is the current through respectively switches,
Ton Are the turn on time,
T off Are the turn off time,
MOSFETs (50A, 400V) are used for calculating switching loss in the inverters.
5.3. Conduction loss
Formula for calculating filter conduction loss is

Pcon = I2rmsRdson
Where,
Rdson is the on state resistance of the switch which can be obtained from the datasheet.
Irms is the rms value of currents flowing through the switch during the entire fundamental period.
5.5. SIMULINK MODEL & ITS SUBSYSTEMS
The detailed MATLAB/Simulink model for seven level inverter is shown in figure 5.1. The different
blocks used for this project are explained separately. In the figure 5.1,
Fig 5.5. Simulink model for Seven level inverter
Complete model of seven level inverter is shown. Switches are triggered using PD-SPWM
technique
is connected to MPPT Solar Charge Controller block. Battery parameter input is also given to
MPPT Solar Charge Controller block. In Fig.4.1, battery is connected to output of Boost
Converter where it gets charge at is required voltage to get charged very efficiently. Here also
one floating scope is connected to view PV power, duty cycle, and efficiency in graphical form.
And also, the display is connected to m terminal of battery to view the battery parameters.
Figure 4.2 shows the subsystem for the MPPT controller with its control system
Fig.4.2 MPPT with its control system
Fig.4.3 Subsystem for power calculation
Fig.4.5. Algorithm for MPPT
Function D = Pand0 (Vpv, Ipv)

Persistent Doid Poid Void
If isempty (Doid)
Doid = 0.35;
Void = 17;
Poid = 120;
end
deltaD = 0.001; Ppv = VPV*Ipv;
If (PPV-Poid) = 0
If (PPV-Poid) > 0
D = Doid – deltaD;
else
D – Doid + deltaD; end
else if (Vpv-Void) > 0

D = Doid + deltaD;
else
D = Doid – deltaD;
end
end
else D = Doid; end
Doid = D;
Void = Vpv;
Poid = Ppv;
It is the simplest method of MPPT to implement. Also commonly known
as hill climbing method, it consists of perturbation of the duty cycle thus observing the alteration in
power, continuing the perturbation in the unchanged direction if power tends to increase else perturbation of
duty cycle is reversed Perturb & Observe (P&O) is the simplest method. In this we use only one
sensor, that is the voltage sensor, to sense the PV array voltage and so the cost of implementation is
less and hence easy to implement. The time complexity of this algorithm is very less but on reaching
very close to the MPP it doesn’t stop at the MPP and keeps on perturbing on both the directions.
When this happens, the algorithm has reached very close to the MPP and we can set an appropriate
error limit or can use a wait function which ends up increasing the time complexity of the algorithm.
However, the method does not take account of the rapid change of irradiation level (due to which
MPPT changes) and considers it as a change in MPP due to perturbation and ends up calculating
the wrong MPP. Perturb and observe (P&O) is one of the famous algorithms due to its simplicity
used for maximum power point tracking. This algorithm based on voltage and current sensing
based used to track MPP. In this controller require calculation for power and voltage to track MPP.
In this voltage is perturbed in one direction and if power is continuous to increase then algorithm
keep on perturb in same direction. If new power is less than previous power then perturbed in
opposite direction. When module power reach at MPP there is oscillation around MPP point.
4.6 Waveforms
4.6.1 Voltage, Current & Power of Solar Module
Fig. 4.4 Waveforms for Voltage, Current & Power of Solar Module
The variation of PV voltage, current and power during load variations from open circuit
condition to short circuit condition is shown in Fig.4.4. The proposed system proved that
hardware results are found to match in close proximity with simulation results. But variation is
due to the internal resistance of PV and variation of irradiation. Circuit Voltage, Current and
maximum power point defines to remarkable point for getting the maximum power point at
any input irradiance to solar cell. The output waveform of current, voltage and power with
respect to time for a single solar cell are resulted by using Simulink model represented.
Fig. 4.5 Waveforms for Irradiance & temperature
Higher irradiance results in higher photo-current and higher open circuit voltage.
Keeping the temperature constant, maximum power is obtained from maximum irradiance.
While decreasing irradiance shifts the maximum power point to the lower left region, a
decrease in temperature helps to shift the maximum power point upwards. The incremental
conductance algorithm can track the maximum power operating point excellently under any
environmental condition. Maximum Power Point Tracking (MPPT) is the most effective solution
to extract the maximum power from the PV system.
Fig.4.6 Waveforms for Solar Power & Load Power
The output power of PV varies due to change in temperature and irradiation levels. This
reduces the conversion efficiency. Hence, Perturb and Observe (P&O) algorithm is used to
achieve maximum power from PV panel with suitable duty ratio and also improves efficiency.
The simulations are carried out using MATLAB/SIMULINK to validate the operation and
effectiveness of the converter using MPPT algorithm.
Figure 4.7 & 4.8 shows the waveforms for Load Current & Load Voltage
Fig. 4.7 Waveforms for load Current
Fig. 4.8 Waveforms for Load Voltage
Figure 4.7. displays the output current under the same circumstances. As it
can be seen, the current plot is inverted respect to the voltage plot. This is because the
converters work on boost mode. Also, at the beginning of the plot the battery and the load
pull energy from the PV. This goes on until the battery charges and enters the flotation. The
next transient occurs when the PV voltage drops. Since voltage goes down 5V the control
shutdowns the PV-Battery converter and as consequence the capacitor of this converter gets
quickly discharged generating a current peak. Finally, calculated active power is displayed in
Figure 4.8.
CONCLUSION
The paper proposes a hybrid 7-level inverter topology for variable frequency drives. The
proposed 7-level inverter is realize using low voltage semiconductor devices and formed by
cascading a 3-level T-type with 5-level active neutral point clamped inverter. It forms two stack
at the front-end and require symmetrical DC sources for individual stacks. The topology
consists of three floating capacitors per phase, out of which two are maintained at V dc/3 and
one is maintained at V dc/6. All the floating capacitors are balanced within PWM switching cycle
using switching state redundancies for each pole voltage levels. This balancing is independent
of load power factor and modulation index. The brief comparison of the proposed topology
with some of the existing 7-level topologies in terms of components count, switching loss and
conduction loss is included. It is shown that this topology has reduced switching and
conduction losses with respect to some of the existing 7-level topologies. Further, the operation
with single DC isolated power supply with closed loop control of neutral point voltage in the
DC-link stacked capacitor is also explained in detailed. This balancing of NPV is independent of
load power factor, modulation index which enables the usage of small capacitance as DC-link
stacked capacitors. The topology with single DC-link with NPV control is experimentally verified
using symmetrical 6-phase IM for open loop V/f and closed loop field oriented control in
steady state as well as transient state. The stability of floating capacitor and DC link stacked
capacitor voltage control algorithms are tested by intentionally creating imbalances in the
capacitor voltages and then bringing the capacitor voltages to its nominal values. Also, with
dual inverter system Due to reduced losses and single DC-link operation, the proposed drive
scheme is one of the efficient solutions for battery fed applications, traction drives, etc.
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ACKNOWLEDGEMENT
It gives us immense pleasure to grab this opportunity to thank all those who were instrumental
in the successful completion of our Project and report within the prescribed time frame.
We have been fortunate to get the guidance of Mr.S.S.Deshmukh who took us through the
thick and thins of the completion of project work. We truly appreciate and value his esteemed
guidance and encouragement from the beginning to the end of this report. We are indebted to him
for having helped me shape the problem and providing insights towards the solution.
Our special to thanks Mr.S.S.Deshmukh (Class & Project Coordinator), Mr.Y.S.Pawar (Head of
Department) and to all the respected staff members and also the non-teaching staff and our friends
for their co-operation. We wish to express our gratitude to our parents, whose love and
encouragement has supported us throughout our education.
Place: Nashik
1) PRADHAN GANESH PANDURANG
2) GANDODE SANDIP MANOHAR
3) PAWAR ATUL ZIPARU
4) SACHIN BHUASAHEB WAGH
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mail.com Gangode
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Chapter 1

Recently, many publications have addressed multilevel converter technology and

1.2. Aim of Project:

1.3. Problem Formulation:

1.3.2 Problems in Existing System:

 This topology required more number of components compared to conventional topology.

 It required higher number of semiconductor switches.

 Does not have self - balancing property.

 It will have worse power quality.

1.3.3 Proposed System:

1.6. Layout of Project:

2.1. Literature review

Samir Kouro, Mariusz Malinowski, K. Gopakumar, This paper first presents

Jose I. L eon, sergio Vazquez, L eopoldo g. Franquelo, In the last decades,

Haitham Abu-Rub, Joachim Holtz, Jose Rodriguez , This paper gives an

Peter Barbosal, Peter Steimer, Jorgen Steinke, Manfred Winkehn

Weihui. Sheng, Qiongxuan. Ge, Traditional seven-level Active Neutral-point-

Mariusz Malinowski, K. Gopakumar, Cascaded multilevel inverters synthesize a

Maryam Saeedifard, Peter Mantovanelli Barbosa , This paper introduces a novel

Apurv Kumar Yadav, K. Gopakumar, Krishna Raj R, This paper proposes a

Kaibalya Prasad Panda, Prabhat Ranjan Bana , Switched-capacitor based

Sandeep. N, Udaykumar R Yaragatti, This paper proposes a new nine-level

Annette von Jouanne,Haoran Zhang, This paper presents a dual-bridge

Rahul Kanchan, M.R. Baiju, K. Gopakumar, A pulse width modulation

2.2. Summary of Literature Review:

2.2.1. Recent Advances and Industrial Applications of Multilevel Converters

Samir Kouro, Member, IEEE, Mariusz Malinowski, Senior Member,

Year of Publishing 2010

Multilevel converters have been under research and development

Name Of Author C.Thulasi yammal and S Sutha

Year of Publishing 2017

2.2.3. Medium-Voltage Multilevel Converters—State of the Art, Challenges, and Requirements in

Name Of Author Bolivar Alvarez, Alberto S´anchez and Omar Aguirre

Year of Publishing 2010

Details their topologies, limitations, and control techniques. As a

2.2.4. Design and Implementation of a Highly Efficient Three-Level T-Type

Converter for Low-Voltage Applications

Design and Implementation of a Highly Efficient Three-Level T-

Mario Schweizer, Student Member, IEEE, and Johann W. Kolar,

Name Of Author T. Bruckner, S. Bernet

Year of Publishing 2001

2.2.6. Active-Neutral-Point-Clamped (ANPC) Multilevel Converter Technology

Active-Neutral-Point-Clamped (ANPC) Multilevel Converter

Year of Publishing 2005

A Novel Seven-level ANPC Converter Topology and Its

Year of Publishing 2013

Capacitor Inverter and an H-Bridge

A Five-Level Inverter Topology with Single-DC

P. Roshankumar, Student Member, IEEE, P. P. Rajeevan, K.Mathew,

Year of Publishing 2012

2.2.9. A Survey on Cascaded Multilevel Inverters

Title A Survey on Cascaded Multilevel Inverters

Details Cascaded multilevel inverters synthesize a medium voltage output

2.2.10. Operation and Control of a Hybrid Seven-Level Converter

Maryam Saeedifard, Senior Member, IEEE, Peter Mantovanelli

Publisher IEEE Journal

2.2.11. A Novel Seven-Level Hybrid-Clamped (HC) Topology for Medium Voltage