Developing High Throughput

communication interface for high

frequency trading on FPGAs
By
Abbas Ali (18jzele0237) – Group Leader
Abdullah Shah (18jzele0236)
Malik Abdul Moiz (18jzele0287)
1

Supervised by

Dr. Malik Umar Sharif

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Goal of our project
 The goal of our project is to design a system where
hardware and software work together to monitor real -
time stock data and implement an algorithm to
analyze the market to inform a user on whether they
should buy, sell, or hold the stock.

 To achieve the profit and lowest possible latency for

Interpreting market data feeds we make algorithm for
high frequency trading through FPGA.
3  How to program a Zed Board?

 To program a Zed Board, we must know about the ZYNQ Chip

inside it.
 ZYNQ Chip contains PS (Programming System) and PL
(Programming Logic)
 To communicate PS with PL, we have to know AXI-Interfaces.
4  How to program a Zed Board?

Programming of Processing System (PS)

 To program PS, we use SDK Software.
 PS is a Hard IP
 UART Port is used to code in PS

Programming of Programmable Logic (PL)

 To program PL, we use Vivado Software.
 PL is a Soft IP
 USB-JTAG Port is used to code in PL
5  Working in PS
 Code for PS in SDK platform given below
 #include <stdio.h>
 int main() {
 printf("Hello! Can anybody hear me?");
 }
6  Working in PL
 Verilog code creates a Logic in Vivado.
 Verilog Code given below
 module led (
input[7:0] switch,
output[7:0] led );
assign led=switch;
endmodule

LOGIC
7  Working in PL (cont.)

INPUT & OUTPUT PORT ASSIGNING INPUT & OUTPUT PIN ASSIGNING
8  Working in PL (cont.)
9  Hardware & Software Co-design

 To make a Hardware & Software co-design we need AXI-Interface

 AXI-Master initiates a transaction
 AXI-Slave respond to the initiated transaction
10  Hardware & Software Co-design
(cont.)
 Types of AXI-Interfaces
11  Hardware & Software Co-design
(cont.)

BLOCK DESIGN IN VIVADO SOFTWARE

12  Hardware & Software Co-design
(cont.)
 SDK code is given below to program PS
 #include "xparameters.h“
 #include<xil_io.h>
 int main()
 {
 Xil_Out8(0x41200000,0xFF);
 }
13  Hardware & Software Co-design
(cont.)

OUTPUT RESULT
14  Generation of Packets
 To generate packets, we have to use Ostinato Software.
 To check our Simulation Result on dummy packet.
15  Capturing of Packets
 Capture these generated Packets with Wire-Shark.

Interface of Wireshark (Capturing Packets)

16  Interface PS with PC
 Ethernet Port is used to transfer packets from PS to PC
 Enable ENET 0 port in PS
17  Interface PS with PC
18  Interface PS with PC
 Sending Packet from PS to PC
 Captured that packet in Wireshark
19  How Data Transfer?
 Data transfer used only two layers of OSI Model
 Data link layer and Physical layer are implemented in Ethernet Interface
 MAC implemented in PS
 PHY is implemented in External Marvell Chip
 Interface between MAC & PHY is MII (Media Independent Interface)
20  Transmission of Data
 DMA (Direct Memory Access) is introduce in which peripheral is no need to
take data from processor.
 Different Peripherals will directly access to the Memory and take data from
it our own desire.
 DMA control data transfer and processor free for other task, as a result the
performance of the processor increases.
 Processor finally receives an interrupt from the DMA controller (DMAC)
when the operation is done.
21  Transmission of Data (cont.)
 Direct memory access (DMA) is a FIFO-based method of transferring data
between an FPGA target and the host computer.
 DMA does not involve the host processor. Therefore, it is the fastest
available method for transferring large amounts of data between the FPGA
target and the host.
 The acronym FIFO stands for First In First Out.
 Data transfer occurs one element at a time. The first element in one buffer
is the first element transferred to the other buffer.
22 What work remains to be done?

 Sending Ethernet packets from PC to PS

 Sending same packets from PS to PL
 Apply trading algorithm on the stock market data
 After apply algorithm send back packets to PS
 Visualize that receive packets of PS in laptop using Wireshark
 Publication of paper.
TEAM

DR. UMAR SHARIF ABBAS ALI ABDULLAH SHAH MALIK ABDUL MOIZ
Supervisor Group Leader Group Member Group Member
Graduated from George Selected High frequency Selected High frequency Selected High frequency
Mason University with the trading on FPGA as a Final trading on FPGA as a trading on FPGA as a
Ph.D. degree in Electrical Year Project (FYP) with the Final Year Project (FYP) Final Year Project (FYP)
and Computer Engineering supervision of with the supervision of with the supervision of
in Summer 2017.
Dr. Umar Sharif Dr. Umar Sharif Dr. Umar Sharif

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 THANK YOU
&
ANY QUESTION
???
Abbas Ali

Abdullah Shah

Malik Abdul Moiz

+92 313 9346490

18JZELE0237@uetpeshawar.edu.pk