Developing High Throughput

communication interface for high

frequency trading on FPGAs
By
Abdullah Shah (18jzele0236)
Abbas Ali (18jzele0237)
Malik Abdul Moiz (18jzele0287)

Supervised by
Dr. Malik Umar Sharif
Goal of our project
 The goal of our project is to design a system where
hardware and software work together to monitor real -
time stock data and implement an algorithm to
analyze the market to inform a user on whether they
should buy, sell, or hold the stock.

 To achieve the profit and lowest possible latency for

Interpreting market data feeds we make algorithm for
high frequency trading through FPGA.
Introduction to HFT
 High Frequency trading
 Trading at a rapid rate
 Transactions of a large number of orders in a fractions of a
second
 Type of a Algorithmic trading/ Programming trading
 Use of algorithmic trading to react to market events faster
than the competition to increase profitability of trades
 Focus on low latency
 Typically short holding period about 22 seconds
 20th Century 21st Century

Traditional Trading Algorithmic Trading

Evolution of High Frequency Trading
From 20th century to 21st Century
 Concept of FPGA
 Scene 1
 Year 2010: I bought my computer and it had Microsoft office 2010
 Year 2016: Microsoft 2016 released
 How to upgrade my system?
 Just download the new software and install it.

 Scene 2
 Year 2010 : I bought my computer and it had 1 Gigabit Ethernet
interface
 Year 2016 : I want to upgrade 10 Gigabit Ethernet
 How to upgrade my system??
 Throw away the Old Ethernet card. Buy a new one and install it.
 Concept of FPGA

 Why two scenarios are different?

 First case is a software and second case is a hardware
and software is inherently flexible, but hardware is not.
 Imagine, how nice it would have been if I could
upgrade my hardware(to some extent) the same way I
upgrade my software
 It is the promise of Field Programmable Gate
Arrays(FPGA)
 Introduction to FPGA

F=Field • User or Designer on the Field

P=Programmable • Can be programmed again and again

G=Gate • Logic Gates

A=Array • Something describes in rows and columns

Introduction to FPGA
 Reprogrammable Chip contains thousands of Logic gates
 Software defined Hardware
 HDL language is used (VHDL or Verilog)

 Main Components
i. CLB (Configurable Logic Gates)
ii. Connection Blocks (Wires)
iii. Switch boxes
iv. Input/ Output Blocks
 Zed board Layout and interfaces
Front View of Zed board
 Hardware: Zynq Architecture
 Zynq Processing System
Why we use FPGA for HFT?

HFT system requires extremely low latency in

response to market updates which is achieved
by FPGA.
FPGA chips enable them to execute certain
types of trading algorithms up to 1000 times
faster than traditional software solutions.
 How to achieve Low Latency data
communication?

 Actually, low latency data communication is achieved

by using Gigabit Ethernet
 Based on LAN technology
 Provides a data rate of 1 billion bits per second or 1 GbE
 Uses the 802.3 Framing structure as standard
 Ranges upto 10GbE, 20GbE, 40GbE, 100 GbE
 Objectives
 Extract data from Stock Market
 Decode the Stock Market data
 First Fed Stock Market data into ZYNQ Chip (PS) through Ethernet
port
 Apply algorithm on FPGA (PL)
 Send Stock Market data from PS to PL
 Display the final Stock Market data on screen by using VGA port
of Zed Board.
 Publication of paper
  Methodology (Design)
 First we study how to design our project, in which way we implement our
project and how we test our project using back-testing software.
 Design
 To design our FYP Project, we involves the following step to complete our
project.
 Generation of Ethernet Traffic Packets
 First of all, we have to generate packets with the help of Software called
Ostinato. We have to use this software for generation of Ethernet packets
through this we will check our simulation result.
 Capture the Ethernet Traffic Packets
 Now, we have to capture these generated Ethernet Packets with the help
of Software called Wire-Shark.
 Filter out the Ethernet Traffic Packets
 Now, we have to filter out the desired packets which we need to transmit
for PS (Programming System) part of the Zynq Chip.
  Methodology (Design)
 Receiving the Ethernet Packets on PS
 Now, we are ready to generate Ethernet packets with the help of Ostinato
and check whether the generated packets are received on the PS part of
the Zynq chip successfully. This is our first main goal of this project to
received Ethernet generated packets on the PS (Programming system)
part of ZYNQ chip.
 Display the receiving Ethernet Packets on PS
 Now, if we received the Ethernet packets on PS, then our task is to display
these received packets on the VGA port.
 Interfacing PS with PL
 If we received data on PS then we have to send that data from PS into PL
(Programming Logic) through interface called AXI interface.
 In this way, we work on the PS (hardware part) as well as PL (Programming
Logic) which is actually FPGA forming the Zynq chip.
 Interfacing PS with PL
To communicate between PS and PL, we need AXI Interfaces
*AXI = Advances Extensible Interface
Methodology (Implementation)

Implementation of project involves

 First, find the best software for generating Ethernet Data packets.
 Now, we find a way to capture these generated Ethernet data
packets.
 After that, we have to receive that data on some Hard IP for that we
have to study the Architecture of PS (Programming System).
 Now, we also have to send that data to Soft IP for that we study the
Architecture of PL (Programming Logic) in order to interface PS with PL
we must know the AXI interface.
Methodology (Testing)
 First we have to implement this on PC using loop-back test on
Software simulation because if we get the desired/successful result
on the PC then we can easily implement the same logic and idea
on the hardware also known as Zynq chip.
 Testing of project involves the following steps
 First of all, we generate packets on PC using Ostinato.
 After that, TURN ON the Wireshark capture these generated
packets on the Wireshark and send it back to the PC.
 Now, if the PC received the same Ethernet generated packets
successfully which it sends earlier. So, we can we say or concluded
that our Loop-back test was successful and now we can try to send
these Ethernet generated packets to the PS then PL using AXI
interface.
 Project Planning
Distribution of work
 GANTT Chart
 Required Hardware & Software
 Hardware
 Pc/ Laptop
 Zed board
 Several Peripherals (Keyboard, Mouse, USB Micro Cables)
 Software
 Vivado for Programming Logic (PL)
 SDK for Processing System (PS)
 Python for Data Analyzation
 Ostinato for Generating Ethernet data packets
 Wire Shark for Data Capturing and Filtering
 C++
 Reference Papers
 [1] B. G. H. L. Christian Leber, "High Frequency Trading Acceleration using
FPGAs," in 21st International Conference on Field Programmable Logic and
Applications, 68131 Mannheim, Germany, 2011.
 [2] A. S. Gillis, "TechTarget," September 2021. [Online]. Available:
https://www.techtarget.com/searchnetworking/definition/Gigabit-Ethernet.
 [3] M. Trochimiuk, "Codilime," 30 April 2021. [Online]. Available:
https://codilime.com/blog/FPGA-programming-how-it-works-and-where-it-can-
be-used/.
 [4] S. A. B. A. S. Nikolaos Alachiotis, "EFFICIENT PC-FPGA COMMUNICATION OVER
GIGABIT ETHERNET," The Exelixis Lab, Department of Computer Science.
 [5] K. a. S. P. K. Shruthi Sangani (M.Tech), "Implementation Of Ethernet Based
Data Transfer," in International Research Publication House, Dept. of E.C.E (VLSI
Design) GITAM University, Number 1 (2015).
 [6] S. D. H. I. Tobias BECKER, "Network-level FPGA Acceleration of Low Latency
Market Data Feed Arbitration".
 [7] C. S. L.R. Doolittle, "FPGA COMMUNICATIONS BASED ON GIGABIT ETHERNET,"
2011.
 [8] B. G. H. L. Christian Leber, " “High Frequency Trading acceleration using FPG
s”," 2010.
TEAM

DR. UMAR SHARIF ABBAS ALI ABDULLAH SHAH MALIK ABDUL MOIZ
Supervisor Group Leader Group Member Group Member
Graduated from George Selected High frequency Selected High frequency Selected High frequency
Mason University with the trading on FPGA as a Final trading on FPGA as a trading on FPGA as a
Ph.D. degree in Electrical Year Project (FYP) with the Final Year Project (FYP) Final Year Project (FYP)
and Computer Engineering supervision of with the supervision of with the supervision of
in Summer 2017.
Dr. Umar Sharif Dr. Umar Sharif Dr. Umar Sharif
 THANK YOU
&
ANY QUESTION
???
Abbas Ali

Abdullah Shah

Malik Abdul Moiz

+92 313 9346490

18JZELE0237@uetpeshawar.edu.pk