FLIP FLOPS

By Unsa Shakir
 INTRODUCTION:

• Flip – flops have two stable states and hence they are
bistable multivibrators. The two stable states are High
(logic 1) and Low (logic 0).

• They can switch between the states under the influence of

a control signal (clock or enable) i.e. they can ‘flip’ to one
state and ‘flop’ back to other state.

• They are binary storage devices because they can store

binary data (0 or 1).
 INTRODUCTION:

• They are also known as signal change sensitive

devices which mean that the change in the level of
clock signal will bring change in output of the flip
flop.

• A Flip – flop works depending on clock pulses.

• Flip flops are also used to control the digital

circuit’s functionality. They can change the
operation of a digital circuit depending on the state
 CONVENTIONS

• The two outputs are complementary to each

other.

• If Q is 1 that is set Q’ to 0.

• If Q is 0, reset Q’ to 1. (Q and Q’ can’t be at the

same state simultaneously. If it happens, it will
violate the definition of the flip-flop and hence is
called undefined condition).
• Q is called the state of the flip-flop whereas Q’
is called complementary state of the flip-flop.

• When the output Q is either 0 or 1, it remains

in that state unless one or more inputs are
excited to effect the change on the output.
 FLIP-FLOPS

3 classes of flip-flops

• latches: outputs respond immediately while

enabled (no timing control)

• pulse-triggered flip-flops: outputs response to

the triggering pulse

• edge-triggered flip-flops: outputs responses to

the control input edge
 TYPES OF FLIPFLOPS

• S-RFlip-flop
• J-K Flip-flop
• D Flip-flop
• TFlip-flop
 S-R FLIP FLOP

• The S-R flip-flop is basic flip-flop among all the flip-

flops. All the other flip flops are developed after SR-flip-
flop.
• SR flip flop is represented as shown below
 S-R FLIP FLOP

• Any flip flop can be build using logic gates. NAND and NOR
gates were used as they are universal gates.
 The Basic SR Flip-flop with clock

The Basic SR Flip-flop

 Working

From the diagram it is evident that the flip flop has

mainly four states. They are

S=1, R=0 — Q=1, Q’=0

This state is also called the SET state.

S=0, R=1— Q=0, Q’=1

This state is k nown as the RESET state.

In both the states ,the outputs are just compliments

of each other and that the value of Q follows the
value of S.
S=0, R=0 — Q & Q’= Remember
If both the values of S and R are switched to 0,
then the circuit remembers the value of S and R in
their previous state.

S=1, R=1—Q=0, Q’=0 [Invalid]

• This is an invalid state because the values of
both Q and Q’are 0.
• They are supposed to be compliments of each
other. Normally, this state must be avoided.
 JK-FLIP FLOP

• The J-K flip-flop is operationally similar to the S-

R flip-flop.

• The J-K flip-flop is clock driven like the clocked

S-R flip-flop.

• The difference is that the J-K flip-flop will retain

its output status when two lows are present at
its inputs. Also, when both inputs are high, the
outputs will toggle on and off
 WORKING

• Q and Q' are feedback to the pulse-steering

NAND gates.
• No invalid state.
• Include a toggle (switch) state.
• J=HIGH (and K=LOW) - a SET state
• K=HIGH (and J=LOW) - a RESET state
• both inputs LOW - a no change
• both inputs HIGH - a toggle
• Toggling means ‘Changing the next state output to
complement of the present state output’

• Toggling will cause the output to complement

again and again.

• This complement operation continues until the

Clock pulse goes back to 0. Since this condition is
undesirable, we have to find a way to eliminate this
condition.

• This undesirable behavior can be eliminated by

Edge triggering of JK flip-flop or by using master
slave JK Flip-flops.
JK-FLIP FLOP
S=J.Q’
J-K FLIP FLOP TRUTH TABLE
R=K.Q
previous values present values
clk J K Q Q’ S R Q Q’
1 0 1 1 0 0 1 0 1
0 1 0 0 0 1
1 1 0 1 0 0 0 1 0
0 1 1 0 1 0
1 0 0 1 0 0 0 1 0 previous
values
0 1 0 0 0 1
1 1 1 1 0 0 1 0 1 compliment
of previous
0 1 1 0 1 0
values
 J-K FLIP FLOP TRUTH TABLE

summary
 D-FLIP FLOP

The D flip-flop is widely used. It is also known as a

"data" or "delay" flip-flop and negative edge
triggered flip flop.
By comparing R-S, J-K, and D flip-flops one can
see that the D flip-flop never has an unknown
state, unlike the R-S and J-K.

• single input D (data)

• D=HIGH - a SET state
• D=LOW - a RESET state
D-FLIP FLOP
D-FLIP FLOP TRUTH TABLE

CLK D J K Q Q’
1 1 0 1 0 1
1 1 1 0 1 0

J=Q
 T-FLIP FLOP

• A T flip flop is like JK flip-flop.

• These are basically a single input version of JK

flip flop.

• This modified form of JK flip-flop is obtained by

connecting both inputs J and K together.
•
• This flip-flop has only one input along with the
clock input.
clk T J K Q Q’ S R Q Q’
1 0 0 0 1 0 0 0 1 0 previous
values
0 1 0 0 0 1
1 1 1 1 1 0 0 1 0 1 compliment
of previous
0 1 1 0 1 0
values
 THE USE OF FLIP FLOP

• For Register Devices:

Flip flops can store a single bit of data i.e. 1 or 0.
Registers are used to store multiple bits of data. So
flip flops are used to design Registers. According to
digital electronics, a Register is a device which is
used to store the information.

• Data Transfer
The process of transferring the data from one
register to another register