Mahavir Swami College of Engineering & Tech, Surat

Digital Electronics (2131004)

Teaching Learning Plan

nd
B.E. 2 YEAR (Modified on 4th Feb 2014)

Course The students need to learn basic concepts of digital circuits and system which leads to
Objectives design of complex digital system such as microprocessors. The students need to know
combinational and sequential circuits using digital logic fundamentals. This is the first
course by which students get exposure to digital electronics world.
Course After learning the course the students should be able to
Outcomes 1. Explain about digital number systems and logic circuits.
2. The student should be able to solve logic function minimization.
3. The students should be able to differentiate between combinational and
sequential circuits such as decoders, encoders, multiplexers, de-
multiplexers, flip-flops, counters, registers.
4. They should be able to design using FSM.
5. The student should be able to compare the design using digital circuits and
PLDs.

Structure of the Curriculum

Course Course
Total Number of contact hours Per Week
Code Title
Total Credits
Lecture Tutorial Practical#
DIGITAL Hours
2131004 (L) (T) (P)
ELECTRONIC
4 0 2 6 6

Teaching and Examination Scheme:

Teaching Scheme Credits Examination Marks

Practical
Theory Marks Total
Marks
L T P C Marks
ESE PA
PA (M) ESE (V)
(E) (I)
PA ALA ESE OEP
4 0 2 6 70 20 10 20 10 20 150
L- Lectures; T- Tutorial/Teacher Guided Student Activity; P- Practical; C- Credit; ESE- End Semester Examination;
PA- Progressive Assessment
*PA (M): 10 marks for Active Learning Assignments, 20 marks for other methods of PA
# ESE Practical (V): 10 marks for Open Ended Problems, 20 marks for VIVA.
Note: Passing marks for PA (M) will be 12 out of 30.
Passing marks for ESE Practical (V) will be 15 out of 30.

ACTIVE LEARNING ASSIGNMENTS: Preparation of power-point slides, which include videos,

animations, pictures, graphics for better understanding theory and practical work – The faculty will
allocate chapters/ parts of chapters to groups of students so that the entire syllabus to be covered. The
power-point slides should be put up on the web-site of the College/ Institute, along with the names of
the students of the group, the name of the faculty, Department and College on the first slide. The best
three works should submit to GTU.
 Module wise Mapping

Sr. Module
TOPICS Module Outcome
No. Weightage
1 Binary Systems and Logic Circuits: Explain about digital number 5%
• The Advantage of Binary, Number Systems systems and logic circuits.
• The Use of Binary in Digital Systems, Logic
Gates
• Logic Family Terminology.
2 Boolean Algebra and Mapping Methods: The student should be able to 15%
• Boolean Algebra solve logic function
• Karnaugh Maps minimization.
• Variable Entered Maps
• Realizing Logic Function with Gates
• Combinational Design Examples.
3 Logic Function Realization with MSI Circuits: The student will able to Solve the 15%
• Combinational Logic with Multiplexers and problem of power flow through
Decoders any power system network.
• Standard Logic Functions with MSI Circuits
• Design Problem Using MSI Circuits.
4 Flip Flops, Counters and Registers: The students should be able to 15%
• Flip Flops and differentiate between
• its Applications combinational and sequential
circuits such as decoders,
encoders, multiplexers, de-
multiplexers, flip-flops, counters,
registers.
5 Introduction to State Machines: They should be able to design 5%
• The Need for State Machines using FSM.
• The State Machine
• Basic Concepts in State Machine Analysis.
6 Synchronous State Machine Design: They should be able to design 15%
• Sequential Counters using FSM.
• State Changes Referenced to Clock, Number
of State Flip-Flops
• Input Forming Logic, Output Forming Logic
• Generation of a State Diagram from a Timing
Chart
• Redundant States, General State Machine
Architecture
7 Asynchronous State Machines: They should be able to design 15%
• The Fundamental-Mode Model, using FSM.
• Problems of Asynchronous Circuits Basic
Design Principles
• An Asynchronous Design Example
8 Logic Families: The student should be able to 5%
• Transistor-Transistor Logic(TTL) compare the design using digital
• Emitter-Coupled Logic(ECL) circuits and PLDs
• MOSFET Logic, TTL Gates.
9 Programmable Logic Devices: The student should be able to 10%
• Introduction to Programmable Logic Devices, compare the design using digital
• Read-Only Memory, circuits and PLDs
• Programmable Logic Arrays (PLA),
• Programmable Array Logic (PAL),
• Combinational PLD-Based State Machines,
• State Machines on a Chip.
 Mahavir Swami College of Engineering & Tech, Surat
DIGITAL ELECTRONICS (2131004)

Digital Electronics Laboratory Lesson Plan

SEM: 3rd (_____________________) COURSE/COURSE CODE B.E: __________________________

TERM: ODD SUBJECT NAME: DIGITAL ELECTRONICS
STAFF NAME: Mr. Vivek Patel BATCH: _____________________________________________

Sr. Planned Actual

Experiment name Remark
No. Date Completed
1 Introduction of The Breadboard.
2 Verification and interpretation of truth tables
for AND, OR, NOT.
3 Verification and interpretation of truth tables
for NAND, NOR Exclusive OR (EX-OR),
Exclusive NOR (EX-NOR) Gates.
4 Realization of logic functions with the help of
universal gates-NAND Gate.
5 Realization of logic functions with the help of
universal gates-NOR Gate.
6 To study & verification of operation of
half and full adder.
7 To study & verification of operation of
half and full subtractor.
Faculty Name& sign HOD sign

Evaluation Sheet

ALA Viva PA
Unit Unit Name
(10 Marks) (20 Marks) Total (30)
1 Binary Systems and Logic
Circuits
2 Boolean Algebra and
Mapping Methods
3 Logic Function Realization
with MSI Circuits
4 Flip Flops, Counters and
Registers
5 Introduction to State
Machines
6 Synchronous State Machine
Design
7 Asynchronous State
Machines
8 Logic Families
9 Programmable Logic Devices
Average

Experiment Evaluation Sheet

Sr. Experiment OEP Viva PA

No. (10 Marks) (20 Marks) Total (30)
1 Introduction of The Breadboard.
2 Verification and interpretation of truth
tables for AND, OR, NOT.
3 Verification and interpretation of truth
tables for NAND, NOR Exclusive OR
(EX-OR), Exclusive NOR (EX-NOR)
Gates.
4 Realization of logic functions with the
help of universal gates-NAND Gate.
5 Realization of logic functions with the
help of universal gates-NOR Gate.
6 To study & verification of
operation of half and full adder.
7 To study & verification of
operation of half and full subtractor.
 8 To verify the function of 4 to 1
multiplexer using 74153 on Multisim
software.
9 To verify the function of 1 to 4 de-
multiplexer using 74156 on Multisim
software.
10 To design and implement encoder and
decoder using logic gates and study of
IC 7445 and IC 74147 To verify the
function of 1 to 4 de-multiplexer using
74156 on Multisim software.
Average

Faculty Name& sign HOD sign

Open Ended Problems

1. Design of combinational lock circuits with varying number of bits (For example 4, 8
…..)
2. Design of various types of counters.
3. Design of Arithmetic and Logic Unit using digital integrated circuits.
4. Design of digital integrated circuit tester
5. Measurement of logic family specifications.
6. Design project for example digital clock, digital event counter, timers, and various
multi-vibrator Circuits, small processor, ports or scrolling display.

Newely Added Experiments

• To verify the function of 4 to 1 multiplexer using 74153 on Multisim software.
• To verify the function of 1 to 4 de-multiplexer using 74156 on Multisim software.
• To design and implement encoder and decoder using logic gates and study of IC 7445
and IC 74147 To verify the function of 1 to 4 de-multiplexer using 74156 on Multisim
software.