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Ram & Rom
Ram & Rom
Solution:
A mod-5 counter counts from 0 to 4. Thus, following the steps given in article - designing of
synchronous counter, a mod-5 counter can be designed as:
Step 1: The number of flip-flops required to design a mod-5 counter can be calculated using the
formula: 2n >= N, where n is equal to no. of flip-flop and N is the mod number. In this case, the
possible value on n which satisfies the above equation is 3. Hence, the required number of flip-
flops is 3.
Step 3: We can draw the state diagram for mod-5 counter describing the state flow in current and
next state as:
Step 4: Using the excitation table of JK flip-flop, we need to obtain the flip-flop inputs
for each state that we obtained in the third step and now we will enter it into a table as:
Step 5: Making K-Map for each input combination and simplifying it to get the
minimized Boolean expression.
.
Step 6: Using the Boolean expressions obtained in step 5, now we will draw the required
counter circuit which can be shown as:
Solution:
A mod-10 counter counts from 0 to 9. Thus, following the steps given in the article - designing
of synchronous counter, a mod-10 counter can be designed as:
Step 1: The number of flip-flops required to design a mod-10 counter can be calculated using the
formula: 2n >= N, where n is equal to no. of flip-flop and N is the mod number. In this case, the
possible value on n which satisfies the above equation is 4. Hence, the required number of flip-
flops is 4.
Step 3: We can draw the state diagram for mod-10 counter describing the state flow in current
and next state as:
Step 4: Using the excitation table of T flip-flop, we need to obtain the flip-flop inputs for each
state that we obtained in the third step and now we will enter it into a table as:
Step 5: Making K-Map for each input combination and simplifying it to get the minimized
Boolean expression.
Step 6: Using the Boolean expressions obtained in step 5, now we will draw the required counter
circuit which can be shown as:
Synchronous 3 bit Up/Down counter
These types of counters fall under the category of synchronous controller counter.
Here the mode control input is used to decide whether which sequence will be
generated by the counter.
In this case, mode control input is used to decide whether the counter will perform up
counting or down counting.
Designing of such a counter is the same as designing a synchronous counter but the
extra combinational logic for mode control input is required.
Steps to design Synchronous 3 bit Up/Down Counter :
1. Decide the number and type of FF –
Here we are performing 3 bit or mod-8 Up or Down counting, so 3 Flip Flops are
required, which can count up to 23-1 = 7.
Here T Flip Flop is used.
2. Write excitation table of Flip Flop –
Excitation table of T FF
If there is a change in the output state of a flip flop (i.e. 0 to 1 or 1 to 0), then the
corresponding T value becomes 1 otherwise 0.
6. Find a simplified equation using k map –
Here we are finding the minimal Boolean expression for each Flip Flop input T using k map.
8. Timing Diagram –
The shift register, which allows serial input (one bit after the other through a single data line)
and produces a serial output is known as Serial-In Serial-Out shift register. Since there is only
one output, the data leaves the shift register one bit at a time in a serial pattern, th us the name
Serial-In Serial-Out Shift Register.
The logic circuit given below shows a serial-in serial-out shift register. The circuit consists of
four D flip-flops which are connected in a serial manner. All these flip-flops are synchronous
with each other since the same clock signal is applied to each flip flop.
The above circuit is an example of shift right register, taking the serial data input from the left
side of the flip flop. The main use of a SISO is to act as a delay element.
Serial-In Parallel-Out shift Register (SIPO) –
The shift register, which allows serial input (one bit after the other through a single data line)
and produces a parallel output is known as Serial-In Parallel-Out shift register.
The logic circuit given below shows a serial-in-parallel-out shift register. The circuit consists
of four D flip-flops which are connected. The clear (CLR) signal is connected in addition to the
clock signal to all the 4 flip flops in order to RESET them. The output of the first flip flop is
connected to the input of the next flip flop and so on. All these flip-flops are synchronous with
each other since the same clock signal is applied to each flip flop.
The above circuit is an example of shift right register, taking the serial data input from the left
side of the flip flop and producing a parallel output. They are used in communication lines
where demultiplexing of a data line into several parallel lines is required because the main use
of the SIPO register is to convert serial data into parallel data.
The shift register, which allows parallel input (data is given separately to each flip flop and in a
simultaneous manner) and produces a serial output is known as Parallel-In Serial-Out shift
register.
The logic circuit given below shows a parallel-in-serial-out shift register. The circuit consists
of four D flip-flops which are connected. The clock input is directly connected to all the flip
flops but the input data is connected individually to each flip flop through a multiplexer at the
input of every flip flop. The output of the previous flip flop and parallel data input are
connected to the input of the MUX and the output of MUX is connected to the next flip flop.
All these flip-flops are synchronous with each other since the same clock signal is applied to
each flip flop.
A Parallel in Serial out (PISO) shift register us used to convert parallel data to serial data.
The shift register, which allows parallel input (data is given separately to each flip flop and in a
simultaneous manner) and also produces a parallel output is known as Parallel-In parallel-Out
shift register.
The logic circuit given below shows a parallel-in-parallel-out shift register. The circuit consists
of four D flip-flops which are connected. The clear (CLR) signal and clock signals are
connected to all the 4 flip flops. In this type of register, there are no interconnections between
the individual flip-flops since no serial shifting of the data is required. Data is given as input
separately for each flip flop and in the same way, output also collected individually from each
flip flop.
A Parallel in Parallel out (PIPO) shift register is used as a temporary storage device and like
SISO Shift register it acts as a delay element.
If we shift a binary number to the left by one position, it is equivalent to multiplying the
number by 2 and if we shift a binary number to the right by one position, it is equivalent to
dividing the number by 2.To perform these operations we need a register which can shift the
data in either direction.
Bidirectional shift registers are the registers which are capable of shifting the data either right
or left depending on the mode selected. If the mode selected is 1(high), the data will be shifted
towards the right direction and if the mode selected is 0(low), the data will be shifted towards
the left direction.
The logic circuit given below shows a Bidirectional shift register. The circuit consists of four
D flip-flops which are connected. The input data is connected at two ends of the circuit and
depending on the mode selected only one and gate is in the active state.
Shift Register Counter
Shift Register Counters are the shift registers in which the outputs are connected back to the
inputs in order to produce particular sequences. These are basically of two types:
Ring Counter –
A ring counter is basically a shift register counter in which the output of the first flip flop is
connected to the next flip flop and so on and the output of the last flip flop is again fed
back to the input of the first flip flop, thus the name ring counter. The data pattern within
the shift register will circulate as long as clock pulses are applied.
The logic circuit given below shows a Ring Counter. The circuit consists of four D flip-
flops which are connected. Since the circuit consists of four flip flops the data pattern will
repeat after every four clock pulses as shown in the truth table below:
The main advantage of Johnson counter is that it only needs n number of flip-flops
compared to the ring counter to circulate a given data to generate a sequence of 2n states.
Applications of shift Registers –
The data that is required to be stored inside ROM is written during manufacturing phase. It stores
such programs that are essential for the booting process of the computer. It generally cannot be
altered. However, technologies are available to program these types of ROM.
Fig.1 – Classification of Primary Memory
A ROM operates like an array. ROM chips contain a grid of rows and columns to turn ON or
OFF. It uses a diode to connect the lines if the value is 1. If the value is 0, then these lines are not
connected at all. Each element of the array corresponds to one storage element in the memory
chip.
The address input to the chip is employed to pick out a specific memory location (corresponding
to the array index). The value read from the memory chip corresponds to the contents of the
selected element of the array.
Fig.2 – Diode Grid in Read Only Memory (ROM)
ROM consists of two basic components- Decoder and OR gates. In ROM, the input to decoder
will be in binary form and output will be its decimal equivalent. All the OR Gates present in the
ROM will take decoders output as their input.
ROM is differentiated on the basis of methods used to write data on ROM chips and the number
of times they can be written. It can be classified into following types : –
MROM stands for Mask Read Only Memory. It is a memory chip that is manufactured with its
contents. These are inexpensive and are the very first ROMs which were hard wired devices that
contain a pre-programmed set of data or instructions.
These chips contain a software mask that is burned onto the chip during design phase of the
semiconductor manufacturing process.
The specification of the ROM is taken by the manufacturer from its customer in tabular form and
in a particular format. The manufacturer then makes the corresponding mask for the paths to
produce the desired output.
The main advantage of Mask Read-Only Memory (MROM) is its low production cost. The cost
of IC depends on its size, per bit. Mask ROM is more compact. It is significantly cheaper than
any other kind of secondary memory when large quantities of same ROM are manufactured.
Design errors are costly i.e. if an error in the code is detected, the MROM is useless and must be
replaced in order to change the code. The life expectancy of MROM is also short, hence requires
frequent replacement.
The process of programming a PROM is called burning the PROM. There are tiny fuses in a
PROM chip which are burnt open during programming. The data can be programmed only once
and cannot be altered. So it is called one- time programming device.
The programming can be done using many types of software and does not rely on hard
wiring of the program to the chip.
Since it is not possible to un-blow the fuse, so the authenticity of the data remains intact
and it is impossible to remove or alter the contents.
The biggest disadvantage of PROM is that the data once burnt cannot be erased or changed when
detected with errors.
EPROM can be erased by exposing it to ultra violet light for a particular length of time using an
EPROM eraser. After exposing, the chip returns to its initial state and can be reprogrammed.
This procedure can be carried out many times but repeated erasing and rewriting can eventually
render the chip useless. Once written, data can be retained for about 10 years.
It is non-volatile.
It can be erased and re -programmed.
It is cost effective as compared to PROM.
The static power consumption is high as the transistors used have higher resistance.
It is not possible for a particular byte to be erased, instead the entire content is erased.
UV based EPROM takes time to erase the content.
The erasing and programming of data takes 4 to 10 milliseconds. Any byte can be erased at a
time instead of the entire chip. The chip can be erased and re programmed for around ten
thousand times, though the process is flexible but slow.
Different voltages are required for erasing, reading and writing the data.
The data retention period of EEPROM is limited i.e 10 years approx.
EEPROM devices are expensive compared to others.
The latest technology computers use BIOS stored on a flash memory chip, called as flash
BIOS.
Modems, pen drives, small cards use flash ROM.
Advantages of Flash Read Only Memory (Flash ROM)
RAM (Random Access Memory) is the internal memory of the CPU for storing data, program,
and program result. It is a read/write memory which stores data until the machine is working.
As soon as the machine is switched off, data is erased.
Access time in RAM is independent of the address, that is, each storage location inside the
memory is as easy to reach as other locations and takes the same amount of time. Data in the
RAM can be accessed randomly but it is very expensive.
RAM is volatile, i.e. data stored in it is lost when we switch off the computer or if there is a
power failure. Hence, a backup Uninterruptible Power System (UPS) is often used with
computers. RAM is small, both in terms of its physical size and in the amount of data it can
hold.
RAM is of two types −
Static RAM (SRAM) is a type of random access memory that retains its state for data bits or
holds data as long as it receives the power. It is made up of memory cells and is called a static
RAM as it does not need to be refreshed on a regular basis because it does not need the power to
prevent leakage, unlike dynamic RAM. So, it is faster than DRAM.
It has a special arrangement of transistors that makes a flip-flop, a type of memory cell. One
memory cell stores one bit of data. Most of the modern SRAM memory cells are made of six
CMOS transistors, but lack capacitors. The access time in SRAM chips can be as low as 10
nanoseconds. Whereas, the access time in DRAM usually remains above 50 nanoseconds.
Furthermore, its cycle time is much shorter than that of DRAM as it does not pause between
accesses. Due to these advantages associated with the use of SRAM, It is primarily used for
system cache memory, and high-speed registers, and small memory banks such as a frame buffer
on graphics cards.
The Static RAM is fast because the six-transistor configuration of its circuit maintains the flow
of current in one direction or the other (0 or 1). The 0 or 1 state can be written and read instantly
without waiting for the capacitor to fill up or drain. The early asynchronous static RAM chips
performed read and write operations sequentially, but the modern synchronous static RAM chips
overlap read and write operations.
Long life
No need to refresh
Faster
Used as cache memory
Large size
Expensive
High power consumption
Dynamic Ram (DRAM) is also made up of memory cells. It is an integrated circuit (IC) made of
millions of transistors and capacitors which are extremely small in size and each transistor is
lined up with a capacitor to create a very compact memory cell so that millions of them can fit on
a single memory chip. So, a memory cell of a DRAM has one transistor and one capacitor and
each cell represents or stores a single bit of data in its capacitor within an integrated circuit.
The capacitor holds this bit of information or data, either as 0 or as 1. The transistor, which is
also present in the cell, acts as a switch that allows the electric circuit on the memory chip to read
the capacitor and change its state.
The capacitor needs to be refreshed after regular intervals to maintain the charge in the capacitor.
This is the reason it is called dynamic RAM as it needs to be refreshed continuously to maintain
its data or it would forget what it is holding. This is achieved by placing the memory on a refresh
circuit that rewrites the data several hundred times per second. The access time in DRAM is
around 60 nanoseconds.
Characteristics of Dynamic RAM
SRAM DRAM
Its memory cell is made of 6 transistors. Its memory cell is made of one transistor
So its cells occupy more space on a chip and one capacitor. So, its cells occupy less
and offer less storage capacity space on a chip and provide more memory
(memory) than a DRAM of the same than a SRM of the same physical size.
physical size.
It is more expensive than DRAM and is It is less expensive than SRAM and is
located on processors or between a mostly located on the motherboard.
processor and main memory.
It has a lower access time, e.g. 10 It has a higher access time, e.g. more than
nanoseconds. So, it is faster than 50 nanoseconds. So, it is slower than
DRAM. SRAM.
It is faster than DRAM as its memory It is not as fast as SRAM, as its memory
cells don't need to be refreshed and are cells are refreshed continuously. But still,
always available. So, it is mostly used in it is used in the motherboard because it is
registers in the CPU and cache memory cheaper to manufacture and requires less
of various devices. space.
Its cycle time is shorter as it does not Its cycle time is more than the SRAM's
need to be paused between accesses and cycle time.
refreshes.