Faculty of Engineering and Technology

Department of Electrical and Computer Engineering

ENCS2301, FUNDAMENTALS OF ELECTRONICS AND DIGITAL SYSTEMS
Final Exam
Date: 27/2/2022 Student Name:
Instructor: Ahmad Alyan Student #:

Please solve the all questions within 150 min. Show all the steps as possible as you can.
Q1) Choose the correct answer (30 marks)
1- The Boolean expression of NAND is the same as:
a) ̅ b) ̅ + c) + d) +
2- Which of these flip – flops cannot be used to construct a serial shift register?
a) D – flip flop b) SR flip – flop c) T flip – flop d) JK flip – flop
3- Which of the following options correctly represents the consensus law of Digital Circuits?
a) + ̅ + = + ̅ b) ̅ + ̅ + = + ̅
c) + ̅ + = + d) ̅ + ̅ + = +
4- What frequency division of the pulsed clock signal can be obtained by connecting 4 flip –
flops in cascade?
a) 2 b) 4 c) 8 d) 16
5- Which of the following options are correct for a 4×1 multiplexer?
a) It has four 3 – input AND gates b) It has four 2 – input AND gates
c) It has one 3 – input AND gate d) It has one 3 – input AND gate
6- Which of these pins will allow to activate and deactivate a Decoder?
a) Enable pin b) Selection pin c) Logic pin d) Preset pin
7- How many (AND, OR and XOR) gates are required for the configuration of full adder?
a) (1, 2, 2) b) (2, 1, 2) c) (3, 1, 2) d) (4, 0, 1)
8- Most demultiplexers facilitate which type of conversion?
a) Decimal-to-hexadecimal b) Single input, multiple outputs
c) AC to DC d) Odd parity to even parity
9- How can parallel data be taken out of a shift register simultaneously?
a) Use the Q output of the first FF b) Use the Q output of the last FF
c) Tie all of the Q outputs together d) Use the Q output of each FF
10- If two inputs are active on a most significant encoder, which will be coded on the
output?
a) The higher value b) The lower value c) Neither of the inputs d) Both of the inputs
11- Design a 16-to-1 multiplexer using from tow 8-to-1 multiplexer at least need:
a) AND gate b) Inverter gate c) a + b d) impossible
12- If F(A, B, C, D) = Σm(0, 1, 2, 5, 7, 8, 9, 10, 13, 15) it is true that:
a) ̅ = 1 b) ̅ ̅ = 0 c) =0 d) None of previous
13- Which transistor is preferred for applications of High power?
a) BJT b) UJT c) MOSFET d) JFET
14- An SCR is sometimes called …………
a) Triac b) Diac c) BJT transistor d) Thyristor

15- If the input of the circuit beside V1=0.5V the output will
be:
a) -5.5V b) 5.5V c) 5V d) -5V

16- For the circuit beside the output will be:

a) 1.05V b) -0.35V
c) 0.35V d) -1.05V

17- The circuit beside represented by:

a) = + b) +
c) = ⨁ d) + )

18- For the circuit beside represented by its true:

a) sw1=on and sw2=off rotate the motor CW.
b) sw1=off and sw2=on rotate the motor CCW.
c) sw1=on and sw2=on increase motor speed.
d) Both (a) and (b) can be true

19- An SCR is turned off by …………….

a) Reducing anode voltage to zero b) Reducing gate voltage to zero
c) Reverse biasing the gate d) None of the these

20- A TRIAC is used as :

a) Unidirectional power switch b) Bidirectional power switch
c) Unidirectional small signal switch d) Bidirectional small signal switch
Q2) a) Derive the function Q and minimize it using a boolean function minimization and plot
the equivalent representation. (12 marks)

A
B Q
C

+ A⨁C) =
+ C + AC + AC)
= + AC + AAC + AAC
= + AC = + C) =
A
B Q
C

b) Write system Verilog code for the above circuit (8 marks)

module AND_NAND_gate_level(output Q, input A, B,C);
wire Y,Yd;
and(Yd, B, C);
not(Y, Yd);
and(Q, Y, A);
endmodule
Input outp
Q3) Find Boolean function using k-map for this truth table: (10 A B C D W
marks) 0 0 0 0 1
C 0 0 0 1 1
0 0 1 0 0
1 1 1 0
0 0 1 1 1
0 0 1 0 0 1 0 0 0
B 0 1 0 1 0
0 1 1 0
A 0 1 1 0 0
1 1 0 0 0 1 1 1 1
D 1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
̅+ ̅ 1 0 1 1 0
= +
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
b) Use 74VHC161 4-Bit Binary Counter with Asynchronous Clear to count from 2 to 13 in a
loop with minimum gates (10 marks).

0
+5

+5

Ck

+5

(Bonus) Use the same counter to count odd only 3-13 in a loop. (3 marks) No Change Just
LSB (Q0) we replace it by 1
Q4) a) Minimize state diagram and redraw it. (8 marks)
b) Design a counter with T flip-flops that counts numbers (0,2,5,7) in loop, show the state
diagram, truth table, k-map. Finally draw the circuit. (12 marks)
x2 x1 x0 y2 y1 y0 T2 T1 T0
0 000 010 0 0 0 0 1 0 0 1 0
2 010 101 0 1 0 1 0 1 1 1 1
5 101 111 1 0 1 1 1 1 0 1 0
7 111 000 1 1 1 0 0 0 1 1 1

T2 x1 T1 x1 T0 x1
0 X X 1 1 X X 1 0 X X 1
x2 X 0 1 X x2 X 1 1 X x2 X 0 1 X
x0 x0 x0

=
=1
=
SET
Q0
J Q

K CL R Q
Y0

SET
Q1
J Q

K Q
1
CL R

Y1
Q2
SET
J Q

K CL R Q
Y2

Ck

Q6) a) Write System Verilog code for JK flip-flop with asynchronous reset (10 marks)
module FJKRSE(J,K,Clk,R,S,CE,Qout);

input J,K; //inputs

input Clk; //Clock
input Reset; //synchronous reset (Res)
input R; //synchronous reset (R)
input S; //synchronous set (S)
input CE; //clock enable (CE)
output Qout; //data output (Q)

//Internal variable
reg Qout;
if(Res == 1) //reset has highest priority.
Qout = 0;
else
always@ (posedge(Clk)) //Everything is synchronous to positive
edge of clock
begin
if(R == 1) //reset has highest priority.
Qout = 0;
else
if(S == 1) //set has next priority
Qout = 1;
else
if(CE == 1) //J,K values are considered
 only when CE is ON.
if(J == 0 && K == 0)
Qout = Qout; //no change
else if(J == 0 && K == 1)
Qout = 0; //reset
else if(J == 1 && K == 0)
Qout = 1; //set
else
Qout =
~Qout; //toggle
else
Qout = Qout; //no change
end

endmodule

b) Find the output of this circuit and show pulse

width if R1=10kΩ R2=22kΩ and C=100µ (5 marks)
= . + )
= .
= . + )

= . + ) = .
= . = .

= = .
. + .

Ahmad Alyan