NAME:- KRUSHNA WARANG

TE ELEC
ROLL NO:- 63

Experiment No - 10
AIM:.PIC 18 Support Devices: ADC module

THEORY:

BLOCK DIAGRAM OF ADC MODULE of PIC MICROCONTROLLER:

FEATURES OF ADC:

FLASH METHOD
This type of A/D converter utilizes 2N-1 comparators (for an N bit converter) to

compare the analog signal with successive reference voltages. The results are then

converted into digital format using an encoder.

Features:

● Analog signals are converted into digital signals directly (since the
comparators themselves are the sampling devices), making a Sample and
Hold circuit unnecessary.
● This allows for extremely fast conversion (with sampling frequencies above
1GHz possible).
● However, the relatively larger size and power consumption (due to the
number of comparators required: 2N-1) limit resolution to around 8 bits.
PIPELINE METHOD:

In the case of a 1.5bit/stage configuration, the following processes are repeated in

order from Stage 1 that determines MSB via pipeline operation (VREF: Reference

Voltage).

● Analog input is sampled (using an S&H circuit)

● At the same time the analog input is converted by an A/D converter into a
3-value digital format (1.5bit). (Here the digital output stage is defined.)
● Analog input ≦-VREF/4 → D="00"
● -VREF/4 ＜Analog input ≦+VREF/4 → D="01"
● +VREF/4 ＜Analog input →D="10"
● These digital values are then converted into analog values using a digital to
analog converter (DAC).
● D="00" → DAC output：-VREF/2
● D="01" → DAC output：0
● D="10" → DAC output：+VREF/2
● The negative DAC output voltage is amplified (x2) and output to the next
stage.
Once processing of Stage N that determines LSB is completed, the delay between

each stage is corrected then digital conversion completed by adding the respective

digital output.
Characteristics:

● High resolution enabled (up to 16bit)

● High-speed conversion possible (200MHz max. sampling frequency)
● There is a necessary wait time until the digital signal is output (based on
bipolar operation), making this impractical for applications requiring real-time
processing (i.e. control).

APPROXIMATION METHOD:

This method compares the sampled analog input with the converter's output in

succession, starting with the MSB.

● The analog input signal is sampled (S&H)

● A successive approximation register (SAR), which is designed to supply an
approximate digital code to the internal DAC, is initialized so that the most
significant bit (MSB) is set to '1'.
● The digital values from the SAR are converted into equivalent analog values by
the internal DAC.
● The sampled input voltage is compared with the DAC output voltage.
 ● If the sampled voltage > DAC output voltage → MSB = 1
● If the sampled voltage < DAC output voltage → MSB = 0
The digital conversion is completed by repeating the operation up to LSB.

Characteristics:

● High resolution conversion possible (up to 18bit)

● Since a clock cycle is required (resolution + α), conversion speed is moderate
(10MHz max. sampling frequency)
● Good response. Connecting a multiplexer to the input makes it easy to switch
analog signals.

ADC REGISTERS:

PIC ADC has 4 registers :

● ADCON0 – ADC Control Register 0
 ● ADCON1 – ADC Control Register 1
● ADRESH – ADC Result High Register
● ADRESL – ADC Result Low Register

ADCON0 Register:

● ADCS1 and ADCS2 are used to select A/D Conversion Clock. It should be
selected in accordance with the device clock.
● CH2, CH1 and CH0 are used to select one of the analog input channels out of
eight channels.
● GO/DONE is the A/D Conversion Status bit. Setting this bit initializes A/D
Conversion and will be automatically cleared when the conversion is
complete.
● ADON is used to switch on/off the ADC Module. When it is 1, the ADC Module
turns ON and when it is 0, the ADC Module will be OFF.

ADCON1 Register:

● ADFM is the ADC Result Format select bit. Two 8 bit registers (ADRESH and
ADRESL) are provided to store the 10-bit result of A/D Conversion, thus we
needn't use 6 bits. When ADFM is 1, the result will be right justified, ie Most
Significant Bits of ADRESH will be read as 0. When ADFM is 0, the result will be
left justified, i.e. Least Significant Bits of ADRESL will be read as zero.
● ADCS2 is used to select the A/D Conversion Clock in association with ADCS1
and ADC2 of the ADCON0 register.
● PCFG3 – PCFG0 are the A/D Port Configuration Control bits. Each pin among
AN0 – AN7 is configured as analog, digital or reference voltage inputs according
to the status of these configuration bits as given below.
 PCFG
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREF* VREF- C/R
<3-0>
00D0 A A A A A A A A VDD VSS 8/0
oooz A A A A VnI=F+ A A A AN3 Vss 7/1
oolo D D D A A A A A VDD VSS 5/0
OOIT D D D A VREF* A A A AN3 Vss 4/1
oloo D D D D A D A A VDD vss 3/0
oloz D D D D VRI=F+ D A A AN3 Vss 2/1
out D D D 0 D D 0 D — — 0/0
1oOo A A A A VREF* VRI=F— A A AN3 AN2 6/2
1oOT D D A A A A A A VDD Vss 6/0
1010 D D A A VREr+ A A A AN3 Vss 5/1
both D D A A VREF* A A AN3 AN2 4/2
11Do D D D A VREF• VREF— A A AN3 AN2 3/2
11Dz D D D D VREF+ VREF- A A AN3 AN2 2/2
1110 D D D D D D D A VDD V5s 1/0
1111 D D D D VREF+ VpEF- D A AN3 AN2 1/2
A = Analog input D = Digital I/O

C/R = # of analog input channels/# of A/D voltage references