INDIAN INSTITUTE OF TECHNOLOGY BOMBAY

ELECTRICAL ENGINEERING DEPARTMENT

MidSemester Examination

Wednesday EE 671 VLSI Design Time: 0900-1100

Oct. 07, 2020 Autumn Semester 2020 Marks: 30
Quantitative answers should be accurate to 0.1%

Q–1 Use the simple transistor model (with perfect saturation and no bulk effect) for this
question. We want to compare the current ID1 drawn by a single nMOS transistor
and ID2 drawn by two series connected nMOS transistors (with identical geometry and
parameters as the single nMOS). The gate and drain voltages are the same for the single
transistor and the series connected pair as shown. The gate voltage is high enough to
turn on all transistors. Currents are to be computed using transistor equations
and not by analogy to equivalent resistors.

VD VD
ID1 ID2
Mn2
VG Mn1 VG
Vx
Mn3

a) In what mode are the transistors (linear or saturated) as we sweep VD from 0 to a

value much higher than VG ? Specify the drain voltages at which the mode of some
transistor will change and tabulate their modes of operation for different ranges of
VD with respect to VG and for a given threshold voltage VT n .
Soln. 1-a)
• Clearly, Mn1 is in linear mode till VD reaches VG − VT n . Also, Mn1 will be
saturated for VD ≥ VG − VT n .
• Since both Mn2 and Mn3 are on, we must have VG − Vx ≥ VT n . Therefore,
Vx < VG − VT n . But Vx is the drain-source voltage for Mn3 . So Mn3 is always
in linear mode.
• VDS for Mn2 is VD − Vx while its gate-source voltage is VG − Vx . Therefore, it
will be saturated whenever

VD − Vx ≥ VG − Vx − VT n or when VD ≥ VG − VT n

. Thus, Mn2 and Mn1 are always in the same mode.

Condition Mn1 Mn2 Mn3

VD ≤ VG − VT n Linear Linear Linear
VD ≥ VG − VT n Saturated Saturated Linear

– [2]

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 b) Derive expressions for the voltage Vx at the source of Mn2 and drain of Mn3 for
all combinations of modes of Mn2 and Mn3 in terms of VD , VG and VT n .
If VG = 2.4V and VT n = 0.4V, tabulate values of Vx for VD = 1.0V, 1.5V, 2.0V,
2.5V and 3.0V.
Soln. 1-b) For 0 ≤ VD ≤ VG − VT n , all three transistors are in their linear mode. Since
Mn2 and Mn3 are in series, their currents must be equal. This gives
1 1
   
Kn (VG − Vx − VT n )(VD − Vx ) − (VD − Vx )2 = Kn (VG − VT n )Vx − Vx2
2 2
We define V1 ≡ VG − VT n . Then,
1 1
(V1 − Vx )(VD − Vx ) − (VD − Vx )2 = V1 Vx − Vx2
2 2
1 1
Or V1 VD − Vx VD − V1 Vx + Vx2 − (VD2 + Vx2 − 2VD Vx ) = V1 Vx − Vx2
2 2
1
This leads to Vx2 − 2V1 Vx + V1 VD − VD2 = 0
2
We can solve this quadratic equation to give
q
4V12 − 4(V1 VD − 12 VD2 )
s
2V1 ± 1
Vx = = V1 ± V12 − V1 VD + VD2
2 2
Since Vx < VG − VT n , the negative sign must be chosen.
s
1
Then Vx = V1 − V12 − V1 VD + VD2
2
s
1
Or V1 (V1 − VD ) + VD2
Vx = V1 −
2
It is interesting to evaluate this at VD = V1 = VG − VT n when Mn2 is at the edge
of saturation. At this value of VD , we get
!
1
Vx = V1 1− √
2

For VD ≥ VG − VT n , Mn2 is in saturation, while Mn3 is in linear mode. Since the

two are in series, their currents must be equal. Therefore,
Kn 1
 
(VG − Vx − VT n )2 = Kn (VG − VT n )Vx − Vx2
2 2
1
 
This gives 2
(VG − Vx − VT n ) = 2 (VG − VT n )Vx − Vx2
2
Defining V1 ≡ VG − VT n , we get (V1 − Vx )2 = 2V1 Vx − Vx2
Therefore V12 + Vx2 − 2V1 Vx = 2V1 Vx − Vx2 So, 2Vx2 − 4V1 Vx + V12 = 0
q s
4V1 ± 16V12 − 8V12 V12
This can be solved to give Vx = = V1 ±
4 2
2
 Again, since Vx must be < VG − VT n , the negative sign should be chosen.
! !
1 1
So Vx = V1 1− √ = 1 − √ (VG − VT n )
2 2
√
Thus the voltage Vx remains constant at (1 − 1/ 2)(VG − VT n ) for VD ≥ VG − VT n .
This value matches with the solution for linear mode at the edge of saturation, as
indeed it should.
Numerical values for Vx :
VG = 2.4V, VT n = 0.4V. So V1 = 2.0V. Mn √ 2 will be saturated for VD ≥ 2.0V
and q
for these values of VD , Vx = 2(1 − 1/ 2) = 0.5858V. For VD < 2.0V, Vx =
2 − 2(2 − VD ) + VD2 /2. So for VD = 1V, Vx = 0.4189V and for VD = 1.5V,
Vx = 0.5423.
VD 1.0 1.5 2.0 2.5 3.0
Vx 0.4189 0.5423 0.5858 0.5858 0.5858

– [4]
c) Find the ratio ID1 /ID2 for all combinations of modes of Mn1 , Mn2 and Mn3 .
Soln. 1-c) For VD ≤ VG − VT n , Mn1 , Mn2 as well as Mn3 are in linear mode. So,
1
ID1 = Kn (V1 VD − VD2 )
2
ID2 can be computed as the current through Mn3 .
1
ID2 = Kn (V1 Vx − Vx2 )
2
The quadratic equation for Vx was
1
Vx2 − 2V1 Vx + V1 VD − VD2 = 0
2
1 1 1
 
Therefore V1 Vx − Vx2 = V1 VD − VD2
2 2 2
So, current through Mn2 and Mn3 is
1 Kn 1
 
ID2 = Kn (V1 Vx − Vx2 ) = V1 VD − VD2
2 2 2
The current through Mn1 in linear mode is
1
 
ID1 = Kn V1 VD − VD2
2
Thus the current through the series connected transistors Mn2 and Mn3 is half of
that thorough the single transistor Mn1 with identical geometry.
This can be shown in another way: Since the currents through Mn2 and Mn3 must
be equal, the sum of their currents must equal 2ID2 .
1 1
   
2ID2 = Kn (V1 − Vx )(VD − Vx ) − (VD − Vx )2 + Kn (V1 Vx − Vx2
2 2
3
 2ID2 1 1
Therefore = (V1 − Vx )(VD − Vx ) − (VD − Vx )2 + V1 Vx − Vx2
Kn 2 2
2ID2 1 1
So = V1 VD − Vx VD − Vx V1 + Vx2 − (VD2 + Vx2 − 2VD Vx ) + V1 Vx − Vx2
Kn 2 2
All terms involving Vx cancel and we are left with
2ID2 1 Kn 1
 
= V1 VD − VD2 or ID2 = V1 VD − VD2
Kn 2 2 2
This establishes that for VD ≤ VG − VT n , the current through series connected Mn2
and Mn3 is half of that through Mn1 .
For VD ≥ VG − VT n , Mn1 and Mn2 are saturated, while Mn3 is in linear mode.
Under these conditions,
Kn 2
ID1 = V
2 1

√
!
1
Since Mn2 is saturated, Vx = V1 1− √ and so, V1 − Vx = V1 / 2
2

Using this, current through Mn2 can be calculated.

Kn Kn V12 Kn 2
ID2 = (V1 − Vx )2 = whereas ID1 = V
2 2 2 2 1
So, in saturation also, the current through Mn2 and Mn3 is half as much as that
through Mn1 .
Thus, at all operating voltages, current through series connected Mn2 and Mn3 is
half as much as that through Mn1 .
(This establishes the validity of the series rule even for non-linear I-V relationships).
– [4]

Q–2 We want to generate the function x.(y + z) + y.z in a single stage of a CMOS static
style logic gate by scaling transistor geometries from a reference inverter, using series
parallel rules. Width of the n channel transistor in the reference inverter is taken as the
unit of width. Width of the p channel transistor is γ times this unit to compensate for
the mobility difference between electrons and holes. Wiring and self capacitance delays
are to be ignored. The delay of a reference inverter driving another is τ .

a) Draw a transistor level schematic for this gate, specifying the width of each tran-
sistor such that the output drive of the gate is the same as that for the reference
inverter (for the worst case input logic value) and the capacitive loading on the
inputs is minimized.
Verify this using a simple equivalent resistor analogy.
Soln. 2-a) The figure below gives the CMOS implementation:

4
 VDD
y Mp4 z Mp5
3γ 3γ

z Mp2
x Mp1 3γ
1.5γ y
Mp3
3γ Out

x Mn1 z Mn4 y
2 2
Mn2 Mn3
y z Mn5
2 2 2

x.(y+z) is implemented as x (MN1) in series with y and z (Mn2 and Mn3) in

parallel for nMOS transistors and x (MP1) in parallel with y and z (MP2 and
MP3) in series for pMOS transistors. The term + y.z is implemented for nMOS
transistors as y and z transistors (Mn4 and MN5) in series and this block in parallel
with the x.(y+z) block. For pMOS, we put y and z (MN4 and MN5) in parallel
and this block is placed in series with the x.(y+z) block.
Let the equivalent resistance of the single n or p channel transistor in the reference
inverter be R.
In the worst case for charge up, we have 3 transistors (Mp3, Mp2 and Mp5) or
(Mp3, Mp2 and Mp4) in series. Each of these should have a resistance of R/3
for the charge path to be equivalent to the drive of the reference inverter. Hence
Mp2, Mp3, Mp4 and Mp5 should have a width of 3γ. The other charge up path
is through Mp4 and mp1. Width of Mp4 is already decided as 3γ. Thus, for the
path (Mp4, Mp1) To be equivalent to a single p channel transistor of the reference
inverter, Mp1 should have a width of 1.5γ.
Verification:
Now the charge paths (Mp3, Mp2 and Mp5) or (Mp3, Mp2 and Mp4) have a net
equivalent resistance of (R/3 + R/3 + R/3) = R. The other charge path of (Mp4,
Mp1) or (Mp5, Mp1) has a resistance of (R/3 + 2R/3) = R. Thus for all logic
combinations enabling a charge up to VDD , the net equivalent resistance is the
same as that for the reference inverter.
For the nMOS transistors, there are two transistors in series in all discharge paths.
So all n channel transistors should have a width of 2. Then all discharge paths
(Mn1, MN2), (Mn1, MN3) and (Mn4, MN5) will have the equivalent resistance of
(R/2 + R/2) = R.
Alternate Solution
An alternative solution is possible for this specific function, which makes use of the
fact that when the charge path through series connected y and z transistors (Mp2
and Mp3) is in use, the two parallel y and z transistors on top (Mp4 and Mp4) are
on simultaneously, and therefore can be less wide (1.5γ each).

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 VDD
y Mp4 z Mp5
1.5γ 1.5γ

z Mp2
x Mp1 3γ
3γ
Mp3 y
3γ Out

x Mn1 z Mn4 y
2 2
Mn2 Mn3
y z Mn5
2 2 2

This leads to the required geometries being: MP1, MP2, MP3 = 3γ each and
MP4=MP5 = 1.5γ each. Verification of this is:
y=z=0, path is through MP2,MP3 in series, with the parallel combination of MP4
and MP5 in series with it. This gives a total rersistance of
R/3 + R/3 + (R/1.5 parallel R/1.5) = R/3 + R/3 + R/3 = R
x=y=0, path is through MP1, MP4, with resistance R/3 + 2R/3 = R.
x=z=0, path is through MP1, MP5,with resistance R/3 + 2R/3 = R.
– [2]
b) While x.y + y.z + z.x is symmetric in x, y and z, our implementation of this func-
tion as x.(y + z) + y.z is not symmetric. If one of the inputs of this implementation
is to be placed in the critical path of a design, which input will you choose? Justify
your choice.
If this critical path input is coming from an identical stage before it, compute the
delay of the previous stage when loaded with your choice of input (x, y or z), in
units of τ .
Soln. 2-b) The x input is loaded with a single n transistor of width 2 and a single p
transistor of width 1.5γ. y and z inputs are connected to 2 n transistors of width
2 each and 2 p transistors of width 3γ each. Thus the total capacitive load on y
and z is 4 + 6γ, while that on x is only 2 + 1.5γ. Therefore placing x in the critical
path will be the fastest alternative.
This stage has the drive strength equivalent to the reference inverter. So the
previous (identical) stage will also have the same drive as the reference inverter.
When loaded with a capacitance of (1 + γ), (the input capacitance of a reference
inverter), it has a delay of τ . When connected to x, it is loaded with a capacitance
of (2 + 1.5γ). So its delay will be (2 + 1.5γ)/((1 + γ) times τ . – [3]
Q–3 The matrix of transistors available in a sea of gates template is shown below:

6
 All n channel transistor in the template have the minimum allowed width, while all p
channel transistor have a width = γ times the width of n transistors to compensate for
mobility ratio.
a) Show the interconnect required to implement the function A.(B + C) + D using a
two stage design with the above template.
Soln. 3-a) We can express A.(B + C) + D as (A.(B + C).D. In the two stage implemen-
tation, the first stage generates A.(B + C), while the second uses a NAND with D
as the other input to produce the desired output.
VDD
B
A A.(B+C) D
C
Out

A A.(B+C) D

B C C

VDD VDD

Out

C B A
D
A.(B+C)

The interconnection required to implement the logic function in a sea of gates

matrix is shown above. – [2]
b) The output of A.(B + C) + D will drive a minimal inverter. Ignoring the delay
due to interconnect and driver self capacitance, find the factor as a function of γ
by which this design is slower than the same circuit implemented in custom design
with transistor widths adjusted according to series parallel rules.
Soln. 3-b) In the first stage, the worst case charge path is through B and C. Since both
have a width of γ, the net output drive is half as much as that of the reference
inverter. Similarly, the worst case discharge path is through A and one of B and C.
This also provides half the drive capability of the reference inverter. The second
stage presents a load of one nMOS and one pMOS to the output of the first stage,
which is equivalent to the input capacitance of an inverter. Thus the delay of the
first stage is 2τ .
Similarly, the discharge path in the second stage is through 2 unit sized n transistors
in series. Therefore the worst case discharge time when loaded with a reference
inverter will be twice that of a reference inverter discharging another. The charge
time will be the same as an inverter because the two p channel transistors are in
parallel. Thus the worst case total delay is 4τ .
In a custom designed circuit with series parallel sizing, all nMOS transistors of the
first stage would have had a size of 2, the pMOS transistor driven by A would have

7
 the width γ while pMOS transistors driven be B and C would have widths of 2γ.
Overall, the first stage will have the same drive capability as the reference inverter.
In the second stage, nMOS transistor widths will be 2, while the pMOS transistor
widths will remain as γ. Thus the load on the first stage will be (2 + γ)/(1 + γ)
times that of the reference inverter. the second stage will have the drive capability
of the reference inverter and will be loaded with an inverter, so its delay will be τ .
Thus the total delay for the custom designed circuit in units of τ will be:
2+γ 3 + 2γ
+1=
1+γ 1+γ
Thus the semi-custom sea of gates is slower by a factor 4(1 + γ)/(3 + 2γ)
for γ = 2, this factor is 12/7. However, the custom designed circuit will load its
previous stage more than the semi-custom circuit. Thus, while the semi-custom
circuit is definitely slower, the loss in speed is not catastrophic. – [3]
Q–4 We had ignored the delay due to self capacitance of the driver while deriving the opti-
mum conditions for a tapered inverter used for driving large capacitive loads. This led
to the result that the optimum stage ratio = e for all stages. We now want to include
the effect of delay due to self capacitance as a size independent addition to the stage
delay. Thus, stage delay is now given by Si+1 /Si + p in units of τ , where τ is the delay
of a minimum inverter driving another without any self capacitance delay.
a) Consider a tapered inverter with input capacitance of 1 (in units of input capac-
itance of the minimum inverter) and a final load which is 1000 times the input
capacitance of a minimum inverter. If we ignore the self capacitance of drivers,
what is the optimum number of stages and the optimal stage ratio for this many
stages?
Soln. 4-a) The optimum number of stages if we ignore self-capacitance is given by
ln Cout /Cin = ln(1000) = 6.9078. The number of stages should, of course, be
integral – so the optimum number of stages is 7.
Since the stage ratio ρ should be the same for all stages, we must have
ρ7 = 1000, so ρ = 10001/7 = 2.6827
Notice that the optimum stage ratio is close to, but not exactly e. – [1]
b) Derive the condition on optimum stage ratio in an inverter chain with a give number
of stages when the delay of i’th stage is modeled as Si+1 /Si + p. What should be
the product of all stage ratios?
Soln. 4-b) The total delay for n stages of an inverter chain is given by:
n  n
Si+1 Si+1
X  X
D= + p = n.p +
1 Si 1 Si
To find the minimum of D with respect to Si values, we take the partial derivatives
of D with respect to each of Si s and set it to 0.
In the sum, the only terms involving Si are: Si /Si − 1 + Si+1 /Si . Therefore when
we take partial derivatives with respect to Si , all other terms contribute 0. Hence,
!
∂ Si Si+1
+ =0
∂Si Si−1 Si

8
 This gives
1 Si+1 Si Si+1
2
=0
− or =
Si−1 Si Si−1 Si
So we get the condition that the stage ratio should be the same for all stages in
this case also. The product of all stage ratios gives
n
Y Si+1 S2 S3 Sn+1 Sn+1
= · ··· =
1 Si S1 S2 Sn S1
since all intermediate S values will cancel. Each stage ratio should be the same
in the optimum case. Let us define this value as ρ. Then the product of all stage
ratios should just be ρn . Hence we get, in the optimum case,
n
Si+1 Sn+1 CL
= ρn =
Y
=
1 Si S1 Cin

– [3]
c) If we model the stage delay as Si+1 /Si + 2 in units of τ , with input capacitance of
1 and final load capacitance of 1000, what is the total delay of the inverter chain
if we use i) 3, ii) 5, iii) 7 and iv) 9 stages to drive the final load?
Soln. 4-c) We have ρn = CL /Cin = 1000. So if the number of stages is given, we can find
the value of ρ = 10001/n . The total delay is given by
n 
Si+1
X 
D= + 2 = n(ρ + 2)
1 Si

since the stage ratio must be the same (= ρ) for all stages.
For n = 3, ρ = 10001/3 = 10 and so the delay is 3 × 12 = 36.
For n = 5, ρ = 10001/5 = 3.9811 so the delay is 5 × 5.9811 = 29.905.
For n = 7, ρ = 10001/7 = 2.6827 so the delay is 7 × 4.6827 = 32.779.
For n = 9, ρ = 10001/9 = 3.9811 so the delay is 9 × 5.9811 = 37.39.
Notice that the optimum number of stages is no more 7 but 5.
Also, all these delays are a huge improvement over the delay of a single inverter
driving the load, which would have been 1000! – [4]
d) By what factor is a 3 input NAND gate and a 3 input NOR gate slower compared
to the reference inverter when transistors are scaled down to offer the same input
capacitance as a reference inverter? Assume the mobility ratio to be γ.
Soln. 4-d) the figure below shows the 3 input NAND and NOR circuits.
VDD VDD

γ γ γ C
3γ
A.B.C
B B
A 3γ
3
A
B 3γ
3 A+B+C

C
3 1 1 1
A B C

3 input NAND 3 input NOR

9
We first find the widths by series parallel rule, which will give us gates with the
same output drive as the reference inverter. We then scaled it down to give the
same input capacitance as the reference inverter.
In the 3 input NAND, the three n transistors are in series, so each should be 3 times
as wide as the nMOS in the reference inverter. The 3 p channel transistors are
in parallel, so each should be the same size as the pMOS in the reference inverter
(= γ).

The total input capacitance is now 3 + γ in units of reference inverter nMOS input
capacitance. With this geometry, it will provide the same output drive as the
reference inverter. But we want a gate which will have the same input capacitance.
The input capacitance of the inverter is 1 + γ. So we must scale down the gate by
(3 + γ)/(1 + γ), which will make it slower by the same factor.

In the 3 input NOR, the three n transistors are in parallel, so each should be the
same size as the nMOS in the reference inverter. The 3 p channel transistors are
in series, so each should be the 3 times the width of the pMOS in the reference
inverter. So the pMOS width in 3 input NOR should be = 3γ).

The total input capacitance is now 1 + 3γ in units of reference inverter nMOS

input capacitance. With this geometry, it will provide the same output drive as the
reference inverter. But we want a gate which will have the same input capacitance.
The input capacitance of the inverter is 1 + γ. So we must scale down the gate by
(1 + 3γ)/(1 + γ), which will make it slower by the same factor.

Thus the 3 input NAND is slower by the factor 3+γ

1+γ
and the 3 input NOR is slower
1+3γ
by the factor 1+γ compared to the reference inverter if these are to offer the same
input capacitance as the reference inverter. – [2]

Paper Ends

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