Chapter 2 | Basics of Chip Design

Catalogs of IP blocks from the likes of Arm, Cadence and OpenCore can be used for the design of a SoC.
Table 2.1 contains a non-exhaustive list of such blocks.

Table 2.1 IP block examples

Interconnects Interconnect family provides on-chip AMBA connectivity for components implementing any
combination of AMBA AXI, AHB, AHB-Lite, APB and APB3 interfaces

Memory controllers Memory controllers including dynamic and static memory controllers

System controllers System controllers including interrupt controllers, DMAs, color LCDs, level-2 cache controllers,
TrustZone controllers

Programmable interfaces Peripherals including GPIOs, UARTs, synchronous serial ports, keyboard/mouse, smart cards,
real-time clocks, external buses, test peripherals

All of the IP block catalogs provide the specifications of the components, providing information on:

n how to connect the component to a system (which interconnects it is compatible with)

n how the component can be configured and the list of registers exposed by its programming interface

n the type of delivery: whether it is in the form of RTL code or an already synthesized block

n the test bench used to validate the design.

If a block is not taken as an IP block from a third-party vendor and must be designed, one needs
to know how it will be connected to the system. Because different types of interconnect exist, the
new block will need to implement the correct signals and the correct interface to receive write
and read commands. Once this is done, the next step is to create the programming interface for
the component. This involves the list of registers that must be configured so that it can be used.
Eventually, once the block has been designed and verified, it can be incorporated into the overall
system design.

2.1.2 Choosing a Processor

As previously indicated, software is just as important as the underlying hardware. Coding is based on
assembly language (assembler) to make it more readable for the programmer. However, in practice,
assembler has to be translated into opcode commands that the processor can understand. Processors
can only understand the opcodes for which they have been designed, meaning that, for example, an
Arm core would give an undefined behavior if a program that was compiled for an Intel processor was
run on it instead.

Thus, the first step necessary is to define the different instructions to be supported and the associated
opcode that the processor will understand. This is termed the instruction set. If we use as an example
the ADD assembler instruction that takes data from a register, adds an operand and puts the result
into another register, the instruction will look like this for Arm:

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