8051 has separate address space for

program memory and data memerory

1. Program memory
2. Data memory

Program memory:

Internal (Onchip)

External (Off chip)

Program memory is used to store program code

Permanent memory

Read only memory

Data memory:

Internal (Onchip)

External (Off chip)

Data memory is used for the storage of data and result

4 KB ROM (on chip)

60 KB ROM (off chip)

Temporary storage

RAM

128 bytes RAM on chip Internal data memory is access with 8 bit address lines

64 KB Ram offchip External data memory access with 16 bits address bus

Address bus length is 8051 = 16bits

16
2 = 64 KB
https://www.youtube.com/watch?v=YYIi2aEyjXI
The internal data memory of 8051 is divided into two groups. These are a set of eight
registers and a scratch pad memory. These eight registers are R0 toR7. The address range
00H to 07H is used to access the registers, and the rest are scratch pad memory. 
8051 Provides four register bank, but only one register bank can be used at any point in time.
To select the register bank, two bits of PSW (Program Status Word) are used.

So the following addressing can be used to select register banks.

Address Range Register Bank

00H to 07H Register Bank 0

08H to 0FH Register Bank 1

10H to 17H Register Bank 2

18H to 1FH Register Bank 3

The concept of four register banks is very useful. For servicing the interrupts, this feature is
very good. The interrupt program can use one bank, and the interrupt Service Subroutine
(ISS) can access another bank for better performance. As there are four banks, so for nested
interrupts these can be used
When all of the register banks are being used, the scratch pad area will be 20H to 7FH. But
from 20H to 2FH (16 bytes or 128 bits) can be used as bit addressable RAM. By using some
simple instructions with 8-bit memory address we can check the bit addressing. For an
example the instruction CLR 6FH, using this instruction it clears the location 6FH. As we
know the8-bit address can locate 256 different locations, but here only128-bits are
addressable. Another section of bit addressable locations is 80H to FFH. The remaining
locations (30H to 7EH) of the RAM can be used to store variable data and stack.

Stack Area
The stack area in 8051always can be implemented in the internal data memory. Here the
stack pointer (SP) is an only 8-bit register, because the internal RAM area is only in range
00H to 7FH, and when all register banks are being used, the stack location will be in range
30H to 7FH. So in such a case, the SP will be initialized with 2FH.
The stack pointer SP increases before each PUSH operation and decreases after each pop
instruction. 
When the 8051 is reset, the Stack Pointer will point to 07H. It means the location 08H to
7FHcan be used as a stack. We are assuming that the register bank 0 is in use and 20H to
27H are not like bit-addressable area.
We have already discussed that the 8051 microcontroller has the internal program memory.
In this chip, there is EA  pin. It indicates the External Access. So by using this pin, we can
check whether the internal program memory is used or not. So when there is a low signal in
this pin, the internal 4K bytes of program memory is not used, but in this situation, it can
access only the ROM.
When we are trying to access the external data memory, then the read RD or write WR will
be the output from 8051. So for reading the data from external sources,
there PSEN (Program Strobe Enable) pin. This is an active low output pin. When this pin is
active low, it indicates that the microcontroller reads from the external ROM. The 16-bit
ROM address will be floated on Port 2 (MS Byte) and Port 0 (LS Byte). The program code is
received on Port 0 pins.
So there is two case of accessing the program memory. The first case is when EA is low, and
the second case is when EA is high. For the low state of EA, it can access the entire external
memory from location 0000H to FFFFH. And in the second case (EA = 1). In this case, the
internal memory is accessed by the address 0000H to 0FFFH. And also the external memory
is accessed from location 1000H to FFFFH.
The external program memory address is always 16-bit address. If the memory is very small
compared to 64KB memory, then also the address will be 16-bit. So when we use the
external memory, we cannot use the Port0 and Port 2 as IO ports. The instruction execution
times are not depending on the on-chip ROM or external EPROMs
So the structure of external program memory interfacing is like below

8051 Interrupts

8051 architecture handles 5 interrupt sources, out of

which two are internal (Timer Interrupts), two are
external and one is a serial interrupt. Each of these
interrupts has its interrupt vector address. The highest
priority interrupt is the Reset, with vector address
0x0000.
Vector Address: This is the address where the controller jumps after the interrupt to
serve the ISR (interrupt service routine).

Interrupt Flag Interrupt vector address

Reset - 0000H

INT0 (Ext. int. 0) IE0 0003H

Timer 0 TF0 000BH

INT1 (Ext. int. 1) IE1 0013H

Timer 1 TF1 001BH

Serial TI/RI 0023H

Reset

Reset is the highest priority interrupt, upon reset 8051 microcontroller start executing
code from 0x0000 address.

Internal interrupt (Timer Interrupt)

8051 has two internal interrupts namely timer0 and timer1. Whenever timer
overflows, timer overflow flags (TF0/TF1) are set. Then the microcontroller jumps to
their vector address to serve the interrupt. For this, global and timer interrupt should
be enabled.

Serial interrupt

8051 has a serial communication port and have related serial interrupt flags (TI/RI).
When the last bit (stop bit) of a byte is transmitted, the TI serial interrupt flag is set,
and when the last bit (stop bit) of the receiving data byte is received, the RI flag gets
set.

IE register: Interrupt Enable Register

IE register is used to enable/disable interrupt sources.

      
Bit 7 – EA: Enable All Bit

            1 = Enable all interrupts

            0 = Disable all interrupts

Bit 6,5 – Reserved bits

Bit 4 – ES: Enable Serial Interrupt Bit

            1 = Enable serial interrupt

            0 = Disable serial interrupt

Bit 3 – ET1: Enable Timer1 Interrupt Bit

            1 = Enable Timer1 interrupt

            0 = Disable Timer1 interrupt

Bit 2 – EX1: Enable External1 Interrupt Bit

            1 = Enable External1 interrupt

            0 = Disable External1 interrupt

Bit 1 – ET0: Enable Timer0 Interrupt Bit

            1 = Enable Timer0 interrupt

            0 = Disable Timer0 interrupt

Bit 0 – EX0: Enable External0 Interrupt Bit

            1 = Enable External0 interrupt

            0 = Disable External0 interrupt

Interrupt priority
Priority to the interrupt can be assigned by using the interrupt priority register (IP)

Interrupt priority after Reset:

 
 Priority Interrupt source Intr. bit / flag

1 External Interrupt 0 INT0

2 Timer Interrupt 0 TF0

3 External Interrupt 1 INT1

4 Timer Interrupt 1 TF1

5 Serial interrupt (TI/RI)

In the table, interrupts priorities upon reset are shown. As per 8051 interrupt
priorities, the lowest priority interrupts are not served until the microcontroller is
finished with higher priority ones. In a case when two or more interrupts arrive
microcontroller queues them according to priority.

IP Register: Interrupt priority register

8051 has an interrupt priority register to assign priority to interrupts.       

Bit 7,6,5 – Reserved bits.

Bit 4 – PS: Serial Interrupt Priority Bit

            1 = Assign a high priority to serial interrupt.

            0 = Assign low priority to serial interrupt.

Bit 3 – PT1: Timer1 Interrupt Priority Bit         

            1 = Assign high priority to Timer1 interrupt.

            0 = Assign low priority to Timer1 interrupt.

Bit 2 – PX1: External Interrupt 1 Priority Bit    

            1 = Assign high priority to External1 interrupt.

            0 = Assign low priority to External1 interrupt.

Bit 1 – PT0: Timer0 Interrupt Priority Bit         

            1 = Assign high priority to Timer0 interrupt.

            0 = Assign low priority to Timer0 interrupt.

Bit 0 – PX0: External0 Interrupt Priority Bit     

            1 = Assign high priority to External0 interrupt.

            0 = Assign low priority to External0 interrupt.

External interrupts in 8051

 8051 has two external interrupt INT0 and INT1.
 8051 controller can be interrupted by external Interrupt, by providing level or edge on
external interrupt pins PORT3.2, PORT3.3.

Input/Output ports of 8051:

The 8051 has four number of 8 bit ports namely
Port – 0
Port – 1
Port – 2
Port – 3
The 8052 has 32 I/O pins configured for these four 8
bit ports
All ports are bidirectional.
Each pin will be configured as input or output under
software control.
Each port consists of a latch, an output buffer and
input buffer.
Features of Port 0:

 Address is 80H
 Construction: Port 0 has a D-type latch, unidirectional buffer, and 2
FETs at each pin. It does not have an internal pull-up resistor. An
 external pull-up resistor is needed when Port 0 is defined as an output
port.
 Port 0 of the 8051 has two main functions: To be used as a simple
input-output port and to access external memory in conjunction with
Port 2.
 it can be used for address/data interfacing for accessing external memory.
 It is a bidirectional port

Features of Port 1:

 Address is 90H
 Construction: Port 1 has one latch, output buffers and input buffers.
 It has only one function – to act as an Input-Output port.


Features of Port 2

 Address is 10H
 Construction: Port 2 has a D type latch, 1 FET, an internal pull-up
resistor, two unidirectional buffers, and a Control Logic block.
 Its main functions are kind of similar to those of Port 0. It can be used
as an input-output port. And can access external memory in
conjunction with Port 0.

Features of Port 3

 Address is B0H
 Construction: The third Port of 8051 has a D-type latch. In addition to
that, it has three unidirectional buffers. A FET with an internal pull-
up resistor. Additionally, it also has a NAND gate connected to the
FET.
 Port 3 performs two main functions, as we will see below.

Functions of Port 3
I/O port
Just like Port 2, Port 3 can function as an input-output port.
Alternate SFR function
The input to SFR 1, we get the output of latch as 1, which turns on the NAND gate,
and depending on the value of ‘Alternate Output Pin,’ FET will be wither
ON/OFF.
RXD: this is used for a serial input port
TXD: this is used for serial output port
INT0: this used for an external interrupt 0
INT1: this used for external interrupt 1
T0: Timer 0 external input
T1: Timer 1 external input
WR:  external data memory write strobe
RD: external data memory Read strobe

SBUF (Serial Data Buffer)

The Serial Buffer or SBUF register is used to hold the serial data while
transmission or reception.

SCON (Serial Control)

The Serial Control or SCON SFR is used to control the 8051
Microcontroller’s Serial Port. It is located as an address of 98H. Using
SCON, you can control the Operation Modes of the Serial Port, Baud Rate
of the Serial Port and Send or Receive Data using Serial Port.
SCON Register also consists of bits that are automatically SET when a byte
of data is transmitted or received.

The following table describes the function of each bit in the SCON
Register.

Bit Symbol De

7 SM0 Serial Port M

6 SM1 Serial Port M

5 SM2 Multiproc

4 REN Recei

3 TB8 Trans

2 RB8 Rec

1 TI Transmi

0 RI Receive
The Serial Port Mode Selection Bits (SM0 and SM1) determine the mode
of UART and also the baud rate. The following table gives an overview of
how the Serial Port Mode Selection Bits can be used to configure Serial
Port (UART) of 8051.

Types of interrupt in 8051 Microcontroller

The five sources of interrupts in 8051 Microcontroller:

Interrupt ROM Location Priority

External Interrupt – INT0 0003H Highest
Timer 0 Interrupt – TF0 000BH
External Interrupt – INT1 0013H
Timer 1 Interrupt – TF1 001BH
Serial Port interrupt – 0023H Lowest
RI/TI
Each interrupt can be enabled or disabled by setting bits of the IE register and the whole interrupt
system can be disabled by clearing the EA bit of the same register.

IE (Interrupt Enable) Register

This register is responsible for enabling and disabling the interrupt. EA register is set to one
for enabling interrupts and set to 0 for disabling the interrupts. Its bit sequence and their
meanings are shown in the following figure.

It disables all interrupts. When EA = 0 no interrupt will be acknowledged and

EA IE.7
EA = 1 enables the interrupt individually.

- IE.6 Reserved for future use.

- IE.5 Reserved for future use.

ES IE.4 Enables/disables serial port interrupt.

ET1 IE.3 Enables/disables timer1 overflow interrupt.

 EX1 IE.2 Enables/disables external interrupt1.

ET0 IE.1 Enables/disables timer0 overflow interrupt.

EX0 IE.0 Enables/disables external interrupt0.

IP (Interrupt Priority) Register

We can change the priority levels of the interrupts by changing the corresponding bit in the
Interrupt Priority (IP) register as shown in the following figure.
 A low priority interrupt can only be interrupted by the high priority interrupt,
but not interrupted by another low priority interrupt.
 If two interrupts of different priority levels are received simultaneously, the
request of higher priority level is served.
 If the requests of the same priority levels are received simultaneously, then the
internal polling sequence determines which request is to be serviced.

- IP.6 Reserved for future use.

- IP.5 Reserved for future use.

PS IP.4 It defines the serial port interrupt priority level.

PT1 IP.3 It defines the timer interrupt of 1 priority.

PX1 IP.2 It defines the external interrupt priority level.

PT0 IP.1 It defines the timer0 interrupt priority level.

PX0 IP.0 It defines the external interrupt of 0 priority level.