Republic of the Philippines

Polytechnic University of the Philippines

Office of the Vice President for Academic Affairs
College of Engineering
ELECTRONICS ENGINEERING (ECE) DEPARTMENT

ECEN 3364-INDUSTRIAL ELECTRONICS AND PLC APPLICATIONS

Belinario, John Orville T. Group 2 BEN B. ANDRES, DEM, PECE

Delos Reyes, Arvin Godfrey F. Professor
Group2Group No.:
Duran, Reineir S.
Mampusti, Jayron T.
Rivera, Shawn Ivan S.
Rating
EXPERIMENT 4
PROGRAMMABLE UNIJUNCTION TRANSISTOR
I. OBJECTIVES:
1. To become familiar with the structure, operation, characteristics, parameters and
applications of PUT.
2. To show how to calculate and measure VO and VP, and how to measure IAK and IG.
3. To demonstrate how a PUT is used as a switch in a relaxation oscillator, and to
determine the output frequency.

II. DISCUSSION:
The PUT operation similar to the UJT, but its precise firing point can be determined.

Structure and Schematic Symbol

This consists of four layers of P and N material and it leads are labeled anode (A),
gate (G), and cathode (K).

Figure 4.1

a) Structure b) Equivalent Transistor Circuit c) Schematic Symbol

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Republic of the Philippines
Polytechnic University of the Philippines
Office of the Vice President for Academic Affairs
College of Engineering
ELECTRONICS ENGINEERING (ECE) DEPARTMENT

Operation of a PUT
The PUT acts like a voltage-controlled diode. It requires a negative going pulse at its
gate to turn it on.
Figure 4.2

At time T1, a negative going pulse at the gate fires the PUT and current flows from K
to A and G. Voltages VA decreases at this time.
At time T2, the pulse is removed from the gate, but current continues to flow from K to
A and G. Voltage VAalso remains low, indicating that the PUT is conducting.

Therefore, the gate can trigger the PUT on, but then loses control.

Current-Voltage Characteristics of a PUT

Figure 4.3

VA decreases because of the negative-resistance "action" of the PUT.

VO also decreases, because of the negative-resistance action. IAK, IA and IG increases.

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Republic of the Philippines
Polytechnic University of the Philippines
Office of the Vice President for Academic Affairs
College of Engineering
ELECTRONICS ENGINEERING (ECE) DEPARTMENT

PUT Relaxation Oscillator

The VP can be programmed by R1 and R2 to cause the PUT to fire at exactly 63.2% of
+VCC, or one time constant.
Figure 4.4

PUT Definitions
Table 4.1
VCC power supply voltage connected to the anode
VA voltage from anode to ground
VC voltage between R1 and R2 to ground
VD forward voltage drop across PUT's anode to cathode. (≈0.7V)
VP peak voltage on anode at which PUT fires
VV valley voltage across anode and ground after PUT fires (≈0.7V)
IAK current flowing into cathode
IA current flowing out of the anode
IG current flowing out of gate
IP current flowing through PUT before firing
Iq current flow through PUT after firing

PUT Working Equations

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Republic of the Philippines
Polytechnic University of the Philippines
Office of the Vice President for Academic Affairs
College of Engineering
ELECTRONICS ENGINEERING (ECE) DEPARTMENT

R1 V P=V G +V D 1
V G= (V ) f OSC =
R 1+ R2 CC R AC A

III. MATERIALS NEEDED:

1 Fixed +9V power supply 1 Breadboard for constructing
1 Oscilloscope (dual trace circuit
preferred) 1 4.6 kΩ resistor at 0.5 W
1 Standard or digital voltmeter 1 33 kΩ resistor at 0.5 W
1 Standard or digital ammeter 1 56 kΩ resistor at 0.5 W
1 2N6027 PUT or equivalent 1 100 Ω resistor at 0.5 W
1 10 kΩ potentiometer (RA) 1 100 kΩ resistor at 0.5 W
1 47 kΩ resistor at 0.5 W 1 220 kΩ resistor at 0.5 W
1 6.8 kΩ resistor at 0.5 W 1 0.01uF capacitor
1 68 kΩ resistor at 0.5 W 1 0.02uF capacitor
1 0.1uF capacitor
IV. PROCEDURES:

Part 1. This experiment involves calculating VG and VP and then measuring for these
voltages it will be shown how the values of R 1 and R2 influence the total current IAK
and the holding current IH through the PUT.
1. Construct the circuit shown in Figure 5.5 as shown below using the values R1
and R2 from the first row of the Table 5.2
Figure 4.5

Table 4.2
Data Table

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Polytechnic University of the Philippines
Office of the Vice President for Academic Affairs
College of Engineering
ELECTRONICS ENGINEERING (ECE) DEPARTMENT

R1 (kΩ) R2 R 1(+V CC ) VG V P=V G +V D VP (VA) IAK IH (mA)

(kΩ) V G=
R1 + R2
6.8 4.6 5.36 6.12 6.06 5.97
47 33 5.2875 5.33 5.9875 6.13
68 56 4.94 5.11 5.64 5.61

1. Adjust RA until VA reads 0 V.

2. Calculate VG and record on the data table.
3. Measure VG and record in the data table.
4. Calculate VP and record in the data table.
5. By adjusting RA, slowly increase VA until the meter indicates a sudden
decrease. The point just before the meter reading decreases is VP. Slowly
perform this step several times to obtain an accurate measurement for VP.
6. Record VP in the data table.
7. With the PUT fired (at the VP point), measure IAK and record in the data table.
8. With the PUT fired, slowly adjust RA so that IAK decreases. The meter reading
will suddenly decreases to zero. The point just before this sudden decrease is
the PUT’s holding current. Slowly perform this step several times to obtain an
accurate measurement for IH.
9. Record IH in the data table.
10. With the PUT fired, note the meter readings of VA and VC. The PUT is acting
like a switch.
11. Repeat steps 2 through 11 for the other values of R1 and R2 given in the table.

Part 2. Relaxation Oscillator

1. Construct the circuit shown in Figure 4.6.
2. Using the voltmeter, measure and record VA, VG, and VK in the blank spaces
provided in Figure.

VCC = 12 V, RA = 100 kΩ, RK = 100 Ω, R1 = 47 kΩ, R2 = 6.8 kΩ, CA = 0.1 uF

VG = 320.6 mV VK = 290.9 mV VA = 1.021 V

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Polytechnic University of the Philippines
Office of the Vice President for Academic Affairs
College of Engineering
ELECTRONICS ENGINEERING (ECE) DEPARTMENT

Figure 4.6

Table 4.3
RA CA Frequency (Hz)
(KΩ) (uF) Calculated Measured
100 0.01 1 kHz 996.57 Hz
100 0.1 100 Hz 102.14 Hz
100 0.02 500 Hz 501.88 Hz
47 0.01 2.13 kHz 2.43 kHz
220 0.01 454.55 Hz 462.39 Hz
3. Using the oscilloscope, examine the voltage waveforms at G, K, and A.
4. Draw these voltage waveforms in the spaces provided and indicate their
peak-to-peak values.
Table 4.4
VG VK VA

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Polytechnic University of the Philippines
Office of the Vice President for Academic Affairs
College of Engineering
ELECTRONICS ENGINEERING (ECE) DEPARTMENT

5. Calculate the approximate frequency of the oscillator from the values of RK

and CK and record in the proper place in Table 4.3.
6. Place the oscilloscope at A and measure the actual frequency. Remember that
f=1/T, where T is the time period of one cycle. Record this frequency in the
proper place in the data table.
7. Change components RA and CA as indicated by the table and repeat steps 5
and 6.

V. OBSERVATION:
PUT relaxation oscillator can be used for generating a wide range of saw tooth
wave forms. It is called a relaxation oscillator because the timing interval is
started by the gradual charging of a capacitor and the timing interval is
terminated by the sudden discharge of the same capacitor.

VI. CONCLUSION:
Gate Resistors set the peak voltage (Vp) and intrinsic standoff ratio (η) of the
PUT. Resistor Rk limits cathode current of the PUT. Resistor R and capacitor C
sets the frequency of the oscillator. When the supply voltage Vbb is applied, the
capacitor C starts charging through resistor R. When the voltage across the
capacitor exceeds the peak voltage (Vp) the PUT goes into negative resistance
mode and this creates a low resistance path from anode (A) to cathode (K). The
capacitor discharges through this path. When the voltage across the capacitor is
below valley point voltage (Vv) the PUT reverts to its initial condition and there
will be no more discharge path for the capacitor. The capacitor starts to charge
again and the cycle is repeated. This series of charging and discharging results in
a sawtooth waveform across the capacitor.

VII. QUESTIONS:
1. Which of the following statements is incorrect?
a) The PUT can be turned on with a negative pulse applied to the gate.
b) The PUT is programmable by selection of the gate resistors, which can
determine the exact firing point.
c) A PUT circuit can produce a sharp pulse to trigger other circuits.
d) The PUT can replace an SCR in a circuit.

2. A sawtooth voltage waveform of PUT oscillator can be seen with an oscilloscope

at:
a) A terminal b) K terminal c) G terminal d) none of the above

3. The condition of PUT as relaxation oscillator when CA is shorted.

a) Oscillates b) Saturates c) Cut-off d) none of the above

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Polytechnic University of the Philippines
Office of the Vice President for Academic Affairs
College of Engineering
ELECTRONICS ENGINEERING (ECE) DEPARTMENT

4. A positive pulse train is found at the gate of a PUT oscillator (True or False).
True

5. A negative pulse train is found at the cathode of a PUT oscillator (True or False).
True
6. Low Voltage Lamp Flasher Operation/Application
A circuit using the PUT in a low
voltage application is shown in
Figure on the left where a supply
voltage of 3 volts is used. The circuit
is a low voltage lamp flasher
composed of a relaxation oscillator
formed by Q1 and an SCR flip flop
formed by Q2 and Q3.
With the supply voltage applied
to the circuit, the timing capacitor
C1 charges to the firing point of the
PUT, 2 volts plus a diode drop. The
output of the PUT is coupled
through two 0.01 uF capacitors to
the gate of Q2 and Q3. To clarify
operation, assume that Q3 is "on"
and capacitor C3 is charged plus to
minus as shown in the figure. The
next pulse from the PUT oscillator
turns Q2 "on". This places the
voltage on C4 across Q3 which
momentarily reverse biases 03. This
reverse voltage turns Q3 "off".
After discharging, C4 then charms
with its polarity reversed to that
shown. The next pulse from Q1
turns Q3 "on" and Q2 "off”. Note
that C4 is a non polarized capacitor.

7. Voltage Controlled Ramp Generator Operation/Application

The PUT provides a simple

approach to a voltage controlled
ramp generator. VCRG, as shown
in Figure on the left. The current
source formed by Q1 in
conjunction with capacitor C1 set

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Polytechnic University of the Philippines
Office of the Vice President for Academic Affairs
College of Engineering
ELECTRONICS ENGINEERING (ECE) DEPARTMENT

the duration time of the ramp. As

the positive dc voltage at the gate is
changed, the peak point firing
voltage of the PUT is changed, the
peak point firing voltage of the
PUT is changed which changes the
duration time i.e.. of the PUT is
changed which changes the
duration time i.e.. increasing the
supply voltage increases the peak
point tiring voltage causing the
duration time to increase.

8. Low Frequency Divider Operation/Application

This division range can be

changed by utilizing the
programmable aspect of the PUT
and changing the voltage on the gate
by changing the ratio R6/(R6+R5).
Decreasing, the ratio with a given CI
and C2 decreases the division range
and increasing the ratio Increases
the division range. The circuit
works very well and is fairly
insensitive to

The circuit works very well and is

fairly insensitive to the amplitude,
pulse width, rise and fall times of the
incoming pulses.

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