Sardar Patel Institute of Technology

Bhavan’s Campus, Munshi Nagar, Andheri (West), Mumbai-400058, India

(Autonomous College Affiliated to University of Mumbai)

End Semester Examination

November 2019

Max. Marks: 60 Duration: 180 Min

Class: SE ETRX / SE EXTC Semester: III
Course Code: EL33 / ET33
Branch: Electronic/Electronic and Telecommunication
Name of the Course: Digital Circuits
Instruction:
(1) All questions are compulsory
(2) Draw neat diagrams
(3) Assume suitable data if necessary
(4) Question attempted in order fetch full marks

Q Max. CO-BL-PI
No. Marks
Q.1 A. Convert SR Flip Flop to JK Flip Flop. Compare Combi- 3 + 3 4-3-3.2.1
national Circuits and Sequential Circuits with atleast 3 dif-
ferentiating parameters.

B. Design MOD 4 UP/DOWN Synchronous Counter using 6 4-3-3.2.1

JK flip flop.

Q.2 A. Draw and explain the operation of the 2-input Standard 4+2 6-2-13.1.2
TTL NOR Gate. Explain atleast two difference between the
Standard TTL and Low-power Schottky TTL family.

B. Using Quine Mc’Clusky Method minimize the given ex- 06 1-3-1.4.1

pression.

X
F (A, B, C, D) = (0, 1, 3, 7, 9, 15) + d(8, 11)

OR

Q.2 A. Use the k-map to reduce the following function and then 06 1-3-1.4.1
implemented it by using NOR Gate only

F (A, B, C, D) = Π(1, 2, 5, 8, 10, 12, 15) + d(0, 6)

B. Explain the Interfacing of the CMOS to TTL logic and 3+3 6-2-13.1.2
TTL to CMOS logic with neat labelled diagram.
Q.3 A. Discuss the Field Programmable Gate Array(FPGA) 4+2 6-2-13.1.2
with neat labelled diagram. Compare FPGA and CPLD with
atleast two distinguishing points.

B. Write a Short note on 3x2 6-2-13.1.2

a. Stuck at ‘0’ fault.
b. Stuck at ‘1’ fault
c. Metastability

Q.4 A.Design a Mealy Sequence Detector to detect four or more 06 5-3-3.2.1

consecutive occurrences of 1’s using D flip flops

B. Implement the following functions using 06 1-3-1.4.1

(a) single 8:1 MUX and NOT Gate
(b) single 4:1 MUX and few NAND gates.

X
F (A, B, C, D) = (2, 6, 8, 12, 13, 14)

OR

Q.4 A. Analyze the following Sequential machine and obtain the 06 5-3-3.2.1
state diagram.

B. Design 4-bit using IC 7483 which is 4 bit binary adder. 6 1-3-1.4.1

Q.5 A. I Explain what Race Around Condition in J K Flip Flop 3 4-2-3.2.1
with waveforms. State any one method to avoid it.

A. II Reduce the given State diagram and obtain reduced 3 5-3-3.2.1

table using Normal Method and Implication Chart Method.

B. Design Mod 72 counter using IC 74160 and basic gates. 6 4-3-3.2.1

Use LD and RCO pins in the design.

*** Best Wishes for your Examination ***