Solid-State Electronics 50 (2006) 24–31

www.elsevier.com/locate/sse

Phase change memories: State-of-the-art, challenges and perspectives

A.L. Lacaita *

Dipartimento di Elettronica e Informazione, Politecnico di Milano, and IU.NET piazza Leonardo da Vinci 32, 20133 Milano, Italy

Received 15 August 2005; received in revised form 10 October 2005; accepted 10 October 2005

The review of this paper was arranged by Enrico Sangiorgi and Claudio Fiegna

Abstract

Among the emerging non-volatile technologies, phase change memories (PCM) are the most attractive in terms of both performance
and scalability perspectives. The paper reviews the physics underlying PCM operation, the scaling potentials of these devices and some
options recently proposed for the cell structure. The paper also addresses the main challenges for the PCM to become fully competitive
with standard Flash technology.
Ó 2005 Elsevier Ltd. All rights reserved.

Keywords: Phase change memories; Non-volatile memories; Chalcogenide materials

1. Introduction negative resistance and a bistable behavior. They can

As the Flash memory scaling trend is slowing down,
alternative memory concepts are being investigated to pro-
vide a better trade-off between scalability and reliability.
Among them, phase change memory (PCM) is attracting
growing interest. These devices were first proposed by S.
Ovshinsky who, in the late 1960s, reported the observation
of a reversible memory switching in chalcogenide materials
[1]. Chalcogenides are semiconducting glasses made by ele-
ments of the VI group of the periodic table, such as sulfide,
selenium and tellurium. As–Se (arsenic–selenide) was inves-
tigated for the adoption in xerography, while the ability of
Ge–Te glasses to undergo fast crystalline–amorphous
phase transformation is being used in rewritable optical
media (CD, DVD) [2,3]. In the latter application selective
crystallization/amorphization is induced by a laser beam.
The binary information is read out by exploiting the
change of the optical reflectivity between the amorphous
and the crystalline state. Chalcogenide materials show also
*
Tel.: +39 2 2399 6117; fax: +39 2 236 7604.
E-mail address: andrea.lacaita@polimi.it
switch from a high to a low resistance state and can be
therefore used as a solid-state memory. The principle of a
chalcogenide RAM memory was first proposed by Dewald
in 1962 [4]; however, only in the early 2000s semiconductor
industries have considered the exploitation of the same
concept for large-size solid-state memories [5–9]. Today
PCMs are considered a promising candidate to eventually
become the mainstream non-volatile technology due to
their large cycling endurance [10–12], fast program and
access times and extended scalability [13].
2. Cell structure and programming
The PCM memory cell (Fig. 1) is characterized by one
transistor and one resistor (1T–1R), the resistor being a
chalcogenide layer (Ge2Sb2Te5, or GST) sandwiched
between a top metal contact and a resistive bottom elec-
trode. Depending on whether the chalcogenide material is
crystalline (SET state) or amorphous (RESET state) the
cell resistance changes by orders of magnitudes. The tran-
sistor acts as a selector, driving the cell current in the writ-
ing and read out phases. Solutions using diodes, bipolar
transistors and MOSFETs as selectors have been presented

0038-1101/$ - see front matter Ó 2005 Elsevier Ltd. All rights reserved.
doi:10.1016/j.sse.2005.10.046
 A.L. Lacaita / Solid-State Electronics 50 (2006) 24–31
Fig. 1. Schematic cross-section for a PCM cell. The active region is
adjacent to the GST-heater interface.
[6–9]. Memory programming is accomplished by driving a
50–100 ns current pulse through the cell, thus inducing the
phase transition of the chalcogenide layer close to the inter-
face with the bottom electrode (heater). The heater keeps
the hot spot far from the cold metal contact, while its shape
is designed to confine the current flow and the heat gener-
ation. The amorphous state is obtained by driving the
device with a current pulse lasting less than 100 ns. The
GST temperature, close to the heater, rises above the melt-
ing temperature (TM = 620 °C); then the device is swiftly
cooled down by the nanosecond trailing edge of the current
pulse. Since the molten material has no time to rearrange
the bondings, it is left into the amorphous phase. The resis-
tance of a cell with an amorphous region capping the top
heater end can be easily in the MX range.
For the opposite transition, the cell is driven by a similar
current pulse but with a lower peak value. The pulse heats
the GST close to the bottom electrode up to around
550 °C. This temperature is lower than the melting temper-
ature but high enough to make the amorphous–crystalline
transition happen in about 100 ns. As the pulse is over the
GST has recovered the crystalline, low resistivity, state.
The corresponding cell resistance is in the kX range. Since
both the programming transitions use 50–100 ns current
pulses, this novel memory is intrinsically able to guarantee
fast programming, which is a big performance advantage
with respect to mainstream Flash devices.
25
Reading is accomplished by biasing the cell and sensing
the current flowing through it. A few hundreds of mV
across the cell in the SET state generate 50–100 lA. This
current is able to load the bit-line capacitances of a mem-
ory array, making possible a reading operation in 50 ns.
The same bias across the cell in the RESET state is not able
to generate enough current to trigger the sensing amplifier,
thus resulting in the evaluation of a ‘‘0’’.
In order to switch the cell from the amorphous to crys-
talline state (RESET–SET transition) the device has to be
driven by about 0.5 mA. Since the amorphous cell has
about 1 MX resistance, a voltage supply higher than
500 V would be needed. No practical electrical memory
could be conceived with such a voltage requirement. The
peculiar I–V curve of the cell in the amorphous (RESET)
state makes possible to overcome this potential limitation
(Fig. 2). Note that the cell in the highly resistive state fea-
tures low conductivity only at low bias. As the voltage rises
above a threshold value, the voltage suddenly snaps-back
and the cell with the amorphous layer becomes highly con-
ductive. Such a threshold switching makes possible to have
large currents flowing through the cell in the RESET state
even if the voltage is just above 1 V.
The physics of this peculiar effect has been a debated
issue for many years. Since Ovshinsky reported threshold
switching [1] different models have been proposed. Many
researchers supported the idea that switching is essentially
a thermal effect and that the current in an amorphous layer
switches due to the creation of a hot filament [14,15]. Later,
Adler showed that the effect is not thermal [16], at least in
thin chalcogenide films, in agreement with the original
Ovshinsky’s picture. In his pioneering work [17], he demon-
strated that a semiconductor resistor may feature switch-
ing, without any thermal effect, whenever carrier
generation depending on field and carrier concentration
(e.g. impact ionization) competes with a Shockley–Hall–
Read recombination via localized states. Recently the
GST electronic switching and the underlying physics have
been quantitatively addressed using a device simulator
0.75
Crystal
Amorphous
0.50
Current [mA]
0.25
Vth
0.00
0.0 0.5 1.0 1.5
Voltage [V]
Fig. 2. Current–voltage characteristics of a PCM cell in both the reset and
set state.
26 A.L. Lacaita / Solid-State Electronics 50 (2006) 24–31
and a good agreement has been reached between calculated
and experimental I–V curves [18]. The effect can be
explained referring to Fig. 2. In the low bias regime the
amorphous GST layer is highly resistive. However, as the
bias increases, the current starts to exponentially rise due
to impact ionization which is balanced by recombination
via localized states. The microscopic structure of chalco-
genide amorphous glasses is characterized by twofold tellu-
rium atoms which are linked in chains. Along these chains
there are structural defects, the so-called valence alterna-
tion pairs, which are responsible of a high density (1017–
1020 cm
3) of localized states [19,20]. As all the defects
are fully saturated by recombining carriers, the exponen-
tially rising carrier generation cannot be balanced any
more by recombination and the only way the device has
to reach a new steady-state condition is to swiftly reduce
the voltage to quench the generation rate [18]. A snap-back
takes place and after switching the GST is still amorphous
but highly conductive.
On the contrary, the I–V curve of the crystalline GST
(SET state) does not feature threshold switching and
approaches the I–V of the reset state after switching. The
slope of this part of the curve is mainly determined by
the resistance of the heater, while the voltage drop across
the GST layer approaches a constant value, the holding
voltage, VH, which is of the order of the material band-
gap (0.5 eV).
Fig. 3 shows the programming characteristic of a PCM
cell, that is the dependence of the cell resistance R as a
function of the programming current. Filled symbols refer
to the resistance obtained driving a cell in the reset state. In
the measurement procedure a 100 ns programming pulse is
applied and the cell resistance after programming is read at
0.2 V. Before the following measurement, the cell is
brought again in the initial reset state using a proper cur-
rent pulse. Then the measurement cycle starts again driving
the cell with a new 100 ns programming current pulse with
a different amplitude. Three distinct regions can be recog-
6 7
10
Set state
Reset state
Resistance [Ω]
5
10
4
10
3
10
0.0 0.1 0.2 0.3 0.4 0.5 0.6
Programming Current [mA]
Fig. 3. Cell resistance as a function of programming current (R–I
characteristic). Before any program pulse the cell is programmed back
in its initial set or reset state.
nized: (i) for programming pulses below 50 lA, the ON-
state conduction is not activated and the very small current
does not provide any phase change, (ii) in the 50–500 lA
range, the resistance decreases following the crystallization
of the amorphous GST, (iii) above 500 lA, the program-
ming pulse melts some GST close to the interface with
the bottom electrode, leaving it in the amorphous phase.
The bit resistance measured after programming increases.
Open circles in Fig. 3 also shows the R–I characteristics
obtained for the same cell, but starting from the SET state.
The resistance value changes only when the current exceeds
500 lA, where the characteristic overlaps to the R–I of the
RESET state. In conclusion the PCM cell can be switched
using pulses of 500 lA and 700 lA, respectively. The pulses
are independent of the initial cell state (resistance). The cell
can be therefore rewritten with no need of an intermediate
erase. The orders of magnitude difference between the cell
resistance in the SET and RESET state makes the PCM
memory ideally suited for a multi-bit operation: in this
scheme the resistance of the cell may be set between the
two extreme values thus placing more than two levels per
cell. This approach may become a viable option to further
reduce the cost per bit of PCM devices.
3. Cell reliability
The crystalline–amorphous transformation in GST is
fast and stable. Fig. 4 shows the resistance of the set and
reset states as a function of the programming cycles. Each
program cycles included a 40-ns reset pulse and a 100-ns set
pulse. A resistance window of a factor 102 is retained over
1011 cycles, confirming the excellent stability of the pro-
gramming characteristic. The reason for such a remarkable
endurance is strictly related to the microscopic structure of
the GST alloy. GST in the crystalline phase is characterized
by a rock-salt structure, whose lattice structure is schemat-
ically depicted in Fig. 5. Based on extended X-ray absorp-
tion fine structure (EXAFS) measurements [3], it was
10
6
10
Resistance [Ω]
5
10 RESET
SET
4
10
0.7 3
10 0 1 2 3 4 5 6 7 8 9 10 11 12
10 10 10 10 10 10 10 10 10 10 10 10 10
Number of cycles [#]
Fig. 4. Cell resistance in set and reset states as a function of the number of
set/reset cycles.

Te
Sb
Ge
Fig. 5. Schematic view of the GST crystal. Te atoms form an f.c.c. sub-
lattice, while Sb, Ge and vacancies form the other sub-lattice.
recently found that the chemical short-range order of the
ternary GST system is almost the same in the two phases.
It means that in the amorphous state, interactions between
different Ge2Sb2Te5 building blocks are weakened. The
structure is therefore allowed to relax, but neither strong
covalent bonds are broken nor atoms drastically change
their position in the lattice. The Te-sublattice is partially
preserved as well as the conservation of the local structure
around the Sb atoms. The original crystalline structure can
be therefore quickly and reliably recovered.
After 1011–1012 cycles, the PCM cell fails featuring
either a stuck-set (inability to reset the cell) or a stuck-reset
(inability to set the cell) [10–12]. Both failure modes criti-
cally depend on the quality of the bottom electrode inter-
face, on its adhesion to the chalcogenide layer and on
interdiffusion processes which may happen between the
chalcogenide alloy and the adjacent materials. The failure
is expected to depend on the energy released during cycling
in the active volume. Fig. 6 confirms that endurance at con-
stant programming current scales inversely to the reset
12
10
11
10
Endurance [# of cycles]
10
10
9
10
8
10
7
10
6
10
1 2
10 10 10
RESET Pulse Width W [ns]
Fig. 6. Cell endurance vs. reset pulse width.
A.L. Lacaita / Solid-State Electronics 50 (2006) 24–31 27
9
10
10 years
Crystallization time [s]
10
7 110 C˚
5
10
3
10
1
10
20 22 24 26 28 30 32 34
-1
1/k BT [eV ]
Fig. 7. Experimental Arrhenius plot for the crystallization time of the
reset state. Ten-year retention requires operation below 110 °C.
pulse width. The longer the pulse, the larger the energy
released per pulse, the faster the interface degradation,
while the overall energy released up to the bit failure
remains almost constant.
Another critical issue for a non-volatile memory cell is
data retention, that is the capability to retain the stored
information during the memory lifetime. From this stand-
point the reset state of the PCM is particularly sensitive.
The amorphous GST can spontaneously evolve towards
the more stable crystalline phase. Fig. 7 shows the Arrhe-
nius plot for the failure time, defined as the time required
to the resistance to decay by half of its reset value. The
experimental activation energy of 2.6 eV corresponds to
10-years lifetime at the maximum temperature of 110 °C.
A further potential concern for reliability is the program
disturb. When an array cell is being programmed, the adja-
cent cells can suffer a parasitic heating, which can result in
data loss (Fig. 8). Fig. 9 shows the results collected in a
multi-Mb array fabricated in 0.18 lm technology. The
resistance of some cells in the amorphous state are moni-
tored while a neighbour cell undergoes repetitive program-
ming (800 lA, 50 ns pulses). The reset state remains stable
Experimental
-1.05
Best Fitting W
3 4 5 6
10 10 10
Fig. 8. Schematic description of the program disturb in a PCM array. The
temperature rise due to a programming pulse may cause an adjacent
amorphous cell to crystallize.
28 A.L. Lacaita / Solid-State Electronics 50 (2006) 24–31
7
10
RESET
6
10
Resistance [Ohm]
(I-1,J-1)
10
5 (I-1,J)
(I,J-1)
(I+1,J-1)
4 SET (I+1,J)
10
3 0.0
10 0 1 2 3 4 5 6 7 8 9 10 11
10 10 10 10 10 10 10 10 10 10 10 10
Number of Cycles [#]
Fig. 9. Resistance of cells in a reset state monitored while a surrounding
cell is being cycled with repetitive writing. No disturb effects are visible up
to 1010 program cycles.
and no data loss was found up to 10 programming pulses.10
To address the impact of possible cross-talk in more scaled
technology numerical simulations have been performed
[13]. The results show that program disturb should not
be an issue at least down to the 45-nm node. For further
scaled devices, interaction between adjacent bits may
impose a cell spacing slightly larger than the feature
size.
4. Scaling perspectives
PCM cell operation relies on bulk properties, i.e. phase
transformation of the active material. No physical limita-
tion to cell scaling are therefore expected to be met until
some monomers of chalcogenide material are left in the
active volume. This potential for extreme shrinking of the
active volume is being used to reduce the programming
currents which may become a limitation for the design of
large memory arrays. A simplified electro-thermal theory
of the PCM cell [13] may help in understanding the scaling
trend. At steady state the temperature rise DT needed to
reach the melting temperature in the active volume is given
by
DT ¼ PRth ;
where P is the power dissipated by Joule heating and Rth is
the total thermal resistance connecting the hot-spot to the
thermal sink at room temperature (metal layers). The
power dissipated in the GST layer is P = VHI, since the
holding voltage VH is the voltage drop across the chalco-
genide layer in the conducting regime. The programming
current is therefore:
I ¼ DT =ðV H Rth Þ.
Since both DT and VH are physical quantities which do not
scale, the programming current should scale as the inverse
of Rth, and can be optimized by accurate design of the bot-
tom electrode. The major consequence of (1) is that the cur-
1.2
Reset Current [mA]
1.0
0.8
0.6
0.4
0.2
0 500 1000 1500 2000 2500 3000
Contact Area [nm2]
Fig. 10. Experimental scaling trend of the reset current in PCM cells as a
function of the contact size.
rent scales linearly with the contact area. Fig. 10 shows
measured reset current as a function of the area of the con-
tact between the bottom electrode and the GST active
layer. Programming currents as low as 50 lA have been
achieved on single cells with complete device functi-
onality, thus demonstrating that the overall physical pic-
ture remains the same down to a contact size of about
20 nm.
For proper operation in the array, each PCM cell
requires the presence of a device acting as selector. Such
a selector basically sets the overall cell size. The adoption
of a MOSFET is interesting for embedded application
but its limited current capability leads to a cell size of
15–20F2 (F is the technology feature size). Even if the use
of a bipolar requires the introduction of specific process
steps, its larger current capability makes possible to reach
8–10F2 and maximum array density. The bipolar is there-
fore an interesting option for high-density stand-alone
non-volatile memories.
The cell structure should scale without major modifica-
tions taking full advantage from the feature shrinking.
Assuming that all the linear dimensions scale as 1/k, the
contact area will scale as 1/k2 while the electrical and ther-
mal resistances will increase by a factor k. Since DT and VH
do not scale, the reset current (from (1)) is expected to scale
as 1/k. Such a dependence matches well the scaling trend of
both MOSFETs and bipolars, whose current capability is
expected to scale as 1/k [21]. However the constant voltage
drop on the PCM device could become an issue since it
poses a constraint on the maximum voltage which should
be sustained by the bipolar selectors or by the gate oxide
of the MOSFETs across the unselected cells of the array.
In summary, beyond the 45 nm technology node, an accu-
rate design of the selecting device will become mandatory.
ð1Þ
Fig. 11 shows the comparison between the scaling projec-
tion of the NOR and NAND cell size and the expected
trend for the PCM cell with the bipolar selector. The
PCM may reach the NOR Flash size at the 65 nm technol-
ogy node and the NAND at the 45 nm node.
 A.L. Lacaita / Solid-State Electronics 50 (2006) 24–31 29

1
FLASH NOR
FLASH NAND
180 nm 180 nm
PCM
Cell size (µ2)

180 nm 130 nm
130 nm
0.1
90 nm
90 nm
130 nm
65 nm 45 nm
90 nm 65 nm 45 nm
65 nm

45 nm
0.01
2001 2003 2005 2007 2009
Year

Fig. 11. Scaling projection of PCM cell size compared to the mainstream
Flash technology.

5. Cell topologies and results

Literature results are encouraging and supporting the

feasibility of a competitive PCM technology as a next-gen-
eration non-volatile memory. The first industrial results on
PCM cells were presented by Intel-Ovonyx [5]. The cell
structure was similar to the one presented in Fig. 1
(lance-like) and the selector was a diode. The GST material Fig. 12. A ltrench PCM cell. Top view and cross-sections [9].
was deposited on top of a lance (heater), which defines the
bottom contact. The lance size is defined starting from a
lithographic feature and using a 2D sidewall spacer to fur-
99.9999999
ther reduce it. The contact size sets the cell programming 99.99997
current, therefore in multi-Mb arrays the control of such 99.997
a feature has to be tight. The heater, usually made by
Cell Percentage [%]

99.87
TiN, adds some further Joule heating without increasing 97.72
too much the overall cell resistance, and keeps the hot-spot 84
far from the cold contacts. The optimum position of the 50
hot-spot depends also on the GST thickness. In order to 16
optimize the thermal resistivity of this layer, nitrogen dop- 2.27
0.13
ing has been proposed [22]. RESET
0.003
Samsung, following the lance-like approach, has demon- 0.00003 SET
strated 64 Mb arrays with MOSFET selectors, scaling pro- 0.0000001
gressively the reset current from the 2.0 mA in the 240 nm 0 10 20 30 40 50 60 70 80 90 100
technology [7] to 600 lA at the 120 nm node with nitrogen- Read Current [µA]
doped GST [8]. By using a two-step CMP process a better
Fig. 13. Read current distribution within a 8 Mb ltrench PCM array.
control of the contact size (52 ± 7 nm) has been achieved
and a further reduction of the programming current has
been obtained limiting the TiN deposition only along the the information stored in the entire array can be correctly
periphery of the lance [23]. decoded.
Reliable contact size control has been also demonstrated Another possible cell geometry is the so-called pore-like
by STMicroelectronics with the so-called ltrench approach structure, reported in Fig. 14. In this case the GST is depos-
[9] (Fig. 12): the contact size is limited in one direction by ited within the pore and therefore the hot-spot is better
the heater thickness (few-nm range), and by a sub-litho confined by the surrounding insulating walls. It has been
trench (few tens of nm) filled by GST in the other one. shown that this approach has the potential to reduce by
The ltrench PCM cell reaches a 600 lA reset current at more than 50% the programming current with respect to
the 180-nm technology node. Fig. 13 shows the read cur- the value achieved in a lance-like approach [13]. However,
rent distributions for set and reset states within an 8Mbit if the GST is deposited using conventional sputtering
PCM array. The program window is compatible with a method it is difficult to get a conformal deposition of the
high-density memory. Placing a read threshold at 15 lA material within the pore. An in-situ deposition/etch/
30 A.L. Lacaita / Solid-State Electronics 50 (2006) 24–31
Fig. 14. Schematic view of a pore-like PCM.
deposition method is able to overcome this difficulty.
Deposition of the GST within a 50 nm pore with a 1:2
aspect ratio has been reliably demonstrated and is able to
reduce the programming current to 400 lA [24].
The PCM resistor can be also fabricated horizontally.
Fig. 15 shows the geometry of a planar cell [25], consisting
of a patterned GST layer with a bottleneck, where phase
change occurs. The cross-section of the chalcogenide layer
in the active region is given by the product of the layer
thickness and the lithographic width. This topology takes
advantage of the distance between the phase-change vol-
ume, which is in the middle of the line, and the contacts
at room temperature. By reducing heat diffusion towards
the contacts, a lower programming current may be
attained. However, the need for two contacts makes this
cell design hardly suitable for high-density applications.
The same planar structure has been recently investigated
at Philips Research [26] using Sb–Te doped with one or
more elements from the series Ge, In, Ag, and Ga. Ref.
[26] shows that doped-Sb–Te features threshold switching.
Fig. 15. SEM micrograph of a lateral PCM cell [25].
Moreover planar cells with lines 200 nm long and (20 nm)2
cross-section are able to switch in less than 50 ns with
450 lA programming current. These results may open the
way to further investigations of performance trade-off in
PCM devices using materials different from GST.
6. Conclusions
The paper reviews the basic issues of current PCM tech-
nology discussing programming and reliability perfor-
mance, cell structures and scaling perspectives. The
development of a cell design compatible with writing, reli-
ability, scalability and process integration requirements is
under way. Tight control of contact size, of material con-
tamination, interface adhesion and overall integration pro-
cess are critical issues as well as the optimization of the
phase-change and contact materials. However, among the
innovative concepts for alternative non-volatile memories,
phase change memories appear as the best candidate to
eventually become mainstream non-volatile technology.
The memory concept is sound and no serious limitations
are posed to the cell downsize beyond the 45 nm technol-
ogy node.
Acknowledgement
The author gratefully acknowledge STMicroelectron-
ics—Agrate Brianza and the entire R&D team for support-
ing this research program.
References
[1] Ovshinsky SR. Reversible electrical switching phenomena in disorder
structures. Phys Rev Lett 1968;21:1450–3.
[2] Yamada N. Rapid phase-transition of GeTe–Sb2Te5 pseudobinary
amorphous thin films for an optical disk memory. J Appl Phys
1991;69(5):2849–56.
[3] Kolobov AV, Fons P, Frenkel AI, Ankudinov AL, Tominaga J,
Tomoya U. Understanding the phase-change mechanism of rewrit-
able optical media. Nature Mater 2004;3:703–8.
[4] Fundamental of amorphous semiconductors. Washington DC;
National Academy of Sciences-Nat. Res. Council; 1972.
[5] Lai S, Lowrey T. OUM—A 180 nm nonvolatile memory cell element
topology for stand alone and embedded applications. IEDM Tech
Dig, 2001. p. 803–7.
[6] Gill M, Lowrey T, Park J. Ovonic unified memory—a high-
performance nonvolatile memory technology for stand alone memory
and embedded applications. ISSCC 2002, Tech Dig. p. 202–459.
[7] Hwang YN, Hong JS, Lee SH, Ahn SJ, Jeong GT, Koh GH, et al.
Full integration and reliability evaluation of phase-change RAM
based on 0.24 lm-CMOS technologies. Symp VLSI Tech 2003, Tech
Dig. p. 173–4.
[8] Ahn SJ, Song YI, Jeong CW, Shin JM, Fai Y, Hwang YN, et al.
Highly manufacturable high density phase change memory of 64 Mb
and beyond. IEDM Tech Dig, 2004. p. 907–10.
[9] Pellizzer F, Pirovano A, Ottogalli F, Magistretti M, Scarafaggi M,
Zuliani P, et al. Novel ltrench phase-change memory cell for
embedded and stand-alone non-volatile memory applications. Symp
VLSI Tech, 2004, Tech Dig. p. 18–9.
[10] Mielke N, Hudgens S, Johnson B, Lowrey T. Reliability of ovonic
unified memory. Sematech/SRC Top Res Conf Reliab, 2002, Tech
Dig.
 A.L. Lacaita / Solid-State Electronics 50 (2006) 24–31
[11] Pirovano A, Redaelli A, Pellizzer F, Ottogalli F, Tosi M, Ielmini D,
et al. Reliability study of phase-change non-volatile memories. IEEE
Trans Device Mater Reliab 2004;4:422–7.
[12] Kim K, Ahn SJ. Reliability investigations for manufacturable high
density PRAM. IRPS Tech Dig, 2005. p. 157–62.
[13] Pirovano A, Lacaita AL, Benvenuti A, Pellizzer F, Hudgens S, Bez R.
Scaling analysis of phase-change memory technology. IEDM Tech
Dig, 2003. p. 699–702.
[14] Popescu C. The effect of local nonuniformities on thermal switching
and high field behavior of structures with chalcogenide glasses. Solid-
State Electron 1975;18:671–81.
[15] Owen AE, Robertson JM, Main C. The threshold characteristics of
chalcogenide-glass memory switches. J Non-Cryst Solids
1979;32:29–52.
[16] Adler D, Henisch HK, Mott SD. The mechanism of threshold
switching in amorphous alloys. Rev Mod Phys 1978;50:209–20.
[17] Adler D, Shur MS, Silver M, Ovshinsky SR. Threshold switching
in chalcogenide-glass thin films. J Appl Phys 1980;51:3289–
309.
[18] Pirovano A, Lacaita AL, Benvenuti A, Pellizzer F, Bez R. Electronic
switching in phase-change memories. IEEE Trans Electron Dev
2004;51:452–9.
31
[19] Kastner M, Adler D, Fritzsche H. Valence-alternation model for
localized gap states in lone-pair semiconductors. Phys Rev Lett
1976;37:1504–7.
[20] Kastner M. Bonding bonds, lone-pair bands, and impurity states in
chalcogenide semiconductors. Phys Rev Lett 1972;28:355–7.
[21] ITRS. Update edition 2003.
[22] Horii H, Yi JH, Park JH, Ha JH, Baek IG, Park SO, et al. A novel
cell technology using N-doped GeSbTe films for phase change RAM.
Symp VLSI Tech Dig, Tech Dig, 2003. p. 177–8.
[23] Ahn SJ, Hwang YN, Song YJ, Lee SH, Lee SY, Park JH. Highly
reliable 50 nm contact cell technology for 256 Mb PRAM. Symp
VLSI Tech, Tech Dig, 2005. p. 98–9.
[24] Cho SL, Yi JH, Ha YH, Kuh BJ, Lee CM, Park JH. Highly scalable
on-axis confined cell structure for high density PRAM beyond
256 Mb. Symp VLSI Tech, Tech Dig, 2005. p. 96–7.
[25] Haring Bolivar P, Merget F, Kim D-H, Hadam B, Kurz H. Lateral
design for phase change random access memory cells with low-current
consumption. European symposium on phase-change and ovonic
science, EPCOS Tech Dig, 2004.
[26] Lankhorst M, Keterlaars B, Wolters RAM. Low-cost and nanoscale
non-volatile memory concept for future silicon chips. Nature Mater
2005:4–6.