A

Summer Training Report

On
VLSI Design
Submitted to the Department of Electronics Engineering in Partial Fulfilment for
the Requirements for the Degree of

Bachelor of Technology
(Electronics and Communication)

by

ANURAG KHARWAR
(U19EC061)
(B. TECH. IV(EC), VIIth Semester)

External Guide
Dr.Sandeep Saini
Subject Expert, Internshala

Internal Guide
Dr. Anand D. Darji
Assistant Professor, DECE

DEPARTMENT OF ELECTRONICS ENGINEERING

SARDAR VALLABHBHAI NATIONAL INSTITUTE OF
TECHNOLOGY
SEPTEMBER-2022
 Sardar Vallabhbhai National Institute Of Technology
Surat - 395 007, Gujarat, India

DEPARTMENT OF ELECTRONICS ENGINEERING

CERTIFICATE
This is to certify that the Summer Training Report entitled “VLSI Design” is
presented & submitted by Candidate ANURAG KHARWAR, bearing Roll No.
U19EC061, of B.Tech. IV, 7th Semester in the partial fulfillment of the requirement for
the award of B.Tech. Degree in Electronics & Communication Engineering for
academic year 2022
- 23.
He/She has successfully and satisfactorily completed his/her Summer Training
Presentation Exam in all respects. We certify that the work is comprehensive, complete
and fit for evaluation.

Dr. Anand D. Darji

Assistant Professor & Summer Training Guide

Name of Examiners Signature with Date

1.

2.

Dr. P. N. Patel
Head & Associate Professor Seal of The Department
DECE, SVNIT (August 2022)
CERTIFICATE
 Acknowledgements
I would like to express my profound gratitude and deep regards to my guide Dr. Anand
D. Darji for his guidance. I am heartily thankful for suggestion and the clarity of the
concepts of the topic that helped me a lot for this work. I would also like to thank Prof
.P.N. Patel, Head of the Electronics Engineering Department, SVNIT and all the
faculties of ECED for their co-operation and suggestions. I am very much grateful to
all my classmates for their support.

Anurag Ajeet
kharwar Sardar Vallabhbhai National Institute of
Technology
Surat

September 15, 2022

v
 Abstract
This defines the Verilog Hardware Description Language (HDL). A formal notation
called Verilog HDL is designed to be used throughout the entire electronic system de-
velopment process. It supports the development, verification, synthesis, and testing of
hardware designs, the exchange of hardware design data, and the maintenance, mod-
ification, and acquisition of hardware because it is both machine readable and human
readable. The implementors of technologies supporting the language and proficient
language users are the main target audiences for this standard.
Very-large-scale integration (VLSI) is a term used to describe a subset of
semicon- ductor and communication technologies. On a single chip, there are
integrated circuits. The original semiconductor chips only had one transistor. A VLSI
device serves as the microprocessor. It entails creating and implementing circuits. It
offers computing speed with the least amount of power consumption and circuit board
space. The term Very Large Scale Integration (VLSI) refers to semiconductor-
integrated circuits made up of millions of memory cells and other logic components.
Computational speed is provided through the approach of implementation circuit
designing. As a result, this method offers a smaller area or volume. Due to better on-
chip interconnects, compact- ness, decreased testing needs, lower power consumption,
increased reliability, increased speed due to much shorter connector lengths, and
significant cost savings result.
vii
 Table of
Contents
Page
Acknowledgements......................................................................................................v
Abstract......................................................................................................................vii
Table of Contents........................................................................................................ix
List of Figures..............................................................................................................xi
List of Tables.............................................................................................................xiii
List of Abbreviations.................................................................................................xv
Chapters

References.....................................................................................................................3
Appendix

ix
List of Figures

xi
List of Tables

xiii
 List of Abbreviations
ALU Arithmetic Logic Unit
ASIC Application Specific Design
Flow CLB Configurable Logic Circuits
CPU Central Processing Unit
CTS Clock Tree Synthesis
EDA Electron Design Automation
FPGA Field Programmable Gate
Array HDL Hardware Description
Language IC Integrated Circuits
LSI Large Scale Integration
PLA Programmable Logic Array
RAM Random Access Memory
ROM Read Only Memory
RTL Register transfer Logic
SRAM Static Random Access
Memory SSI Small Scale Integration
VLSI Very Large-Scale Integration
xv
 CHAPTER 1

INTRODUCTION

The first week of the internship period was spent in learning basic concepts of VHDL and
Verilog coding. I was also introduced to the front end and backend domain of the VLSI
design and some basic things like hardware design related issues like static timing analysis,
simulations, synthesis and basics of PLDs (internal architecture, various types etc.). To get
better acquainted with the design and coding techniques, various test-codes were written for
testing the various peripherals (starting from basic LED testing).

On moving to second week, I got to introduced with deeper concept of VLSI coding and got
familiar with HDL coding concepts in which we learnt types or coding used in VLSI and also
types of modeling used.

In third week, the main focus was on combinational and sequential circuit design in which I
got to learn more about this topic also I learnt to write some code my own using data level,
gate level and behavioral level including writing the test- bench for the for the testing purpose
of the final product which ever we design and prepared for next week.

In fourth week I got to introduced with FSM(finite state machine),finite-state

automaton (FSA, plural: automata), which means A finite-state machine (FSM) or  finite
automaton, or simply a state machine, is a mathematical model of computation. It is
an abstract machine that can be in exactly one of a finite number of states at any given time.
And learnt about transition if FSM.

System Design using FPGA got introduced in the fifth week of the summer internship that
was the most interesting part of the summer internship where I had to work on the tool called
VIVADO by Xilinx in which I made some of basic assignment such as FULL- ADDER
HALF -ADDER, MUX, DEMUX, DECODER, INCODER and many as such.

Finally in the last week of the internship mentor gave me a final project and case studies to
work on that was the most challenging part of the entire internship which I will discuss more
in detail in chapter 2, after completion of the given project I had to go through the final test
which was based on the entire learning till now
Finally, I passed the internship test with 72% and got the certificate of compilation.
 CHAPTER 2

VLSI DESIGN

Project 1: Realtime Traffic Light Control System

Brief Introduction:

Through using VHDL language towards the traffic controller that is light design, the traffic
light control circuit utilizes signal that is electronic automatic control to understand two sets
of lights which are red, Green and yellowish. Those lights command automobiles and
pedestrians moving properly at the crossroad, which bases regarding the information of traffic
state transition. Most of control systems are designed by advanced PLC technology, that also
can effortlessly imitate the traffic that has experience. In addition, FPGA cannot compare the
round that is anti-dry Speed and benefit advantage that is fast. But PLC has a drawback for
traffic light design. Most PLC costs much more could be 10 times throughout the price that is
FPGA, which includes not considered the expansion module. The PLC technology is mostly
utilized in hefty industry and Precision Instruments manufacturing. The traffic that is FPGA
control system has to consider the present traffic situation, that will be based on the
information from sensors. The FPGA gets current signals of vehicles moving crossroad and
base on those signals send next thing order. Also, into the specific road the traffic light should
specifically be set. In addition, the FPGA need to consider the best time, meaning that
isolating the traffic situation by the proper time. The codes must certainly be packed within
the FPGA development base on different models, that might increase the program flexibly.

Hardware Details:

* Programmable Logic Controller

 FPGA board

Software Details:

 VHDL
 Xilinx

FPGA - Field Programmable Gate Array is an IC (Integrated Circuit) which can be modified
by the customer or designer based on their requirement after manufacturing. In the electronics
industry, the components are manufactured based on their standards and protocols which
makes it difficult for the users to configure it according to their needs. This created a
requirement for new hardware which can be configured by the user or designer.

FPGA contains programmable logic blocks and interconnection circuits which can be
modified based on the requirement after manufacturing. FPGA is cheaper for small scale
requirements when compared to ASIC (Application-specific Integrated circuit) which is
suitable for large scale production.

VHDL : The VHSIC Hardware Description Language (VHDL) is a hardware description

language (HDL) that can model the behavior and structure of digital systems at
multiple levels of abstraction, ranging from the system level down to that of logic gates, for
design entry, documentation, and verification purposes

Xilinx : Xilinx, Inc. was an American technology and semiconductor company that primarily

supplied programmable logic devices. The company was known for inventing the first
commercially viable field-programmable gate array (FPGA) and creating the first fabless
manufacturing mode.
Block Diagram:

Figure 2.1: Block diagram of traffic control

Design of traffic signal controller for this scenario

 Figure 2.2: Model highway

The following specifications must be considered

 the traffic signal for the main highway gets highest priority because the
cars are continuously present in the main highway. Thus, the main
highway signal remains green by default.
 Occasionally, cars from the country road arrive at the traffic signal. The
traffic signal for the country road must turn green only long enough to let
the cars on the country road go.
 As soon as there are no cars on the country road, the country road traffic
signal turns yellow and then red and traffic signal on the main highway
green again.
 There is a sensor to detect cars waiting on the country road. The main
sensor sends a signal X as input to the controller. X = 1 if there are cars
on the country road; otherwise, X =0;
 There are delays on the transitions from S1 to S2, from S2 to S3 and from
S4 to S0, the delays must be controllable.

The state machine diagram and the state definitions for the traffic
signal controller are shown in figure 2.3
 Figure 2.3: finite state diagram.

State signal
So Hwy = GCntry = R
S1 Hwy = YCntry = R
S2 Hwy = RCntry = R
S3 Hwy = RCntry = G
S4 Hwy = RCntry = Y

Table 2.1: Finite state definitions

Things to remember before design:

Two conditions:
so, 1 bit X
…………………………………………………………..
Five stages :

So 3 bits required to present

So to S4

…………………………………………………………..
Three colors:
So, 2 bits to represent three colors.

Verilog code.

`timescale 1ns / 1ps

`define TRUE 1'b1

`define FALSE 1'b0

//Delays
`define Y2RDELAY 3 //Yellow to red delay is 3-time units
`define R2GDELAY 2 //Red to green delay is 2-time units

module sig_control(hwy, cntry, X, clock, clear);

//I/0 ports

output reg [1:0] hwy, cntry;

// 2-bit output for 3 states of signal GREEN, YELLOW, RED;

// declared output signals are registers

input X;

input clock, clear;

// if TRUE, indicates that there is car on the country road,
// otherwise, FALSE
parameter RED = 2'd0,
YELLOW = 2'd1,
GREEN = 2'd2;

//State definition HWY CNTRY

parameter
S0 = 3'd0, //GREEN RED
S1 = 3'd1, //YELLOW RED
S2 = 3'd2, //RED RED
S3 = 3'd3, //RED GREEN
S4 = 3'd4; //RED YELLOW

//Internal state variables

reg [2:0] state;
reg [2:0] next_state;

//state changes only at positive edge of clock

always @(posedge clock)
if (clear)
 state <= S0; //Controller starts in SO state

else
state <= next_state; //State change

//Compute values of main signal and country signal

always@(state)
begin
hwy = GREEN; //Default Light Assignment for Highway light
cntry = RED; //Default Light Assignment for Country light

case(state)

SO: ; // No change, use default

S1: hwy = YELLOW;
S2: hwy = RED;
S3: begin
hwy = RED;
cntry = GREEN;
end
S4: begin

hwy = RED;
cntry = YELLOW;
end
endcase
end

//State machine using case statements

always @(state or X)
begin
case (state)
SO: if(X)
next_state = S1;
else
next_stage = S0;

S1: begin //delay some positive edges of clock

repeat(`Y2RDELAY) @(posedge clock);
next_state = S2;
end

S2: begin //delay some positive edges of clock

repeat(`R2GDELAY) @(posedge clock);
next_state = Sa3;
end

S3: if(X)
 next_state = S3;
else
next_stage = S4;
S4 : begin // delay some positive edges of clock
repeat(`Y2RDELAY) @(posedge clock);
next_state = S0;
end
end
endmodule;

Output simulation
Defining Clock -

Figure 2.4: Defining clock value

Case 1 :X = 0 (means no vehicle on the country road)

 Figure 2.5: Simulation result at X = 0;

Case 2 :X = 1 (means its traffic on the country road)

Figure 2.6: Simulation result at X = 1;

Conclusion: A smart Traffic Light Controller system is designed using FPGA for four roads
intersection with traffic sensors and walk request signals.
The system has been simulated using VHDL to realize alternating traffic light and FSM for
efficient T.L.C. with ability to change its
timing parameters manually. Each subcomponent is constructed and tested thoroughly before
moving onto the next one. The design is
robust; all the design decisions were inspected comprehensively before employment.
Synchronization component are very important in
the system design where they are implemented without any hazards in the system. Overall the
design and implementation of the traffic
light controller is respectable to design more complex system. The system is verified on
FPGA Spartan 3E xc3s500efg320-4

Case 3: After changing on more cycles and keeping (X = 0)

Figure 2.7: Simulation result after changing cycle value.

Project 2: ARITHMETIC LOGIC UNIT

SOFTWARE REQUIRED: Xilinx,Vivado

INTRODUCTION:
Arithmetic Logic Unit is the part of a computer that performs arithmetic operations on
binary numbers. On the contrary, FPU (Floating Point Unit) works on decimal values.
This ALU is comprised of CPU (Central Processing Unit), Floating Point Unit (FPU),
GPU (Graphical Processing Unit. Thus, a single CPU or FPU might contain many
ALU’s. The inputs to an ALU are the data where we have to perform operations. They
are called operands. They perform the necessary operation and the result is the output of
the operation we have performed. Thus, the ALU consists of input or output or even both.
They also contain results of previously performed operations or the current operation and
also registers. Registers are used to store, fetch and process data and that is being used by
the Central Processing Unit. Processor Registers are the registers that are being used by
the CPU for processing. Modern computers contain very complex Arithmetic Logic
Units. In addition to that, they might contain the Control Unit (CU) as well. Data is
moved in between ALU, memory, and registers and this operation is performed by the
Central Processing Unit (CPU).

METHODOLGY OF ARITHMETIC LOGIC UNIT:

ALU performs Arithmetic and Logical Operations.

Figure 2.8: Block diagram of ALU

Arithmetic Operations include Addition, Subtraction, Multiplication, and

Division. Logical Operations include operations using AND, OR, and NOT. It
does comparison of operations. The computer manipulates and stores numbers in
terms of 0’s and 1’s. Transistor switches are used to do these operations as they
accept values only in terms of 0’s and 1’s. Open and Closed Switch concept is
used. Open switch is a device in which no current passes through and it represents
the value ‘0’. Closed switch is a device in which current passes through and it
represents the value ‘1’.
Multiple transistors can be connected and the resulted output can be obtained. The
first transistor can be connected to the second one and in turn, control the
operation of the second transistor. The second transistor can be switched ON or
OFF depending on the state if the first processor. This is called ‘GATE’ (logical
gates) Gate is the one that allows the flow of current. Now let us see in detail
about Gates. There are 3 gates. AND, OR, and NOT gate.

OR gate:
In this, we give two inputs and get one output. If Input A is 0 and input B is 0,
then output C is 0. If input A is 0 and input B is 1, then output C is 1. If input A is
1 and input B is 0, then output C is 1. If input A is 1 and input B is 1 then output C
is also 1.

AND gate:
This AND gate again have two inputs and gives one output. If Input A is 0 and B
is 1, then output is 0. If input A is 0 and input B is 1, then output C is 0. If input A
is 1 and input B is 0, then output C is 0. If input A is 1 and input B is 1 then output
C is also 1.

NOT gate:
NOT gate generally consists of 1 input and 1 output. If input A is 0 then output B
is 1. If input A is 1 then output B is 0.

XOR gate:
The X or is the reverses version of the OR gate. In XOR gate if Input A is 0 and B
is 0 then output C is 0. if input A is 0 and B is 1 then output C is 1. If input A is 1
and input B is 0 then output C is 1. If input A is 1 and B is 1 then output C is 1.

NOR gate:
In the NOR gate if input A is 0 and B is 0 then output C is 1. if input A is 0 and B
is 1 then output C is 0. If input A is 1 and input B is 0 then output C is 0. If input
A is 1 and B is 1 then output C is 0.

NAND gate:
In the NAND gate, if input A is 0 and B is 0 then output C is 1. If input A is 0 and
B is 1 then output C is 1. If input A is 1 and input B is 0 then output C is 1. If
input A is 1

and B is 1 then output C is 0.

BIT SHIFTING OPERATIONS:

A bit shifting operation is done to shift the most significant bit either to the
right or left. There are three types of bit-shifting operations:
LEFT ARITHMETIC SHIFT:
In a left Arithmetic shift, the most significant bit is shifted towards the right. The
zeros are shifted on the right.

RIGHT ARITHMETIC SHIFT:

In a right Arithmetic shift, the most significant bit is shifted towards the left. The
zeros are shifted in the left.

RIGHT LOGICAL SHIFT:

In the Right Local Shift, the zeros are shifted to the left and the point to be noted is
the least significant bit is lost.

CODE:

Figure 2.9: Code logic for ALU.

Testbench:

Figure 2.10: Test bench for ALU

RESULTS:

Figure 2.11: Output of ALU

APPLICATIONS:
Multiple-precision arithmetic
In integer arithmetic computations, multiple-precision arithmetic is an algorithm
that operates on integers which are larger than the ALU word size. To do this, the
algorithm treats each operand as an ordered collection of ALU-size fragments,
arranged from most-significant (MS) to least-significant (LS) or vice versa. For
example, in the case of an 8-bit ALU, the 24-bit integer 0x123456 would be
treated as a collection of three 8-bit fragments: 0x12 (MS), 0x34, and 0x56 (LS).
Since the size of a fragment exactly matches the ALU word size, the ALU can
directly operate on this "piece" of operand.
The algorithm uses the ALU to directly operate on particular operand fragments
and thus generate a corresponding fragment (a "partial") of the multi-precision
result. Each partial, when generated, is written to an associated region of storage
that has been designated for the multiple-precision result. This process is repeated
for all operand fragments so as to generate a complete collection of partials, which
is the result of the multiple-precision operation.
In arithmetic operations (e.g., addition, subtraction), the algorithm starts by
invoking an ALU operation on the operands' LS fragments, thereby producing
both a LS partial and a carry out bit. The algorithm writes the partial to designated
storage, whereas the processor's state machine typically stores the carry out bit to
an ALU status register. The algorithm then advances to the next fragment of each
operand's collection and invokes an ALU operation on these fragments along with
the stored carry bit from the previous ALU operation, thus producing another
(more significant) partial and a carry out bit. As before, the carry bit is stored to
the status register and the partial is written to designated storage. This process
repeats until all operand fragments have been processed, resulting in a complete
collection of partials in storage, which comprise the multi-precision arithmetic
result.
In multiple-precision shift operations, the order of operand fragment processing
depends on the shift direction. In left-shift operations, fragments are processed LS
first because the LS bit of each partial—which is conveyed via the stored carry bit
—must be obtained from the MS bit of the previously left-shifted, less-significant
operand. Conversely, operands are processed MS first in right-shift operations
because the MS bit of each partial must be obtained from the LS bit of the
previously right-shifted, more-significant operand.
In bitwise logical operations (e.g., logical AND, logical OR), the operand
fragments may be processed in any arbitrary order because each partial depends
only on the corresponding operand fragments (the stored carry bit from the
previous ALU operation is ignored).
CONCLUSION:
We have seen the ARITHMETIC Logic Unit in detail. We have seen how to use it for
arithmetic and logical operations. We have also seen various gates and how to use them. I
hope this would be helpful to learn the concepts of the Arithmetic Logic Unit.

Summary and Future scope

VLSI electronic circuit design is possible at a variety of abstraction levels, wherein
each level, from system behavior to the most intricate physical layout, reflects a
separate model of the same information and processes, but with varying levels of
detail. Open-source electronic design automation software called VLSI Design
System can handle a variety of circuit design tasks, including custom IC layout, digital
and analogue schematic capture, textual languages like VHDL and Verilog, and more.
Additionally, using electricity is a great approach to combine several design contexts.
Using a technique called very large-scale integration, several different kinds of
electronic parts can be combined into a tiny area or chip. Basically, this technique:
Makes the device smaller Lowers the device’s cost minimizes current usage
Quickens the process of operation VLSI have better speeds and higher reliability
while using less power and less space on the circuit board.
Presently, it seems very promising to apply VLSI and signal processing
techniques in wireless mobile communications, such as for next-generation mobile
communications. The industry is experimenting with data science methodologies in
order to com- prehend VLSI better and generate fresh insights that could potentially
boost revenue. On the other hand, the research community is interested in the future
of the VLSI sector. A renewed interest has been generated by the focus on merging
VLSI + Computer architecture and system designs. However, we cannot dismiss the
importance of artificial intelligence and machine learning in contemporary technology.
We can quickly observe how artificial intelligence has influenced VLSI design and
how intriguingly Al experts and VLSI engineers have connected.
We are rapidly nearing the optical limit of photolithographic methods, beyond which
the feature size cannot be reduced due to diminishing accuracy, even on the
fabrication front. Extreme ultraviolet lithography techniques were available as a
result. use of swift clocks the power dissipation and noise levels both rise as the
number of transistors does. The chips are already getting close to the heat produced
per unit area of a jet engine’s nozzle. While complicating matters, the voltage scaling
of threshold volt- ages above a certain point offers substantial obstacles to achieving
low dynamic power dissipation. At such nanoscales, the number of metal layers and
the interconnects, both global and local, also have a tendency to become disorganized.
We are rapidly nearing the optical limit of photolithographic methods, beyond which
the feature size cannot be reduced due to diminishing accuracy, even on the
fabrication front. Extreme ultraviolet lithography techniques were available as a
result. use of swift clocks

References