nst = cst;

Binary Sequence Detector using           y=1'b0;

Mealy Machine
          end
module melfsmolp(din, reset, clk, y);
   S1: if (din == 1'b0)
output reg y;
          begin
input din;
        nst = S2;
input clk;
          y=1'b0;
input reset;
          end
reg [1:0] cst, nst;
       else
parameter S0 = 2'b00,
          begin
parameter S1 = 2'b01,
           nst = cst;
parameter S2 = 2'b10,
          y=1'b0;
 parameter S3 = 2'b11;
          end
always @(cst or din)
   S2: if (din == 1'b1)
 begin
          begin
 case (cst)
         nst = S3;
   S0: if (din == 1'b1)
          y=1'b0;
          begin
          end    
         nst = S1;
            else
          y=1'b0;
          begin
          end
           nst = S0;
      else
          y=1'b0;
          begin
          end
   S3: if (din == 1'b0)

          begin

         nst = S2;

          y=1'b1;

          end

       else

          begin

          nst = S1; TESTBENCH

          y=1'b0;

          end module melfsmolp_tb;

   default: nst = S0; reg din,clk,reset;

  endcase wire y;

end melfsmolp m1(din, reset, clk, y);

always@(posedge clk) initial

begin begin

           if (reset) reset=0       ;clk=0;din=0;

             cst <= S0; $monitor($time, , ,"c=%b",clk,,"y=

%b",y,,"r=%b",reset,,"d=%b",din);
           else
#10 din=1;
             cst <= nst;
#10 din=0;
end
#10 din=1;
endmodule
#10 din=0;

#10 din=1;
#10 din=0; //#5 reset=0;

#10 din=1; end

#10 din=1; always

#10 din=1; #5 clk=~clk;

#10 din=0; initial

#10 din=1; #100 $finish ;

//#5 reset=1; endmodule