Journal of Physics D: Applied Physics

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Review of memristor devices in neuromorphic computing: materials

sciences and device challenges
To cite this article before publication: Yibo Li et al 2018 J. Phys. D: Appl. Phys. in press https://doi.org/10.1088/1361-6463/aade3f

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Page 1 of 26 AUTHOR SUBMITTED MANUSCRIPT - JPhysD-117309.R1

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Review of Memristor Devices in Neuromorphic Computing:
5 Materials Science and Device Challenges
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8 Yibo Li, Zhongrui Wang, Rivu Midya, Qiangfei Xiaa, and J. Joshua Yangb

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Department of Electrical and Computer Engineering, University of Massachusetts
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13 Amherst, Amherst, MA 01003, USA

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15 a)
Qiangfei Xia. Electronic mail: qxia@umass.edu
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17 J. Joshua Yang. Electronic mail: jjyang@umass.edu
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20 The memristor is considered as the one of the promising candidates for next generation computing systems. Novel

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22 computing architectures based on memristors have shown great potential in replacing or complementing
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24 conventional computing platforms based on the von Neumann architecture which faces challenges in the big-data
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era such as the memory wall. However, there are a number of technical challenges for implementing memristor

based computing. In this review, we focus on the research performed on the memristor material stacks and their

30 compatibility with CMOS processes, the electrical performance, and the integration. In addition, recent
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32 demonstrations of neuromorphic computing using memristors are surveyed.
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35 I. INTRODUCTION
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38 Demand for a more powerful computing device
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40 Over the past few decades, driven by the rapid growth of information technology markets, the performance of
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42 computing system has been dramatically improved over time thanks to the Moore’s Law. The computing
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44 efficiency is considered as a new benchmark in addition to the computing capacity, which is of great significance
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46 in the big data environment, for example, Internet-of-Things (IoT) and autonomous vehicles [1, 2]. To improve
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48 the computing efficiency further, electronic devices need to be scalable to reduce the fabrication cost, increase the
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50 speed, and lower down the power consumption. Due to the physical limitations and the manufacturing cost, sub
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52 10-nanometer technology nodes of traditional CMOS transistor cannot afford cost-effective and sustainable
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54 scaling [3], which therefore calls for novel electronic devices with superior computing efficiency to meet the
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56 demands of the ever-increasing information technology markets.
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58 The Memristor
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 AUTHOR SUBMITTED MANUSCRIPT - JPhysD-117309.R1 Page 2 of 26

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3 Various new electronic elements have been explored in this regard thus far. Among them, the memristor is a
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5 new 2-terminal device with a number of attractive properties [4, 5, 6]. The prototypical memristor (memory +
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7 resistor) devices reported by HP Labs has a capacitor structure consisting of two Platinum (Pt) electrodes
8

pt
9 sandwiching a bilayer dielectric. The dielectric comprises of a stoichiometric titanium oxide layer and a non-
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11 stoichiometric titanium sub-oxide layer (TiO2/TiO2-x) [7]. (See Figure 1) In this prototypical device, the memristor
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13 conductance can be modulated by applying a voltage bias across the electrodes. The electric field is capable of

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15 relocating the interface between the TiO2 and the TiO2-x layers due to the migration of oxygen vacancies (VO2+).
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17 Since then, the research interest in memristor has boomed, manifested by a large number of publications.
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32 FIG. 1. The Pt/TiO2-x/TiO2/Pt memristor. The equivalent circuit shows that the device resistance can be changed by applying
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33 a voltage bias which modifies the resistance of the TiO2-x and the TiO2 layers. (Reprinted from Ref [6], Copyright from 2008
34 Springer Nature)
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37 The ability to encode the biasing history makes the memristor suitable for the potential application as a
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storage class memory. Unlike dynamic random access memory (DRAM) or static random access memory
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(SRAM), the storage class memory, usually based on floating gate transistors or magnetic storage, operates at a
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42 slower speed but has a higher density and nonvolatility. To surpass the performance of the floating gate transistors
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44 and the magnetic storage, the feature size of the novel memory element is preferred to be less than 10 nanometers
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46 to achieve high density integration. The device should be able to retain its state for years and possess large write-
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48 erase endurance at a reasonable switching speed. The device switching energy per operation should be in the pico-
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50 joule range or lower for a compelling energy efficient [8] and compatible with the circuits that are to be driven,
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52 which are comprised of advanced CMOS technology nodes. So far, great performance in each aspect has been
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54 attained with different memristors. Although it is challenging to demonstrate all the best figures of merit in a
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56 single material system, the memristor has shown a great potential which makes it a strong candidate as the next
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58 generation storage class memory.
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3 In addition to storage, memristors with multiple analog states are capable of actively processing information,
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5 via the so called in-memory computing scheme. In-memory or near-memory computing with SRAM, DRAM, or
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7 flash memory [9, 10] provides a highly parallel alternative to resolve the “memory wall” of the von-Neumann
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9 architecture [11] that the data processing and the data storage are separated. This separation results in low
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11 efficiency for data-centric tasks due to the high cost of time and energy in data transferring between the memory
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13 and the processing units. In contrast, the memristor based in-memory computing is free of the bottleneck of von-

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15 Neumann architecture as data are stored and processed in the same location.
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17 In the following sections, we will firstly analyze the material system engineering and challenges. Then, the
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19 electrical performance and the non-idealities of memristor are discussed with implications to neuromorphic
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21 computing related applications. Finally, memristor based neuromorphic computing architectures and the recent
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23 research are reviewed.
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26 II. Material System Engineering
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Oxide based memristors
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32 Similar to the memristor structure used by HP in 2008, most memristors are built using simple capacitor like
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structures consisting of electrodes and a switching layer. Memristive switching layers are generally comprised of
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dielectrics. The dielectrics used are mainly binary oxide materials such as Silicon Oxide (SiO2) [12], Titanium
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Oxide (TiO2) [13], Copper Oxide (CuO) [14], Nickel Oxide (NiO) [15], Zinc Oxide (ZnO) [16], Hafnium Oxide
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39 (HfO2) [17], Tantalum Oxide (Ta2O5) [18] and Aluminum Oxide (Al2O3) [19]. The memristors made from these
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41 materials have shown promising resistive switching performance. Depending on the material system, the resistive
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switching characteristics could either be abrupt (binary) or gradual (analog). The abrupt resistance change is
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45 suitable for storing or processing binary data, and the gradual resistance change is more suitable for storing
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47 multiple resistance states for analog computing. Resistive switching devices based on NiO dielectric have been
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49 documented in many references. [20] It possesses large ON/OFF ratio and unipolar switching properties. However,
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51 there are many issues associated with NiO-based memristors. One of the more important ones is the fact that such
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53 devices usually suffer from a high RESET current which make them less suitable for low-power applications. In
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55 addition, NiO devices show unipolar switching and hence might be subject to voltage overlapping issues for SET
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and RESET processes. When that happens, the device write-erase performance deteriorates. Unlike NiO, ZnO is
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a wide-bandgap material and possesses unique optical properties. ZnO-based memristors are well-suited for being
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fabricated on transparent and flexible substrates, such as polyimide (PI) [21] and polyethylene terephthalate (PET)
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3 [22]. M. Wang et al. used MoS2-xOx, which is a 2D material as the switching material and Graphene as the electrode
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5 material to achieve reliable resistive switching at a temperature of 340 °C for the first time [23]. They successfully
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7 fabricated the device on PI substrate for flexible electronic applications. One of the advantages of the CuO-based
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9 memristor is that CuO is compatible with the CMOS process[24]. Al2O3 is another widely used dielectric material.
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11 It is generally used in low-current applications by pairing Al2O3 with another switching layer to limit the device
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13 current [25]. SiO2 is an oxide material with excellent CMOS compatibility, and it can be used as either the

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15 memristor switching layer or selector dielectric layer to provide outstanding I-V nonlinearity in one RRAM (1S1R)
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17 crossbar configuration [26].
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19 The write and erase operations of a memristor are performed by applying voltage/current pulses with
20

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21 appropriate amplitude and polarity on memristor electrodes. It is believed that the Joule-heating effect induced by
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23 the voltage stimulus plays a critical role in the formation and rupture of localized conduction paths of oxygen
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25 vacancies in the oxide layer. Although at the initiation of memristor research, there were a lot of potential candidate
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materials for building memristors, very few materials were CMOS compatible and also led to superior device

performance. Nowadays. only these oxides are used frequently as memristive dielectrics. A few of them are HfO2
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Ta2O5, TiO2, SiO2 and Al2O3.
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32
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33 Phase change memristors
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35 In addition to the metal oxide memristor, PCM (Phase Change Memory) can also be considered as a
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37 memristor device. PCM devices are mainly built out of Chalcogenide materials. Ge2Sb2Te5 is one of the prime
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39 examples of a chalcogenide which is extensively used to build PCM devices. It can change its phase between
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41 crystalline and amorphous states when current pulses are applied to it due to Joule-heating [27]. When a short and
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43 large current pulse is applied to RESET a PCM device, a part of Ge2Sb2Te5 starts to melt. When a current pulse
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45 amplitude rapidly decreases, the atomic structure of Ge2Sb2Te5 melted part becomes disordered and thus it
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47 transforms to an amorphous phase. When cooled down quickly, the PCM device transitions to its high resistance
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49 state. When a small current pulse with a long pulse time is applied to SET PCM, the melted part of Ge2Sb2Te5
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51 stays in a temperature range between crystallization and when it is completely melted. The Ge2Sb2Te5 is then
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53 transformed back to a crystalline phase with a low resistance if cooled at a relatively slow speed.
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55 Like the RRAM type memristor device, the PCM type memristor can also achieve two or more resistance
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57 states if the applied current pulse and the threshold temperature point is carefully controlled. However, there are
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59 still many issues associated with PCM devices. Since the transition from amorphous phase to crystalline phase
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3 takes time, the SET switching speed for PCM is intrinsically slow. In addition, another challenge is the high
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5 programming current (typically is the high RESET current, above 100 µA) associated with these devices, due to
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7 a Joule heating operation principle. A high RESET current makes PCM devices incompatible with conventional
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9 access devices and consumes relatively large power. Generally, in order to decrease the PCM RESET current, the
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11 serial heating resistance is increased to generate more heat with a lower current. The same effect can be achieved
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13 by decreasing the contact area between the GST material and the device electrode by using advanced fabrication

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15 approaches to achieve a dash-shaped structure or a pore-shaped structure to replace the conventional mushroom-
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17 shaped structure [28, 29]. Another workaround is to add some dopants like B, C, N, O, SiO 2, SiN or SiC in GST
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to change the thermal properties of the crystalline state [30-35].
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21 The PCM reliability issue is also very critical. Devices can fail at either high resistance state or low resistance
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23 state. It is believed that voids and vacancies may form at the boundary between GST and electrode by repeatedly
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25 increasing or decreasing the volume of the melted GST during operation. These voids can lead to PCM cells
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getting stuck at the high resistance state. To solve this issue, carbon dopants were used inside the GST to limit the

micro-void formation [36]. The ageing issue of multi-bit PCM is also severe when there is a resistance drift if the
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GST amorphous state is unstable at a given temperature. PCM devices could also fail at a low resistance state if
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Sb is enriched to increase the RESET current which in turn blocks the Sb-rich part from getting transformed to
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34 the amorphous state.
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37 Thermal disturbances could occur in PCM cells between two neighboring PCM cells in the crossbar array if
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39 the distance between crossbar word lines and bit lines are small (sub-100 nm). When programming a target PCM
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41 cell at a high temperature, the heat may be transferred to cells nearby and this could trigger a change in the
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resistance states of those cells. This effect becomes more pronounced when the device dimensions are scaled
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down. Choosing a proper dielectric material is necessary to prevent thermal disturbances between PCM cells.
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47 Other memristors
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49 In addition to binary oxides, there are reports of other switching materials, including heterogeneous materials,
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such as cerium oxide and strontium Titanate (CeO2 and SrTiO3) [37, 38]; organic materials, such as copper-
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53 Tetracyanoquinodimethane (Cu-TCNQ) [39]; electrolytic materials, such as copper sulfide (Cu2S) [40] and
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55 chalcogenides such as silver-germanium-selenium (Ag-Ge-Se) [41]. Because of the unconventional fabrication
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3 commonly used. These materials are typically paired with metal electrodes such as Tantalum (Ta), Platinum (Pt),
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5 Palladium (Pd), Titanium Nitride (TiN) and Tantalum Nitride (TaN) [42, 43].
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III. The Materials Challenges of Memristor Dielectric and Electrode

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12 Challenge 1: Stochasticity
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14 The resistance states, the SET and RESET currents, and the working voltages of memristors usually show
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16 variations from device to device and from cycle to cycle. The memristor device-to-device variation originates
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18 from the limitations of fabrication techniques and the underlying electrochemical processes. The former yields
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20 nonideal film morphology and homogeneity, which could lead to the differences of electrical characteristics

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22 between memristors [44-45]. In addition to the device-to-device variation, the temporal stochasticity is reflected
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by the cycle-to-cycle variations [45-46], which is typically caused by the randomness in conducting path formation
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and rupture processes. Such spatial and temporal stochasticity is a double-edged sword. It is unfavorable for
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applications like storage class memory. However, the variability may also be utilized for hardware security

applications like random number generators and physical unclonable functions [47, 48].
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32 Techniques are used to eliminate the impact of stochasticity for applications requiring stringent accuracy.
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34 Raqibul Hasan et al. proposed an iterative method to program 0T1M memristor crossbar arrays with feedback to
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36 overcome the device stochasticity [49].
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38 The stochasticity is favored for security applications. In 2014, Siddharth Gaba et al. found that the
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40 randomness of a single filament in a-Si follows a Poissonian distribution. The variability of memristor switching
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42 behavior is dependent on the voltage pulse amplitude and width, which can be used for unconventional computing
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44 applications such as the random number generator [44]. Similarly, the intrinsic stochasticity of the delay
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46 mechanism of the Ag diffusive memristor was used by Jiang et al. to build a true random number generator [50].
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The stochasticity could also benefit operations of memristor based neural networks. Walt Woods et al. found
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that certain stochasticity of memristors could compensate the limited number of memristor synaptic weight states
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52 [51]. Maruan Al-Shedivat et al. has proposed a method to exploit the stochasticity of memristor switching to avoid
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54 the noise generation circuit in building the WTA neuron network [52]. Jie Lin et al. used the built-in stochasticity
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56 of the memristor to model the stochastic neuronal behavior in a deep belief network [53]. Rawan Naous et al.
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58 found that the inherent variability of the memristor can benefit the area efficiency and power consumption of the
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60 crossbar memristive synapses [54]. Manan Suri et al. proposed a hybrid RBM architecture, they found that the
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3 memristor cycle-to-cycle resistance variability can help to implement the necessary stochasticity function for their
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5 RBM system [55].
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Challenge 2: CMOS compatibility
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10 The second challenge comes from the compatibility with the existing CMOS fabrication processes. Bipolar
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12 switching redox memristors with asymmetric electrodes, a noble metal electrode paired with an active metal
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14 electrode serving as the oxygen reservoir, have been reported of decent performance [56]. However, state-of-the-
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16 art CMOS processes are not optimized for patterning inert metals like Pt or Pd [57]. Recently, CMOS compatible
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18 electrodes like TiN and TaN are used as alternatives even though they are not as inert as Pt when interfacing with
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switching oxides. These two materials can perfectly fit to the CMOS transistor fabrication process, but due to the
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compound nature, the fabrication process of either TiN and TaN requires careful engineering of the atomic ratio
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23 between Ti, Ta and nitride to retain the high electrical conductivity while being less chemically active compared
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29 IV. Expectations on Electrical Performance
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31 The expectations of the performance of the memristor vary with the application. As mentioned in Section I,
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33 for memory applications, the memristor is favored to have a programming voltage below 1.8V (i.e. the supply
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35 voltage of the 90 nm CMOS nodes). In addition, the maximum programming current should not go beyond 100
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µA to simplify the design of the driven circuits. In terms of the operation speed, the memristor features for fast
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switching which could take as short as 100 ps per SET or RESET transition. In addition, the memristor, particularly
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40 redox memristor with oxide switching medium, exhibits endurance beyond 1×106 cycles, better than that of the
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42 floating gate transistors, and projected retention longer than 10 years at room temperature. As discussed in Section
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44 III, the smaller the device-to-device and cycle-to-cycle variation, the easier the operation of the memristor based
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46 storage is.
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On the other hand, the memristor used for neuromorphic computing needs to possess the analog switching
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characteristic. The analog programming with predictable conductance change by using identical electrical pulses
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52 is highly desirable for the memristor based neural networks [58]. The performance of the training depends on the
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54 yield of such programming protocols [59] and the accuracy of voltage-to-conductance multiplication in memristor
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56 crossbar arrays. The latter is mainly contributed by the crossbar wire resistance which consumes the input voltages
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3 V. Challenges and Strategies for Memristor Integration
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6 Since 2008, there have been many attempts to implement memristor based hardware neuromorphic
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computing, by using crossbar integration of memristors. However, most networks demonstrated so far is
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comprised of less than 1000 memristors per crossbar, which hinders practical applications of the memristor neural
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11 networks. The lack of large scale memristor integration is because of the following two reasons. The first reason
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13 is that, to integrate more memristor devices into one crossbar matrix, the effect of the parasitic wire resistance of

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15 the crossbar will be intensified, which could significantly lower the precision of the weighted sum of the array.
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17 The other reason is the fact that the device-to-device variation, which could adversely impact the programming.
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3D stacking
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22 One of the possibilities to address the integration challenge is to stack memristor crossbars in three-
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24 dimension (3D) [60] so that the parasitic wire resistance of each individual crossbar layer could be less significant.
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26 Since the cognitive operations in the high-dimensional space relies on large amounts of weights, it naturally
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requires high memristor density. Hence the 3D vertical stacking of memristor crossbars can be advantageous in

30 terms of integration density per area. For example, C. Li et al. demonstrated the 3D stacking of a silicon oxide
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based self-rectifying memristor [61] which features the large projected device packing density as it does not need
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external selecting devices to suppress the intra-layer and inter-layer sneak path currents. This illustrates the
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35 opportunity for low-cost and high density integration of memristors.
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38 Scaling
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40 The variability issue may potentially be addressed by scaling down the size of the memristor. The state-of-
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42 the-art memristor feature size is about 10 nm [62]. The variability of device electrical characteristics is associated
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44 with the randomness of filament formation process. Theoretically, it is possible to scale down the memristor device
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46 size to the atomic level [63]. If the memristor size is decreased even further, the filament could potentially be
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48 confined to a smaller volume so that the population and morphology of the filament could be better regulated.
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50 With a single filament of a volume comparable to that of the device, not only can the uniformity of the devices be
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52 improved. Decreasing the memristor size may also help to reduce the programming current of the memristor and
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54 thus result in lower power consumption.
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57 VI. Review of Recent Memristor Performance for Neuromorphic Computing

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60 Conventional and in-memory computing
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4 The conventional computing system is usually built around a system that includes CPU [64], graphics
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7 processing unit (GPU) [65] or field programmable gate array (FPGA) [66]. Such a system could simulate neural
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9 networks in a sequential manner. The GPU features for better parallelism pipelines than CPU.
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11 A more revolutionary platform is in-memory computing where the memristor array embodies the neural
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13 network by storing weights and performing forward passes. In recent years, many research groups have developed

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15 memristor neural networks. Figure 2 shows the conventional computing architecture of CPU, the GPU computing
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17 architecture with fast memory access speed, and memristor based computing structure.
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37 FIG. 2. The conventional computing architecture of CPU, the computing architecture of GPU with fast memory access, and
38 the memristor based computing structure. (Reprinted from Ref [86], Copyright from 2018 Macmillan Publishers Limited)
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41 Literature survey of memristor based neuromorphic computing
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F. Alibart et al. demonstrated pattern classification using a TiO2-x based memristive crossbar circuit by
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45 building a single-layer perceptron network [67]. The I–V characteristic is nonlinear for TiO2-x devices, so TiO2-x
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47 based memristor could limit the sneak path current in a small crossbar array [68]. They trained the perceptron
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49 network by both in-situ and ex-situ method. For ex-situ method, the synaptic weights are calculated using a
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51 software; and for in-situ method, the synaptic weights are adjusted parallelly in the memristive crossbar. The ex-
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53 situ method is easy to implement and it may require a shorter training time and have a lower efficiency in synaptic
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55 weight updating. This work showed a proof-of-concept memristor-based ANN. By extending this work into a
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large-scale circuit, it can be used to implement complicated Neural Networks, such as CrossNets and a variety of
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hybrid ANN circuits and recurrent Hopfield networks. M. Prezioso et al. experimentally demonstrated a transistor-
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60 free memristor crossbar array with oxides of TiO2-x/Al2O3 stack [69]. In this work, a memristor needed with a low
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3 variability was required. The authors tried to decrease the forming voltage to reduce the memristor variability and
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5 current overshoot effect by increasing the TiO2-x conductivity and controlling the oxygen concentration in the
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7 TiO2-x layer. However, the TiO2-x does not have enough non-linearity to support the crossbar operation, so the
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9 authors added an additional Al2O3 layer to increase device I-V non-linearity. However, this approach also
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11 increased the memristor forming voltage, thus a thickness tradeoff was made between TiO 2-x layer (30 nm) and
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13 Al2O3 layer (4 nm). Figure 3a shows the convergence of memristor crossbar outputs in the training and Figure 3b

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15 shows the output signals of neurons z, v and n. The device uniformity is sufficiently high to allow the operation
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17 in a single layer perceptron. This crossbar network can be trained in situ by using the coarse-grain variety of the
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delta rule algorithm. The CMOS/memristor system the authors made could classify a 3x3 pixel image into three
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different classes.

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36 FIG. 3. (a) The trend of convergence of crossbar outputs in the training process, from initial states to zero for six training runs,
and (b) The output signals of neuon z, v and n in 60 epochs. (Reprinted from Ref [69], Copyright from 2015 Macmillan
37 Publishers Limited)
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39 In 2015, to achieve the internal dynamics and enhance the efficiency of learning algorithms in recurrent
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41 neural networks, Lei Deng et al. proposed an iron-oxide (FeOx) based memristive network to support the complex
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43 learning function [70]. The authors carried out pre-form and RESET for FeO based memristor to achieve analog
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45 resistance states. They believed the LTP and LTD effects might be attributed to the filament geometry structure
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and the filament number. Good memristor analog behavior can be obtained by properly controlling the drift of
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oxygen vacancies and diffusion fluxes, and these two parameters are related to the electron hopping distance
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50 between sites of oxygen vacancies in FeO layer. Various timing patterns and spatiotemporal patterns of human
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52 motor neurons were successfully learned in this framework. M. Giulioni et al. studied on-chip synaptic plasticity
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54 and used a dedicated scheme to decide the neural network parameters [71]. They found that autonomous learning
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56 shaped the stimulus selective attractors by simple visual stimuli. G. W. Burr et al. used two phase change memory
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58 (PCM) cells as one synapse [72, 73]. They used Pr1-xCaxMnO3 (PCMO) as the memristive switching layer for
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60 modeling the synapse function. This memristor can achieve optimum potentiation and depression characteristics
Page 11 of 26 AUTHOR SUBMITTED MANUSCRIPT - JPhysD-117309.R1

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3 by on the application of successive pulses for bidirectional synaptic device in neuromorphic systems. They built
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5 a three-layer perceptron network with a total of 164885 synapses trained on the MNIST database to achieve a
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7 training accuracy of 82.2%, and the simulation agreed with the experimental results. The authors found that the
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9 PCM based network could tolerate the device variability and yield issues. If the PCM device can function
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11 bidirectionally, then a linear conductance response for a high dynamic range is able to deliver high classification
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13 accuracies, Figure 4a shows the simulation result of the weight update of a memristive neural network. Figure 4b

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15 shows the experimental accuracy for the training of a three-layer perceptron of PCM device based crossbar array.
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17 In 2016, A. Pantazi et al. reported a memristor based neuromorphic architecture where both neurons and synapses
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were constructed using PCM devices [74]. This crossbar architecture had been used previously in performing
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unsupervised learning and detection of temporal correlations in parallel input. This paper demonstrated that the

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22 memristor based neuromorphic system is able to learn multiple correlations from a large number of input vectors
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24 in an unsupervised manner. Figures 5a to 5c show the experimental results for detecting the spatio-temporal
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26 patterns. Apart from PCM, Ag based redox memristors have been used to emulate both synaptic and neural
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dynamics. The Ag threshold switches, also termed as diffusive memristors, share similar temporal dynamics with

30 ion channels of neurons [75]: the Ag movement in the diffusive memristors can resemble the synaptic Ca2+
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32 behavior and thus lead to direct and natural functions of a bio-realistic synapse for both short-term and long-term
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34 plasticity, such as PPF, PPD and STDP, as shown in Figure 6a. In addition to being a synapse emulator, the
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36 diffusive memristor can also act as a selector with a large device I-V nonlinearity, which enables operations in a
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38 large crossbar array. On pairing these diffusive memristors with traditional non-volatile memristors (drift
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40 memristors), the combined synapses were capable of faithfully emulating spike-timing-dependent plasticity
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(STDP), one of the most important learning protocols of bio-neural system, as shown in Figure 6 b. The diffusive
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memristor could also be exploited to replicate the integrate & fire functions of neurons [76], either with a capacitor
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45 in parallel or the intrinsic Ag accumulative switching, which could work with drift memristive synapses in synergy
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47 on a fully memristive network chip, as shown in Figure 6c. Such a network provides a general platform for
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49 demonstrating simple functions at a system level, such as a convolutional neural network with unsupervised
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training, as shown in Figure 6d. T. Breuer et al. designed the Complementary Resistive Switching (CRS) RRAM
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53 based fuzzy logic gate by using Ta2O5 as the switching layer. They used two anti-serial RRAM devices to form
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55 one CRS device. When they changed the resistance state of each RRAM cell, the CRS devices with different HRS
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57 and LRS combinations could be utilized to achieve different logic functions [77]. The minimum and maximum
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59 gate functionality can be directly derived from the integrated CRS RRAM device. This design helps to enhance
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 AUTHOR SUBMITTED MANUSCRIPT - JPhysD-117309.R1 Page 12 of 26

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3 the efficiency of the sorting network for analogous data processing. S. Barbera et al. analyzed the dynamic resistive
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5 switching based on Ag2S in electrochemical metallization cells for synaptic plasticity implementation. The
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7 switching mechanism during SET process is based on the oxidation of Ag into Ag+ at the top electrode. During
8

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9 RESET process, the reduction of Ag+ ions at the top electrode can increase device resistance. This reversible effect
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11 leads to a bipolar memristor analog switching behavior, which results in the observed short term to long term
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13 transition [78]. The authors found that the observed synaptic features like short-term plasticity, long-term plasticity,

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15 and STDP are all associated with the filament stability during Joule-heating. These synaptic features have an
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17 interplaying role and are responsible for object motion detection in a spike-based neuromorphic circuit. A. Serb
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et al. proved that the TiO2 based memristors can be used to model complicated weight-dependent plasticity [79].
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The capability of TiO2-based memristors to enable conditional probabilities is largely reliant on the ability to

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22 support gradual resistive switching by applying successive pulse to stimuli. They demonstrated unsupervised
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24 classification, forgetting and relearning in a WTA network. Their method can be used to process the unlabeled
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26 data and adapted to the time-varying clusters to support reversible unsupervised learning. I. Gupta et al.
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demonstrated that the intrinsic properties of Memristive devices can be harnessed to compress information

30 contained by neural spikes in real time [80]. The authors fabricated a solid-state TiOx memristors with a metal-
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32 insulator-metal structure. This device was able to achieve a gradual resistive state transition. When pulses were
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34 applied with an amplitude exceeding the device’s inherent bipolar switching threshold, the devices acted as
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36 threshold integrators, and were able to build the “zero phase -shift dynamic system”. The voltage threshold of
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38 TiOx based memristor was used to discriminate recorded spiking patterns from the background noise and the
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40 amplitude and frequency could be transduced and stored in one single memristor. Their method has the potential
41
to be generalized for enabling smart data compression in distinct sensing platforms.
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57 FIG. 4. (a) Simulation of neural network shows that the weight update of memristor crossbar is as effective as the weight
58 update of conventional rule, and (b) the experimental accuracy for training three-layer perceptron of PCM devices based
crossbar array. (Reprinted from Ref [72], Copyright from 2015 IEEE)
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56 FIG. 5. Experimental results for detecting spatio-temporal patterns. (Reprinted from Ref [74], Copyright from 2016 IOP
Publishing)
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38 FIG. 6. Ag diffusive memristor for both synaptic and neural dynamics emulation. (a) Short-term synaptic plasticity exhibited
by a single diffusive memristor (b) Spike-timing-dependent plasticity with non-overlapping pulses using paired diffusive
39 memristor and drift memristor (c) Fully memristive neural network consisting of diffusive memristor neurons interfacing with
40 drift memristor synapses. Each diffusive memristor neuron is paired with an external capacitance. (d) Schematic illustration
41 of a simple convolutional network built on the fully memristive network chip to cluster simple patterns. (Reprinted from Ref
42 [76], Copyright from 2018 Macmillan Publishers Limited)
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44
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46 In 2017, A. Sebastian et al. developed a crossbar architecture with one million phase change memory devices to
47
run a high performance computation. The results show that the memory system can process U.S weather data
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49
using computation and storage components with nanoscale dimensions to achieve a highly-dense, low-power
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consumption, and parallel computing system [81]. Figures 7a to 7c show the mapping processes of a 1000 × 1000
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53 pixel black-and-white picture, and 7d to 7f show the generation of the rainfall data stochastic processes in USA
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55 by uncentered covariance matrix in the crossbar array. P. M. Sheridan et al. implemented sparse coding algorithms
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57 in an analog memristor based crossbar array experimentally. The authors had fabricated and characterized a
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59 tungsten oxide-based memristive device, which showed reliable synaptic behavior with good endurance. The
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3 memristive behavior is attributed to the migration of oxygen vacancies driven by voltage bias, and it can modulate
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5 the interplay between Schottky barrier emission and tunneling at the WOX and electrode interface. This memristor
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7 network enables energy efficient pattern matching and allows input data to be sparsely encoded. The crossbar also
8

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9 allows matrix multiplication to run directly in the analog mode. No stored weight is needed to be read first [82].
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11 Figures 8a to 8h present the experimental and simulated results of a patch reconstruction process by the LCA
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13 algorithm and offline-learned dictionary based on WTA. P. Yao et al. had shown an analog RRAM based crossbar

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15 network to experimentally demonstrate the grey-scale face classification using 1024 RRAM cells [83]. To achieve
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17 a robust analog switching behavior with a good cell-to-cell uniformity, the authors used HfO2 and AlOx as the
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switching layers. As HfO2 is well-known for being phase-stable, the HfOx/AlOy combined structure can control
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the generation of oxygen vacancies in the RRAM fabrication. The ratio between the HfO2 layer and the Al2O3

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22 layer was well adjusted in the experiment and optimized to be 3:1. This RRAM showed better analog performance
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24 whencompared to the TiN/TaOx/HfO2/TiN RRAM structure. The results showed that the energy consumption of
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26 this RRAM crossbar system with write-verify schemes was significantly reduced, the converging speed was faster
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and the recognition accuracy was improved. Figures 9a to 9c show examples of training patterns with one hundred

30 noise pixels, and the comparison between two different schemes based on the latency, energy, and accuracy,
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32 respectively. M. M. Shulaker et al. fabricated a RRAM crossbar nanosystem. This system has more than 1×106
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34 RRAM devices and more than 2×106 carbon-nanotube field-effect transistors to achieve a vertical stacked
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36 structure [84]. The RRAM stack was optimized to achieve threshold voltages that were able to meet the voltage
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38 requirements for the logic gates and sensors used in the monolithic 3D system design. The authors used this system
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40 to sense and classify the ambient gas. The nanosystem was compatible with state-of-the-art CMOS technology.
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Figures 10a to 10d show the data sensed for seven different gases, and the data was successfully distinguished by
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RRAM 3D crossbar system.

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23 FIG. 7. (a) The processes are mapped on to a 1000×1000 pixel black-and-white picture, the pixels turn on and off with the
24 PCM memristor in two resistance states. (b) The PCM devices associated with the processes go to a high conductance state.
(c) The distribution of PCM device’s conductance, it indicates the algorithm is able to demonstrate the most of the correlated
25
processes. (d) The generation of the rainfall data stochastic process from multiple weather stations in the USA. (e) The
26 uncentered covariance matrix in crossbar associated with weather conditions at different geographical regions. (f) The map of
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Copyright from 2017 Abu Sebastian et al.)
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device conductance levels show the dominant group is able to achieve a higher conductance value. (Reprinted from Ref [81],

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59 FIG. 8. (a) A 120×120 pixel image, (b) the image is split into 4×4 patches, (c) the reconstruction of the patch by using the
60 16×32 memristor crossbar with LCA algorithm and offline-learned dictionary based on WTA, (d), the neurons’ membrane
Page 17 of 26 AUTHOR SUBMITTED MANUSCRIPT - JPhysD-117309.R1

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3 potential associated with the iteration number in LCA analysis, (e) the experimental demonstration of the reconstruction image
4 according to the reconstructed patches, (f) the simulation of reconstruction image by using the offline trained dictionary, (g)
5 the simulation of reconstruction image by using the sparse coding and gradient descent, and (h) the simulation of reconstruction
image with memristor variabilities in the online learning. (Reprinted from Ref [82], Copyright from 2017 Macmillan
6 Publishers Limited)
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22 FIG. 9. (a) An example of the training patterns with one hundred noise pixels, (b) the curves of two programming recognition
23 rates in the test, (c) the comparison between two schemes based on the latency, energy, and accuracy in the training. (Reprinted
24 from Ref [83], Copyright from 2017 Peng Yao et al.)
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FIG. 10. (a) The data sensed from seven different gases, the data were written into the RRAM from a 3D crossbar array with
46 2048 cells, (b) and (c) the output from a CNFET classification accelerator as a function of exposing to vapors of lemon juice
47 and rubbing alcohol, respectively, (d) the sensor data shows that the RRAM nano-crossbar array can successfully distinguish
48 the nitrogen and other six vapors. (Reprinted from Ref [84], Copyright from 2017 Macmillan Publishers Limited)
49
50
51 B. Chakrabarti developed a hybrid 3D CMOS and memristor crossbar circuit on a CMOS substrate [85]. The
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53 memristor device exhibited analog switching behavior with controlled multi-level operations. The authors
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55 performed dot-product operations to prove its feasibility as a multiply-add engine. The memristor device had a
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Al2O3/TiOx switching stack. It was a forming-free device with low switching voltage and multi-level control of
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the states. In 2018, C. Li et al. successfully fabricated an crossbar array based on Ta/HfO2-x memristors with an
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60 equivalent precision of 6-bit (64 levels) and 8192 devices for analog-vector and analog-matrix-vector
 AUTHOR SUBMITTED MANUSCRIPT - JPhysD-117309.R1 Page 18 of 26

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3 multiplication for applications in IoT and edge computing [68, 73]. CMOS transistors are used to form 1T1R cells.
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5 The analog conductance states of the memristors were precisely controlled to 64 levels (6 bits) with linear I–V
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7 relationship. It can directly utilize Ohm’s law to perform multiplication computing. Considering the low-precision
8

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9 requirements in many applications, the precision achieved is encouraging. The authors showed that a large
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11 memristor crossbar array can implement a one-step VMM operation, featuring high-throughput and low-energy
12
13 consumption. The computing accuracy was acceptable for the machine learning applications, such as image

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15 recognition. Instead of metal-oxide based memristor, the heterostructure with 2D materials can be used to fabricate
16
17 memristor.
18
19
20 TABLE I. THE SUMMARY OF THE RECENT RESEARCH PROGRESS OF MEMRISTOR

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Memristor
22 Ron/Roff or Endurance/ SET/RESET
23 stacks (from top Vforming/Vset/Vreset tset/treset Ref
Gmax/Gmin retention pulse energy
24 to bottom)
25
Au (25)/Pt (15)/ 6 V/
26 5×10-4 S [67]
27
28
29
TiO2-x (30)/
Pt (25)/Ti (5)
-0.7 V to -1.3 V/
0.7 V to 1.2 V
/5×10 S
an
-5
200 ns/1 us N/A N/A
[86]

Pt (60)/Ti (15) 2 V/1.5 V/-1.5 V At least

30 500 us/
31 /TiO2-x (30)/ (operation current 2×104 ohm 5000 cycles/ 1e-7 J/
500 us [69]
32 Al2O3 (4)/Pt between 100 nA 6
/2×10 ohm 10 years @ 1e-9 J
dM
33 (±2 V)
(60)/Ta (5) and 100 uA) RT
34
35 TiW (100)/Pt
200 ohm At least
36 (45)/FeOx/Pt 1.6 V/-1.6 V 10 us/10 us N/A [70]
37 />550 ohm 1000 cycles.
(45)/TiW (100)
38
39 -2.5 V/2 V
Pt (80)/TiN
40 (operation current 1.67×108 ohm 100 us/ 300 nJ/pulse, [72]
(10)/PCMO >200 cycles
41 between 0.1 nA 10
/1×10 ohm 100 us ~200nJ/pulse [87]
42 (~25)/Pt (50)
and 1 mA)
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44 2×104 ohm/ 50 us (3 V)/ [75]

Pt/HfOx/TiN 4 V/1.7 V/-1.6 V N/A N/A
45 5
2.83×10 ohm 50 us (-4 V) [76]
46
Pt (25)/Ta2O5
47 In
48 (10)/Ta (10) 1.65 V/1.2 V/-0.6 4×103 ohm/ >1×106
millisecond N/A [77]
49 /Ta2O5 (10)/ V >1×105 ohm cycles.
50 range
Pt (30)
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52 about
Ag (30)/Ag2S 50 us/50 us
53 0.16 V/-0.13 V 1×103 ohm N/A N/A [78]
54 (60)/Pt/Ti (±0.4 V)
/N/A
55
56 At least
Pt (10)/
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57 3
4.5×10 ohm/ 100 us/ 1×103
58 TiO2 (25) 1 V/-1 V 22 nJ/11.7 nJ [79]
8.5×103 ohm 100 us cycles/
59 /Pt (10)
60 2.5 hours
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100 us
4 Pt (10)/TiOx
5 2×103 ohm (0.8 V)/
(25)/Pt (10)/ 6.5 V/3 V/-3.5 V >200 ~25 pJ [80]
6 /15×10 ohm3
100 us
7 Ti (5)
(-1.2 V)
8
100 us

pt
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10 (1.4 V)/ 1×105 [82]
11 Pd/WO3 (50)/W 1.25 V/-1.25 V N/A N/A
100 us cycles. [88]
12
(-1.4 V)
13

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14 TiN/ 50 ns
61.16 nJ
15 TaOx (60)/ 2.5×10 ohm4
(2 V)/ >1000
16 2 V/-3 V (write- [83]
HfAlyOx (8) /1.5×105 ohm 50 ns cycles
17 verify)
18 /TiN (-2.3 V)
19 Pt/Ti/TiN/ 7×102 ohm/
20 3.5 V/2 V/-2 V 10 us/10 us N/A N/A [84]
HfOx (5)/Pt 1×107 ohm

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22 Pt/Ti/Al2O3(3)/
5×103 ohm/ >500 cycles/
23 TiOx(30)/Pt(60) 0.7 V/-0.7 V N/A N/A [85]
24 5×104 ohm 10000 sec
/Ta(5)
25
26 At least
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Ta (50)/
HfO2 (5)/ 1.1 V/-1.3 V
2×103 ohm/
6
1×10 ohm
an 50 ns/50ns
1×106
cycles/ N/A
[68]
[73]
30 Pd (60) 10 years @
31 RT
32
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TABLE I shows a detailed comparison of memristor electrical parameters published recently, metal oxides such
35
36
asTiO2, HfO2, WO3, Ta2O5 are frequently used as device resistive switching layer. Although the resistive switching
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38 mechanism may vary from one device to another (e.g. oxygen vacancies filament or Ag ion redox reaction), the
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40 memristor devices need to have either analog hysteresis I-V curves or multi-bit resistance states to model the
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42 weight change of chemical synapses. The stability of electrical characteristics can be controlled by adding extra
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44 layers (e.g. a Al2O3 layer) or introducing a CMOS transistor. The electrode materials for these devices are mostly
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46 inert metals like Pt or Pd, which are not friendly to the semiconductor foundry mainly due to etching issues, an
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48 alternative TiN electrode with a low resistivity may be needed for commercialization. In addition, the
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50 forming/SET/RESET voltages and read current levels in the low resistance state for these memristors are still too
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52 large in most cases. The CMOS transistor with 90 nm or a smaller node may not be compatible as the transistors
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54 has a high risk to be damaged in these voltage and current ranges. In addition, the corresponding energy
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56 consumptions are high. Besides, device forming operations may need extra circuit cost in order to provide a high
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voltage and a large driving current. Generally, the memristor itself can work at a very high speed (a nanosecond
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or lower is possible). However, the data shown in the table are mostly in micro-second range. Part of the reason
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1
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3 might be that the speed of selector device is not compatible with that of the memristor. The endurance performance
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5 of these devices looks promising when compared with FLASH memory, but still, the variability issue can
6
7 substantially narrow the ON/OFF window. The retention at elevated temperatures (>85 ℃) can be an issue for
8

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9 PCM based memristor, which is more severe considering the thermal disturbance issue in operating PCM crossbar
10
11 arrays.
12
13 VI. Conclusion

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16 To overcome the shortcomings of the conventional computing systems based on the von Neumann
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18 architecture, memristor based computing platforms have been proposed to deliver high computing efficiency for
19
data centric applications. Although significant progresses have been made in this field in the past few years, there
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are still a number of challenges ahead.
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24 Material system engineering is critical to resolve the issues on the stochasticity and the CMOS compatibility,
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26 which impacts on the underlying electrical performance. The ultra large scale integration of the memristive devices
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is partly hindered by the parasitic wire resistance and the device variability. To address the integration challenge,

30 3D stacking could be a potential solution. Further Material and device development is still critical to address the
31
variability and device non-ideality issues. On the other hand, designing new algorithms, architecture or circuits
32
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can be very effective to take care of these issues, but has not been fully developed yet.
34
35
36
37 REFERENCE
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