J Electron Test

DOI 10.1007/s10836-016-5573-5

A 10-Transistor 65 nm SRAM Cell Tolerant

to Single-Event Upsets
Yuanqing Li 1 & Lixiang Li 2,3 & Yuan Ma 2 & Li Chen 1 & Rui Liu 1 & Haibin Wang 1 &
Qiong Wu 4 & Michael Newton 1 & Mo Chen 1

Received: 28 May 2015 / Accepted: 15 February 2016

# Springer Science+Business Media New York 2016

Abstract A novel SRAM cell tolerant to single-event up- Keywords Alpha particle . Proton . Single event upset
sets (SEUs) is presented in this paper. By adding four (SEU) . Soft error rate (SER) . SRAM
more transistors inside, the proposed circuit can obtain
higher critical charge at each internal node compared to
the conventional 6-transistor (6T) cell. Arrays of 2k-bit 1 Introduction
capacitance of these two designs were implemented in a
65 nm CMOS bulk technology for comparison purpose. In modern application specific integrated circuits (ASIC) and
Radiation experiments showed that, at the nominal 1.0 V system-on-chips (SOC), embedded static random access
supply voltage, the proposed cell achieves 47.1 % and memories (SRAMs) can act as major contributors of soft-
49.3 % reduction in alpha and proton soft error rates errors induced by single-event upsets (SEUs), because they
(SER) with an area overhead of 37 %. can occupy a significant portion of chip area (50 % and
higher) [16]. On the other hand, the scaling of technology
continuously reduces the critical charge of single bit-cells,
which severely increases their sensitivity to SEU [1, 2, 6].
Responsible Editor: S. Kajihara
Therefore, the protection against SEUs is critical and is also
Lixiang Li equally contributed to this work as the first author. becoming more challenging for SRAMs fabricated in ad-
vanced technologies.
* Lixiang Li Until now, various methodologies have been developed by
lx829382@dal.ca
the radiation effects community to harden SRAMs against
soft-errors. At the system-level, error correction codes
Yuanqing Li
yuanqing.li@usask.ca (ECCs) are suitable solutions given the very regular architec-
tures of SRAM arrays [7, 11, 15]. The protection ability of
Yuan Ma
each ECC solution (amount of errors can be corrected) de-
yuan.ma@dal.ca
pends on its specific algorithm [11]. As system-level harden-
Qiong Wu ing approaches, ECCs commonly involve less custom-design
qiong.wu@usask.ca
tasks, which relatively ease their implementations. However,
the additional time consumed by the error correction process
1
Department of Electrical and Computer Engineering, University of can significantly increase the access times of SRAMs with
Saskatchewan, Saskatoon, SK, Canada ECCs, and this performance degradation can be more serious
2
Department of Electrical and Computer Engineering, Dalhousie when a complex algorithm is required to guarantee the ability
University, Halifax, NS, Canada to correct more errors [5]. This drawback of ECCs can be
3
Present address: TSMC Design Technology Canada, Kanata, ON, overcome by another category of solutions which focus on
Canada the hardening of single cells. Dual-interlocked storage cell
4
College of Information and Control Engineering, China University of (DICE) is one of the most well-known solutions of this cate-
Petroleum, Qingdao, China gory [4]. For circuit-level hardening designs, one of their main
 J Electron Test

costs is the large area overhead. As analyzed in [5, 21], many
of these custom-designed circuits can be about 200 % larger
than the conventional 6-transistor (6T) cell. One reason of
their large areas is that they utilize redundancies to construct
special topologies inside to achieve error mask and recovery
for each node. Such topologies can provide very large (or the-
oretically infinite sometimes) critical charge amount at internal
nodes, which consequently results in their enhanced soft-error
resilience. Due to the excellent hardening performance, these
hardened by design (HBD) cells can be proper candidates for
products targeting extreme radiation environments (e.g., outer
space). However, applying these cells in terrestrial environ-
ments may lead to over design, since very few particles can
have high linear energy transfer (LET) there. For example, as a
significant source of terrestrial ionizing radiation, the alpha
particles emitted from the radioactive impurities in chip pack-
ages can only have a peak LET of around 1.6 MeV-cm2/mg in
silicon, and their emissivity is also low (10 ~ 10−3 a/cm2/h,
depending on different parts of packages) [3]. On the other
hand, storage density is commonly a critical metric for
SRAMs in various designs. Therefore, an appropriate balance
between cell area and improved soft-error rates (SERs) can
always be a practical requirement for terrestrial applications.
In this paper, an area efficient SRAM cell that tolerates
SEUs is presented. Compared to the conventional 6T cell,
the proposed circuit has larger critical charge amount at each
internal node, which helps enhance its soft-error resilience.
For clear description, the proposed SRAM cell is named
Soft-error-Tolerant-10T (ST-10T) in this paper. Arrays of 2k
capacitance of the 6T and ST-10T were developed and fabri-
cated in TSMC (Taiwan Semiconductor Manufacturing
Corporation) 65 nm CMOS 1.0 V technology. Alpha and pro-
ton radiation experiments were carried out on these two de-
signs, and the ST-10T shows superior soft-error resilience over
the 6T. Compared to the 6T, the ST-10T only induces an area
overhead of about 37 %, which makes it attractive in radiation
tolerant and area constraint applications.
The rest of this paper is organized as follows. Comparison
and analysis of SEUs resilience and some traditional features
of the 6T and proposed ST-10T cells are presented in Section
2. Section 3 provides the details of test chip design, radiation
experiments setup, and experimental results. Finally, this pa-
per is concluded in Section 4.
2 ST-10T SRAM bit-cell
The schematics and layouts of the 6T and proposed ST-10T
cells are depicted in Fig. 1. As shown in this figure, compared
to the 6T cell, additional four transistors P3-P4 and N3-N4 are

Fig. 1 Schematics of the 6 T (a) WL

and ST-10T (b), and layout
WL
diagrams of the 6T (c) and ST-
10T (d) P3 P4

P1 P2
P1 P2
Q QB
A1 A2 Q QB
A1 A2
N1 N2
N1 N2
BL BLB X XB
BL BLB
N3 N4

a b

VDD VDD
XB
P1

P2

P3

P1

P2

P4

Q QB Q QB
X

Q QB Q QB
XB
N1

N2

N3

N1

N2

N4
X

A1 A2 A1 A2

GND GND

c d
J Electron Test

Fig. 2 Device structures of 6T

(a) [9] and ST-10T (b) in Accuro

used in the ST-10T. The ST-10T is similar to the SRAM cell
circuit with stacked transistors used in silicon on insulator
(SOI) technologies [14, 20]. However, the main difference is
that the drains of P3 and N3 (P4 and N4) are connected to
form another node X (XB) in the ST-10T cell. For these two
cells, all their Px (x = 1 ~ 2 in the 6 T and x = 1 ~ 4 in the ST-
10T) transistors have the same sizes, and so do their Nx
transistors.
2.1 SEUs resilience analysis
As described above, compared to the 6T cell, two more nodes
X and XB are introduced inside the ST-10T. Because the
structure of the ST-10T is symmetrical, we only go into the
SEUs resilience analysis for its logic-0 state (Q = 0 and
QB = 1). First, we analyze the scenario that node X is affected
by an SEU. When Q = 0, X also stays at a low level, which
makes the drain of P3 reverse-biased and sensitive to SEUs.
At this moment, if sufficient charge generated by a single-
event is deposited at P3’s drain, a positive voltage pulse would
appear at X and then propagate to Q through N1. In this case,
the on-state N1 will act as a resistor to help resist this fault
propagation. In fact, by further observing the ST-10T cell in
Fig. 1b, we can see that P1, P2, N1, and N2 can all act as
resistors to suppress fault propagation in the cross-coupled
inverters formed by P3, P4, N3, and N4, which is similar to
the resistive hardening design presented in [18]. However,
different from simple resistors, using transistors in the ST-
10 T can provide additional benefits. As analyzed above, the
incorrect positive pulse at X should propagate to Q to activate
the upset of the ST-10T. Because N1 is not good at transferring
a high level, the amplitude of the pulse at Q can be reduced,
which further helps mitigate this fault propagation. Similarly,
a single-event induced pulse at N4’s drain can also be attenu-
ated by P2 as it propagates to QB.
Second, we consider the upset occurred at Q of the ST-10T
cell, and critical charge modeled in equation (1) is used to
analyze the SEU sensitivity of this node [6, 13]. In (1), Cnode
is the capacitance of the struck node (Q in this case), which
includes the gate and diffusion capacitances; VDD is the supply
voltage; IDP is the maximum restoring current provided by the
on-state devices (N1 and N3), which is also their saturated
currents; and TFLIP is the flipping time, which is proportional
to the propagation delay of an inverter inside the inverter-loop

Table 1 LET threshold of each node of the 6T and ST-10T

SRAM Cell Node LET threshold

(MeV-cm2/mg)

6T Q 1.33
QB 0.55
ST-10T Q 2.03
QB 0.86
X 4.69
XB 2.34
Fig. 3 Write times of the 6T and ST-10T cells at varied supply voltages

Fig. 4 Leakage power of the 6T and ST-10T cells at varied supply
voltages
[6]. Compared to the 6T cell, because the gates of two PMOSs
and two NMOSs are connected to Q, the value of the first term
in (1) should also be increased by two times for the ST-10T
cell. Because of the stacking of N1 and N3 in the ST-10T, the
IDP provided by them should be half of that provided by N1 in
the 6T cell ideally. As shown in (1), this weakened IDP would
lower the value of the second term for the ST-10T. However,
for the inverter formed by P2, P4, N2, and N4 in the ST-10T,
the equivalent resistances of the pull-up and pull-down net-
works are both doubled compared to the inverters in the 6T
cell. Furthermore, the capacitance load at QB is also doubled,
which approximately leads to a 4 times longer delay of the
stacking inverters in the ST-10T compared to the normal in-
verters in the 6T. Since the error at Q should propagate to QB
to cause an upset of the ST-10T cell, the 4-times enlarged
Fig. 5 Read (a) and write (b)
SNMs of the 6T and ST-10T at
varied supply voltages
J Electron Test
delay of the stacking inverter would consequently enlarge
the TFLIP of the ST-10T and help compensate the negative
effect induced by the weakened IDP.
Qcrit ¼ C node V DD þ I DP T FLIP ð1Þ
The above analysis is verified through simulations by using
Accuro, a software package from Robust Chip Inc. [8, 10, 12,
17]. This tool reads in the schematic and layout of a design,
and then carries out 3D device-level simulation to calculate
the single-event charge transport in substrate/well and predict
design’s behavior through circuit-level simulation. Accuro
provides high-speed SEUs analysis and allows SEUs injec-
tions at user-specified locations with user-specified LET
values [12]. The schematics and layouts of the 6T and ST-
10T cells are designed in TSMC 65 nm CMOS bulk technol-
ogy, and their 3D device structures generated in Accuro are
depicted in Fig. 2 (active areas, substrate, and n-well includ-
ed). Electron concentration of substrate and n-well is color
coded and indexed logarithmically. Dimensions in X, Y, and
Z directions are also shown (in microns). To study the SEUs
sensitivity of each node of these two designs, incident parti-
cles are directly injected to each sensitive drain area when
logic-0 states are maintained by them. The simulated LET
thresholds of corresponding nodes are listed in Table 1.
As listed in Table 1, X and XB in the ST-10T obviously
present higher LET thresholds than other nodes. This indicates
that the four transistors (P1-P2 and N1-N2) used as resistors
inside the ST-10T can significantly enhance the SEUs resil-
ience of these two nodes. Q and QB in the ST-10T also have
higher LET thresholds than the corresponding nodes in the 6T.
Although the stacked transistors lead to lowered restoring cur-
rents at these nodes in the ST-10T, the doubled capacitance
loads of these nodes and 4-times enlarged inverters delay
eventually result in their lower SEUs sensitivities. In
Table 1, the nodes staying at low levels have higher LET
thresholds than the corresponding nodes staying at high levels
(for example, in the ST-10T cell, X has a higher LET
J Electron Test

threshold than XB). This is because that these low level nodes
are driven by NMOSs which can provide larger restoring cur-
rents than PMOSs. The simulation results listed in Table 1 are
reasonably fit to the analysis presented above.
2.2 Speed, power, area, and SNM analysis
As analyzed above, in the ST-10T cell, the driving strength of
inverters formed by stacked transistor are weakened. To guar-
antee reliable operation, the access transistors (A1 and A2) in
this cell are also scaled to be smaller. Given that the nodal
capacitances of Q and QB are enlarged meanwhile, the write
operation of the ST-10T cell would be slowed. To explore this
phenomenon, post-layout simulations in Cadence Spectre of
the 6T and ST-10T cells are carried out at 1.0 V, 0.8 V, and
0.6 V supply voltages to calculate their write times. The sim-
ulation results are depicted in Fig. 3.
The simulated static leakage power of the 6T and ST-10T
cells from Spectre are illustrated in Fig. 4. In this figure, the
ST-10T cell consumes 1.66, 1.60, and 1.51 times more leakage
power than the 6T cell at 1.0 V, 0.8 V, and 0.6 V voltages,
respectively. As shown in Fig. 1b, transistors P1, P2, N1, and
N2 in the ST-10T cell always have zero drain-to-source volt-
age differences. Therefore, these four devices would not con-
tribute channel leakage power. For the ST-10T cell staying in
the logic-0 (Q = 0 and QB = 1), since all Px (x = 1 ~ 4) and Nx
(x = 1 ~ 4) are of the same sizes as the corresponding transis-
tors in the 6T cell, the channel leakage currents of P3 and N4
should be the same as those of P1 and N2 in the 6T. As
analyzed before, the access transistors A1 and A2 of the ST-
10T are also scaled to be smaller, which would reduce the

Fig. 6 Block diagram (a) and Column Decoder

micrograph (b) of the SRAM test
chip [9] Cell Array
2048 bits×
TMR

Address
8 pages

CK

Page-7 (ST-10T)
Row Decoder

Page-0 (6T)

Page-1

Page-2

Page-3

Page-4

Page-5

Page-6
TMR

Data_in

CK

Write
Driver

MUX

Data_out

b
 J Electron Test

Fig. 7 Test system [9]

leakages associated with them. Hence, all these factors men-
tioned above would help limit and lower the leakage power of
the ST-10T cell compared to the 6T. However, as shown in
Fig. 4, the ST-10T still presents higher leakage power than the
6T, and the main reason of this phenomenon should be the
gate leakages associated with the stacked transistors. For Q
and QB in the ST-10T cell, since two more transistor gates are
driven by them, the gate leakages at these two nodes should
also increase, which finally enlarge the overall leakage power
of the ST-10T cell.
Compared to the 6T cell, four more transistors are used in
the ST-10T. However, through sharing drain areas between
adjacent transistors (for example, P1 and P3 share a common
drain area in the n-well, as shown in Fig. 1d), the total area of
the ST-10T is 3.39μm2 which is only 1.37 times larger than
that of the 6T.
As discussed above, the stacked transistors weaken the
driving strength of the inverters inside the ST-10T cell. To
obtain similar write and read static noise margins (SNMs) as
the 6T cell, the width-to-length (W/L) ratios of the access
transistors A1 and A2 of the ST-10T are also reduced by half.
However, as shown in Fig. 5, the ST-10T cell presents lower
read SNMs and higher write SNMs than the 6T. This phe-
nomenon should be due to the carrier velocity saturation of
this 65 nm technology. In fact, the channel lengths of A1 and
A2 in the ST-10T are 1.2 times longer than the access transis-
tors in the 6T. Although their W/L ratios are reduced by half,
the longer channel lengths help improve their driving capabil-
ities through eliminating the velocity saturation [19].
Considering the ST-10T cell staying at logic-0, for the on-
state stacked PMOSs (P4 and P2), their velocity saturation
effects are naturally much less significant than that in the
NMOS A2 [19], which eases the write operation and leads
to the higher write SNMs. For the on-state stacked NMOSs
(N1 and N3), since their drain-to-source voltage differences
are slight in the read phase, velocity saturation does not affect
their overall driving strength much [19], which is undesirable
for reliable read operation because A1 is relatively stronger
now. On the other hand, also due to the different significances
of velocity saturations in PMOSs and NMOSs, the switch
threshold of the inverters with stacked transistors inside the
ST-10T is lowered. This effect along with the velocity

Table 2 Experimental results of

alpha particle radiation SRAM cell Supply voltage Pattern # of unit # of errors
process (T) (Nerror)

6T 1.0 V all-1 9000 1773

ST-10T 1.0 V all-1 9000 938
6T 0.8 V all-1 4096 1060
ST-10T 0.8 V all-1 4096 704
6T 0.6 V all-1 4096 1167
ST-10T 0.6 V all-1 4096 951
J Electron Test

Fig. 8 Alpha SERs of the 6T and ST-10T at varied supply voltages

saturation effects on the access transistors makes the ST-10T
more sensitive to noises in the read phase and consequently
results in its lower read SNMs. However, as a secondary ef-
fect, the impact of velocity saturation on SNM is actually not
that significant. As shown in Fig. 5, there are only −9.54 %
read and 9.51 % write SNM differences between these two
cells at 0.6 V, and these differences are even more negligible at
higher supply voltages. This indicates that transistor scaling is
still the main factor that affects SNMs.
3 Implementation and SERs characterization
The 6T and ST-10T cells are both implemented in an SRAM
test vehicle fabricated in TSMC 65 nm technology [9].
Besides these two designs, this test chip also includes other
six types of SRAM cells for SEUs resilience evaluation. For
each SRAM design, 2k cells are organized as an array page.
The 6T and ST-10T cell arrays are indexed as page-0 and
page-7, respectively. For each cell array, every eight bits are
organized as one word to be accessed through a specific ad-
dress. Peripheral circuits (flip-flops, row/column decoders,
etc.) are shared among all these arrays. Flip-flops used to
sample input address and data are all hardened against SEUs
through triple-modular-redundancy (TMR). The block
Fig. 9 Proton SERs of the 6T and ST-10T at varied supply voltages
diagram and micrograph taken by a laser imaging system of
the test chip are illustrated in Fig. 6 [9]. For this test chip, the
supply voltage of the core SRAM circuits is adjustable (nom-
inal 1.0 V and lower values), while the voltage of the IO
modules is fixed to 2.5 V. The area of this test chip is
1.5 mm × 0.7 mm [9].
A Xilinx Virtex-5 field programmable gate array (FPGA)
based system is developed for the functional test and radiation
experiments of this SRAM test chip [9]. The test chip is em-
bedded on a daughterboard and connected to motherboard on
which the FPGA is located. This FPGA core is responsible for
operating the SRAM test chip and the communication be-
tween the test chip and a micro-processor unit (MCU). The
data read out by the FPGA is then sent to a personal computer
for analysis through the Ethernet module under MCU’s con-
trol. An off-chip configurable power is applied to provide
different supply voltages for the SRAM core circuits. The test
system is shown in Fig. 7 [9].
3.1 Alpha radiation results
Alpha radiation experiments were carried out at the University
of Saskatchewan, Saskatoon, Canada, and an Americium-241
alpha source with 2.5 uCi activity and 4.61 × 107 a/cm2/h

Table 3 Experimental results of

proton radiation SRAM cell Supply voltage Pattern # of unit # of errors
process (T) (Nerror)

6T 1.0 V Checkerboard 5696 420

ST-10T 1.0 V Checkerboard 5696 213
6T 0.8 V Checkerboard 2600 233
ST-10T 0.8 V Checkerboard 2600 145

emissivity was applied. During this test, all-1 data was peri-
odically written into each cell array and then readout after a
period of radiation. Each unit process formed by a write oper-
ation, radiation, and a readout operation lasted for 1 s, and the
radiation time occupied over 99 % of this unit process period.
Such a unit process was repeated 9000 times at 1.0 Vand 4096
times at 0.8 V/0.6 V for each cell array. The readout data was
recorded and compared to the written data to identify upset
errors. The SERs of the 6T and ST-10T arrays with different
voltages are calculated as (2). Here, Nerror is the total amount
of errors, CA is the capacitance of each cell array (2k-bit), and
T is the repeat times mentioned above. Alpha test configura-
tions and results are listed in Table 2. The SERs calculation
results are illustrated in Fig. 8.
N error
SER ¼  100% ð2Þ
CA  T
As shown in Table 2 and Fig. 8, at 1.0 V, 0.8 V, and 0.6 V
supply voltages, SER of the ST-10T decreases by 47.1 %,
33.6 %, and 18.5 % compared to the 6T. The SERs of both
the ST-10T and 6T cells increase as the supply voltage de-
creases, and this phenomenon should be mainly due to the
reduction of critical charge.
3.2 Proton radiation results
The proton radiation experiments were carried out at
TRIUMF (Tri-University Meson Facility), Vancouver,
British Columbia, Canada. Protons were incident normally,
and their average energy is 63 MeV. The test process is the
same as that of the alpha test, except that checkerboard (1010)
pattern data is used in this experiment. For the 6T and ST-10T
arrays, 5696 and 2600 times of unit process tests were applied
for them at 1.0 V and 0.8 V supply voltages, respectively.
Proton test configurations and results are listed in Table 3.
Their SERs calculated according to (2) are illustrated in Fig. 9.
As shown in Table 3 and Fig. 9, 49.3 % and 37.8 % SER
reduction are achieved by the ST-10T at 1.0 V and 0.8 V
supply voltages, respectively. Similar to the alpha radiation
results, the decrease of supply voltage also leads to the SER
degradations of both designs.
4 Conclusion
An area efficient 10-transistor SRAM cell (named ST-10T)
tolerant to SEUs is proposed in this paper. Compared to the
conventional 6T cell, the ST-10 T can achieve higher critical
charge at each internal node, which consequently improves its
SEUs resilience. Simulations in Accuro show that each node
inside the ST-10T has higher LET threshold than the
J Electron Test
corresponding node in the 6T cell. Alpha and proton radiation
experiments were also carried out for both designs and the
superior SEUs resilience of the proposed ST-10T cell is ex-
perimentally verified. Comparisons and analysis of some tra-
ditional features in terms of write speed, leakage power, area,
and SNMs are also provided.
Acknowledgments The authors appreciate the supports from the
Natural Sciences and Engineering Research Council of Canada
(NSERC), CMC Microsystems, ASPIRE (CREATE program), and
Robust Chip Inc.
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Yuanqing Li received the B.E., M.E., and Ph.D. degrees in 2008, 2010,
and 2014 from Tianjin University, Tianjin, China. He is now a post-
doctoral fellow with the Department of Electrical and Computer
Engineering, University of Saskatchewan. His research interests include
the radiation effects on microelectronic devices and circuits, radiation
hardening techniques, and VLSI design.
Lixiang Li received the B.E. degree from Guangdong University of
Technology, Guangzhou, China, and MASc. degree from Dalhousie
University, Halifax, Nova Scotia, Canada. He is now with the
TSMC Design Technology Canada, Kanata, Canada. His research
interests include VLSI systems and mixed signal integrated circuits
design.
Yuan Ma received the B.Sc. and M.Eng. degrees from Southeast
University, China, in 1991 and 1994, respectively, and the M.Sc. and
Ph.D. degrees in electrical and computer engineering from the
University of Alberta, Edmonton, AB, Canada, in 1997 and 2002, respec-
tively. From November 2000 to June 2006, she worked as a Research
Scientist in the Exploratory Research group of JDS Uniphase, Ottawa,
ON, Canada. In July 2006, she joined the Electrical and Computer
Engineering Department, Dalhousie University, Halifax, NS, Canada, as
a University Faculty Award recipient. Her research interests include
micro-sensors and actuators, mechatronic system design and analysis,
photonics, and MEMS device industrial applications.
Li Chen is currently an Associate Professor of the Department of
Electrical and Computer Engineering, University of Saskatchewan. He
received his Ph.D. degree from the University of Alberta in 2004. His
current research is focused on radiation-tolerant microelectronic circuit
design and testing, advanced technology reliability testing like 130 nm
3D-IC and 28 nm IC, and single event testing methodology like pulsed
laser and X-ray.
Rui Liu is a Ph.D. candidate majoring in electrical engineering in the
University of Saskatchewan.
Haibin Wang received his Ph.D. degree from the University of
Saskatchewan in 2015. He received his Bachelor and Master degrees
from Hohai University. His research interests include radiation effects,
fault-tolerant IC design, reliability engineering, and embedded system
design. He has worked on single event hardened flip-flop and logic design
and testing in 28 nm bulk/SOI and 130 nm technologies.
Qiong Wu received her M.Sc. degree in 2015 from the Department of
Electrical and Computer Engineering, University of Saskatchewan. She
received her B.E. and M.E. degrees in Communication and Information
Engineering in 2006 and 2008 from Tianjin University. Her research
interests focus on the area of VLSI and digital circuits design.
Michael Newton received his B.Sc. degree in Physics from the
University of Saskatchewan, where he is now working toward an M.Sc.
degree in Electrical Engineering. His research interests include solid state
and nuclear physics, quantum mechanics, and single event effects on
semiconductor devices. His current research mainly focuses on the appli-
cation of lasers in single event effects tests for integrated circuits and
photonic devices.
Mo Chen received the B.E. degree from Beijing Institute of Technology
and now is working toward the Master degree in the University of
Saskatchewan. Her research interest focuses on the design of fault-
tolerant SRAM.