COMPUTER ENGINEERING DEPARTMENT

Logic Circuits and Design

ACTIVITY 3: LOGIC GATE INTERCONNECTION

3.1 Program Outcomes (POs) Addressed by the Activity

a. Apply knowledge of computing, science, and mathematics appropriate to the
discipline.
b. Understand best practices and standards and their applications.
c. Analyse complex problems and identify and define the computing requirements
appropriate to its solution.

3.2 Activity’s Intended Learning Outcomes (AILOs)

At the end of this activity, the student shall be able to:
a. To interconnect a basic logic gate IC with other basic logic gates.
b. To experimentally verify the output signal of the resulting circuit.
c. To compare the certain gate combinations with existing basic gates.

3.3 Objectives of the Activity

The objectives of this activity are to:
a. To construct combinational logic circuits
b. To derive the truth table based on the given logic circuit

3.4 Principle of the Activity

Combining or interconnecting logic gates forms a logic circuit.. a logic circuit is an
electronic circuit that processes information by performing logical operations on it. In logic
circuits, there are only two possible levels for the input and output signals: HIGH and LOW,
numerically represented by the binary digits 1 and 0, respectively.

The output signal, using binary notation, is controlled by the logic circuit in accordance
with the input system. The basic logic gates are the AND, the OR, and the INVERTER (NOT).
The AND circuit yields a binary 1 output only if a binary 1 is present on each of the input
terminals, otherwise the output is a binary 0. The OR circuit yields a binary 1 output if a binary
1 is present on at least one of the input terminals. The NOT logic gate yields the
complement/inverse of the input signal, i.e., producing binary 1 output for a binary 0 input, and
vise versa. Often, certain combinations of logic gates are commonly used, e.g., a NAND circuit
consists of NOT + AND logic gates, and a NOR for NOT + OR.

ACTIVITY 3: LOGIC GATE INTERCONNECTION 1

3.5 Materials/Equipment

Integrated Circuits (ICs)

1 Logic Probe 1 74LS00
1 Fixed Power Supply 1 74LS02
1 Protoboard 1 74LS04
1 Long Nose Pliers 1 74LS08
1
Wire Stripper Pliers 1 74LS32
Connecting Wires 1 74LS86

3.6 Circuit Diagrams

ACTIVITY 3: LOGIC GATE INTERCONNECTION 2

 14 13 12 11 10 9 8 14 13 12 11 10 9 8
Vcc Vcc

GND GND
1 2 3 4 5 6 7 1 2 3 4 5 6 7

Figure 2. Basic Gates Pin Configuration

ACTIVITY 3: LOGIC GATE INTERCONNECTION 3

3.7 Procedure

1. Connect the circuit shown in Figure 1-A . Supply the circuit with +5V and ground.
2. Derive the truth table of the circuit by inputting the values indicated in the DATA AND
RESULTS Table 1-A for Figure 1-A and record the result.
3. Repeat Step 2 for the Figures 1-B, 1-C, 1-D, 1-E and 1-F.

3.8 Activity Report

Section: TE21 Date Performed: 05/12/22
Course Code: CPE0021L Date Submitted:
Course Title: Logic Circuits and Design
Instructor: Ma’am Maribel Misola
Group No.: Activity No.:

Group Members: Signature:

1. Francisco, Elly Roi Dominic F.
2.
3.
4.
5.

3.8.1 Data and Results

A X
A NAND gate with
input terminals 0 1
Table 1-A
shortcircuited. 1 0
A X
A NOR gate with
input terminals 0 1
Table 1-B
shortcircuited. 1 0

ACTIVITY 3: LOGIC GATE INTERCONNECTION 4

 A B X

An AND gate with 0 0 1

input terminals
0 1 0
inverted (Bubbled
Table 1-C 1 0 0
AND).
1 1 0
A B X
0 0 1
Ad OR gate with input
terminals inverted 0 1 1
Table 1-D (Bubbled OR). 1 0 1
1 1 0
A B X
0 0 0
A combination of
INVERTER, AND, 0 1 1
Table 1-E and OR gates. 1 0 1
1 1 0
A B X
0 0 1
A combination of
INVERTER, AND, 0 1 0
Table 1-F and OR gates. 1 0 0
1 1 1

ACTIVITY 3: LOGIC GATE INTERCONNECTION 5

 Table 1-A:

Link: https://www.tinkercad.com/things/ciKM6EbWJa6-shiny-bruticus-
turing/editel?sharecode=iK08GX5kLZA_cFf18otjXsYIZe3OoIYX9H0KshI4xkw

Table 1-B:

Link: https://www.tinkercad.com/things/dKtNM6z8Bs4-swanky-
amberis/editel?sharecode=sVCFY4aOmoR9yVsJM_mTxFLrSOZbT4a0sVJWPLhfT1s

ACTIVITY 3: LOGIC GATE INTERCONNECTION 6

 Table 1-C:

Link: https://www.tinkercad.com/things/cc4IIXhaxrf-fantastic-
jaagub/editel?sharecode=QgwZolDWowmDy8OiYBl2bfZWxhxngiDsA6JdE2dAfSM

Table 1-D:

Link: https://www.tinkercad.com/things/aaFd7nNSmsS-fantabulous-
kasi/editel?sharecode=RObqzmczhC7Xcv8Og6T-tmAjSX8SUaI9grR9BfZxJ4A

ACTIVITY 3: LOGIC GATE INTERCONNECTION 7

 Table 1-E:

Link: https://www.tinkercad.com/things/3QwUvsQpOIs-tremendous-rottis-
tumelo/editel?sharecode=6-FuIY7ubGAPlFEpHAIVzr01AeqherGyteC8Ypab9Z0

Table 1-F:

Link: https://www.tinkercad.com/things/jN5bQdj6xkI-fantastic-fulffy-
waasa/editel?sharecode=TQc0OAf1f_b42aBTV_hQOT4n6KWCvxOvQuJ144WjxHY

ACTIVITY 3: LOGIC GATE INTERCONNECTION 8

 3.8.2 Solutions

3.8.3 Observations

3.8.4 Conclusions

When looking at a logic circuit diagram, we can see that logic gates are operated in a
specified order. When we employ numerous logic gates, we can see how a circuit diagram
becomes more intricate. Logic gates typically have two inputs and one output. And the
decision of logic gates is based on a combination of digital signals from their inputs.

ACTIVITY 3: LOGIC GATE INTERCONNECTION 9

 3.8.5 Rating

Member Member Member Member Member

Criteria
1 2 3 4 5

Activity Conduct (1-5)

Equipment
Operation and (1-5)
Material Handling

Data Collection (1-5)

Data Analysis and

(1-5)
Evaluation

Results
(1-5)
Interpretation

Total Score

Mean Score = (Total

Score/5)

Percentage Score = (Total

Score/5)*100%

ACTIVITY 3: LOGIC GATE INTERCONNECTION 10

 Other Comments/Observations:

ACTIVITY 3: LOGIC GATE INTERCONNECTION 11