SYSTEM VERILOG | Notes by Bhuvanesh Arulraj

CONSTRAINT RANDOM VERIFICATION:

Keywords to be known:

RAND VS RANDC

rand: will create random variable like dice cannot be predicted

randc: will create cyclic random variable, meaning it will not repeat a random value until every possible
value has been assigned.

For random variables:

OUTPUT:

The above is the example of creating a random variable.

Steps:

1. Use rand or randc in the Packet class.

2. Use class_handler.randomize() inside the module.
3. Randomization will be initiated.

Now Let’s imagine that we don’t need everything to be random, in the above example we can observe
that Max is not going to come as max all the time, so how to set limits or conditions to those.

How to set conditions and limits?

Soln: Constraints

Let’s discuss about that. Below are some useful examples and constraint types.
 SYSTEM VERILOG | Notes by Bhuvanesh Arulraj

Constraint min_max problem:

If we use <, >, <=, >=, ==, only once such operators should be used in an expression. If we use multiple
operators in same constraint, it won’t give the desired result. Check the below code. (EDA-
https://www.edaplayground.com/x/Ycf9 )

Output:

In the above example, we want to minimum should be less than middle, and middle less than max.
However, if we write altogether in one statement it results in a wrong constraint.
 SYSTEM VERILOG | Notes by Bhuvanesh Arulraj

Weighted Distribution:

WHAT? The dist operator takes a list of values and weights, separated by := or :/ operator. The values
can be constant or variable or list of values. The weights are not percentage and won’t sum up to 100%.
It’s more like probability, which is mentioned in the code below.

WHY we need? When reviewing functional coverage results, if corner cases has not been covered, then
for covering stimulus more in a particular direction and finding bugs.

HOW? By using “dist” keyword weighted distribution can be made.

Let say we have some data which need to be

: = weight is same for every specified value in the range.

:/ weight is to be equally divided between all the values.

Output:
 SYSTEM VERILOG | Notes by Bhuvanesh Arulraj

INSIDE OPERATOR:

Inside operator defines that the variable is within that specified limit. We can inverse that too.
See the examples below.

OUTPUT:

Implication operator:

The implication operator is useful for expressing conditional relationships between two variables. The
symbol -> represents the implication operator. The implication operator is used to connect the
expression and the constraint.

Implications are useful in defining modes, FSM, etc. The below is one such example.

In class implications, if io==1 then addr will be either of those corresponding values.
 SYSTEM VERILOG | Notes by Bhuvanesh Arulraj

IMPLICATION CODE:

OUTPUT:

Here you can observe that we can control over the modes by using constraints. We can also use if else
in constraints. Those are shown below in the example below.

IF ELSE CONSTRAINT:

if else constraints can be executed conditionally using the if else block. If the expression is true, all the
constraints in the first constraint/constraint-block must be met; otherwise, all of the constraints in the
optional else constraint/constraint-block must be met.
 SYSTEM VERILOG | Notes by Bhuvanesh Arulraj

OUTPUT:

Here in the above code, we are setting if the required mode is set the gpio will pass the data, else 0.

SWITCH OFF CONSTRAINTS:

The constraints sometimes needed to turn off inorder to cover some particular case scenario.
So, for that how to turn off? Let’s see.

For turning off we need to use - constraint_mode(0) if we use (1) it’s on. However, that’s not needed.
 SYSTEM VERILOG | Notes by Bhuvanesh Arulraj

OUTPUT:

In the above example, we have two constraints, one for long and another as short, We turned off the
long thus all the randomized value falls within the short range.

For practicing:

EDA PLAYGROUND: https://www.edaplayground.com/x/hKWJ