UNIT – I

Introduction to Embedded System Design

 Embedded System: Definition
 Classification
 Characteristics
 Design challenges
 Design flows

Introduction to ARM7TDMI Core

 RISC and ARM design philosophy
 ARM7TDMI core architecture
 ARM state register set & THUMB state register set
 Pipeline
 Exceptions
 Embedded C programming with
09/18/2022 An Intro
ARM
3
 UNIT – II
ARM based Microcontroller (LPC2148)
 Architectural Overview & Block diagram
 Memory map
 On-chip Peripherals
 GPIO
 Timer
 PWM
 Real Time Clock (RTC)
 USART
 Vectored Interrupt Controller (VIC)
 Embedded C programming with on-chip peripherals

09/18/2022 An Intro 4
 UNIT – III
DSP Processor Architectures
 Fixed Point Vs Floating Point digital signal processors
 VLIW Architecture of TMS320C6713 floating point
processor
 Key features
 C6713 DSK functional diagram
 basic operations
 memory mapping
 L2 memory architecture
 DSP Interfacing CODEC (AIC23)
 Software development and debugging using Code
Composer Studio (CCS)
09/18/2022 An Intro 5
 UNIT – IV
Implementation of DSP Algorithms on Floating Point
Digital Signal Processor
 FIR filtering
 IIR filtering (Direct Form I, Direct Form II)
 DIF FFT implementation
 Wiener filtering
 Least Mean Square adaptive algorithm
 Recursive Least Square adaptive algorithm
 Discrete Kalman Filtering algorithm

09/18/2022 An Intro 6
 TEXTBOOKS
TEXTBOOKS
1. Marilyn Wolf, Computer as Components: Principles of
Embedded Computing System Design, 4th Edition, Elsevier,
2017.
2. Emmanuel C. Ifeachor and Barrie W. Jervis. Digital Signal
Processing: A Practical Approach, 2nd Edition, Pearson
Education, 2012.
3. Andrew N. Sloss, Dominic Symes, Chris Wright. ARM System
Developer’s Guide: Designing and Optimizing System Software,
Elsevier, 2004.

09/18/2022 An Intro 7
 REFERENCES
REFERENCES
1. Simon Haykin. Adaptive filter theory, 4th Edition, Pearson
Education, 2013.
2. User Manual LPC2148:
https://www.scribd.com/doc/210433900/User-Manual-
LPC2148
3. User manual TMS320C67XX Texas instruments
https://www.ti.com/lit/ds/symlink/tms320c6713b.pdf
4. Technical Reference manual TMS320C6713 DSK, Texas
Instruments:
http://c6000.spectrumdigital.com/dsk6713/revc/files/
6713_dsk_techref.pdf
5. TMS320C6000 Code Composer Studio Tutorial
http://www.ti.com/lit/ug/spru301c/spru301c.pdf
09/18/2022 An Intro 8
 Introduction to
Embedded System Design
Unit – I

Courtesy: Frank Vahid and Tony Giv – “Embedded

System Design: A Unified Hardware/Software
Approach”, 3rd Edition, John Wiley & Sons, 2009.
 System Vs Embedded System
• System is a way of working, organizing or doing one or
multiple tasks according to a fixed plan, program or set of
rules
• System is also an arrangement in which all its units
assemble and work together according to a plan or
program
Embedded computing systems have to provide
sophisticated functionality:
• Real time: operations be completed by deadlines
• Multirate: operations that run at different rates (Eg:
audio & video)
• To satisfy cost, power & energy requirements
 Embedded System Definitions
➢ Computing systems embedded within electronic devices
➢ An embedded system is nearly any computing system other
than a desktop computer.
➢ An embedded system is the one that has computer hardware
with software embedded in it as one of its most important
component.
➢ It is any device that includes a programmable computer but is
not itself intended to be a general purpose computer.
➢ Embedded systems are hard to define because they cover
such a broad range of electronic devices.
➢ An embedded system is a combination of
computer hardware and software designed for a
specific function.
Classifications of Embedded System
Small scale Embedded System
• Single 8-bit/16-bit microcontroller
• Mostly battery operated
• Uses IDE with C language
• Software to fit within available memory
• S/W complexity & board level design
Ex: Calculator, Automatic door lock,
Medium scale embedded system
• Single or few 16-bit/32-bit microcontroller, DSPs
• Also uses readily available SPPs and IPs
• Both H/W & S/W complexities
• Uses IDE, RTOS, C/C++/JAVA
Ex: Digital camera, Washing machine, Oven
Classifications of Embedded System
Sophisticated Embedded System
• Need several IPs, ASIPs, PLAs
• Enormous H/W & S/W complexities
• Used for cutting edge application that need hardware &
software co-design
• Uses hardware for encryption, DCT, Network driver, etc…
• Development tools may not be readily available
Ex: ATM, ABS, Navigation control
 Embedded Systems

https://www.indiamart.com/proddetail/embedded-system-software-
6585748473.html
 Characteristics of Embedded Systems
• Single-functioned
– Executes a single program, repeatedly
• Tightly-constrained
– Low cost, low power, small, fast, etc.
• Reactive and real-time
– Continually reacts to changes in the system’s
environment
– Must compute certain results in real-time without
delay
 Design Challenges –
Optimizing Design Metrics
• Obvious design goal:
– Construct an implementation with desired
functionality
• Key design challenge:
– Simultaneously optimize numerous design metrics
• Design metric
– A measurable feature of a system’s implementation
– Optimizing design metrics is a key challenge
 Design Metrics
➢ Unit cost: the monetary cost of manufacturing each
copy of the system, excluding NRE cost

➢ NRE cost (Non-Recurring Engineering cost): The one-

time monetary cost of designing the system
total cost = NRE cost + unit cost * No. of of units
per-product cost = total cost / No. of units
= (NRE cost / # of units) + unit cost
➢ Size: the physical space required by the system

➢ Power: the amount of power consumed by the system

 PROBLEM 1
• Suppose a smart phone per unit cost is RS.
10,000 and NRE cost is RS. 2000000, if total of
1000 units fabricated then calculate the per
product cost of the device.

(ANS:12000)
 Design metrics (continued)
➢Performance: the execution time or throughput of the
system

➢Flexibility: the ability to change the functionality of

the system without incurring heavy NRE cost

➢Time-to-prototype: the time needed to build a

working version of the system

➢Time-to-market: the time required to develop a

system to the point that it can be released and sold to
customers
 Design metrics (continued)
➢ Maintainability: the ability to modify the system after its
initial release

➢ Correctness: to implement the system’s functionality

correctly. Insert test circuitry to check that
manufacturing was correct.

➢ Safety: the probability that the system will not cause

harm.
 Design Metric Competition
• Expertise with both software
and hardware is needed to
Power optimize design metrics
➢Not just a hardware or
Performance Size
software expert, as is
common
➢A designer must be
NRE cost comfortable with various
technologies in order to
choose the best for a given
application and constraints
 Time-to-market
• Time required to develop
a product to the point it
can be sold to customers
• Market window
➢Period during which
Revenues ($)

the product would

have highest sales
Time (months)
• Delays can be costly
 Losses due to delayed market entry
• Simplified revenue model
Peak revenue
➢Product life = 2W, peak at W
Peak revenue from
➢Time of market entry defines
On-time
delayed entry
a triangle, representing
Revenues ($)

Market rise Market fall market penetration

Delayed ➢Triangle area equals revenue
• Loss
D W 2W ➢The difference between the
On-time
entry
Delayed
entry
Time
on-time and delayed triangle
areas
 Losses due to delayed market entry
Area = 1/2 * base * height
On-time = 1/2 * 2W * W
Peak revenue
Delayed = 1/2 * (W-D+W)*(W-D)
Peak revenue from
delayed entry
Revenues ($)

On-time

Market rise Market fall

Percentage revenue loss =
Delayed
(D(3W-D)/2W2)*100%

D W 2W
On-time Delayed Time
entry entry
 PROBLEM 2
• Consider a lifetime of the product is 52 weeks,
if the product is released with delay of 4
weeks, then the approximate percentage
revenue loss will be _____%.

ANS(22%)
 Performance Design Metric
• Widely-used measure of system, widely-abused

– Clock frequency, instructions per second – not good

measures

– Digital camera example – a user cares about how fast it

processes images, not clock speed or instructions per
second

• Latency (response time)

– Time between task start and end

– e.g., Camera’s A and B process images in 0.25 seconds

 Performance design metric
• Throughput

– Tasks per second, e.g. Camera A processes 4 images

per second

– can be more than latency due to concurrency,

e.g. Camera B may process 8 images per second (by

capturing a new image while previous image is being
stored).

• Speedup of B over S = B’s performance / A’s performance

– Throughput speedup = 8/4 = 2

 Challenges in
Embedded Computing System Design
How much hardware do we need?
• Too little hardware and the system fails to meet its
deadlines
• Too much hardware and it becomes too expensive

How do we meet deadlines?

• Increasing the CPU clock rate may not make enough
difference to execution time, since program’s speed may
be limited by the memory system
 Challenges (contd…)
How do we minimize power consumption?
• Slow down the noncritical parts of the machine for power
consumption while still meeting necessary performance
goals
How do we design for upgradability?
To add features by changing software. will it
provide the required performance for new software
Does it really work?
• Reliability is especially important in some applications,
such as safety-critical systems.
 Challenges (contd…)
• Complex testing: to run a real machine in order to generate
the proper data. Cannot separate the testing of an
embedded computer from the machine in which it is
embedded
• Limited observability and controllability: We may be forced
to watch the values of electrical signals on the
microprocessor bus.
• Restricted development environments: often much more
limited than those available for PCs and workstations. To
debug the code, we must usually rely on programs that run
on the PC or workstation and then look inside the embedded
system.
Losses due to delayed market entry : Calculation

Area = 1/2 * base * height

On-time = 1/2 * 2W * W=W*W
Delayed = 1/2 * (W-D+W)*(W-D)=(2W-D)*(W-D)/2
Percentage revenue loss=((on-time)-delayed)/(on-time) *100
=(W*W-[2W2-2WD-DW+D2]/2)/W2*100

= (D(3W-D)/2W2)*100%
Design Flows
Unit I
 INTRODUCTION

•Designing an embedded system is not an easy task.

•Most real embedded system designs are inherently complex,
given that their functional specifications are rich
•They must obey multiple other requirements on cost,
performance, and so on.

2
 DESIGN GOALS
The obvious goal of a design process is to create a product that does
something useful.
Typical specifications for a product will include
 functionality (e.g., cell phone),
 manufacturing cost (must have a retail price below $200),
 Performance (must power up within 3 s),
 power consumption (must run for 12 h on two AA batteries), or
 other properties.
A design process has several important goals beyond function,
performance, and power. Three of these goals are summarized below.
■ Time-to-market
-beat competitors to market
■ Design cost
■ Quality 3
 Design Methodology

• Design methodology: a procedure for creating an

implementation from a set of requirements.
• Methodology is important in embedded computing:
– Must design many different systems.
– We may use same/similar components in many
different designs.
– Both design time and results must be predictable.

4
 Design flow

• Design flow: sequence of steps in a design methodology.

• May be partially or fully automated.
– Use tools to transform, verify design.
• Design flow is one component of methodology.
Methodology also includes management organization,
etc.

5
 COMMON DESIGN FLOW MODELS
• Waterfall model

• Spiral model

• Successive refinement

• Hierarchical design flows

• Concurrent engineering

6
 Typical Design Flow
requirements

Top-down
design specification

architecture
Bottom-up
design
Real design component
development
often iterative
system
integration
7
 1. Waterfall model
Introduced by Royce , the first model proposed for the
software development process.

• Early model for software development:

The waterfall model gets its name from the largely one-way
flow of work and information from higher levels of
abstraction to more detailed design steps

8
 Waterfall model
• Requirement analysis
– Determines the basic characteristics of the system
• Architecture design
– Decomposes the functionality into major components
• Coding
– Implements the pieces and integration
• Testing
– Determines the bugs
• Maintenance
– Entails deployment in the field, bug fixes and
upgrades
9
 Problems in Waterfall model
• Real projects rarely follow the sequential flow models
• Difficult for the customers to state all the properties
explicitly
• Customer must have patience
– To overcome these problems an alternative model of
software development called the spiral model
• While the waterfall model assumes that the system is
built once in its entirety, the spiral model assumes that
several versions of the system

10
2.Spiral model

11
 Spiral Model
• Designing the system is more complex progresses in that
each level of design, the designers go through
requirements, construction, and testing phases.
• Finally more complete versions of the system are
constructed, each phase requires more work, widening
the design spiral.
• The first cycles at the top of the spiral are very small and
short, while the final cycles at the spiral’s bottom add
detail learned from the earlier cycles of the spiral.
12
 Spiral Model
Advantage:
• The spiral model is more realistic than the waterfall
model because multiple iterations are often necessary
to add enough detail to complete a design.

Disadvantage:
• However, a spiral methodology with too many spirals
may take too long when design time is a major
requirement.

13
3. Successive refinement model

specify specify

architect architect

design design

build build

test test
initial system refined system
The system is built several times. A first system is used as
a rough prototype, and successive models of the system
are further refined. 14
 Hardware/software design flow
Embedded computing systems often involve the design of
hardware as well as software.
requirements and

specification

architecture

hardware design Software design

integration

testing
15
 Hardware/software design flow

• It consists of three kinds of activities

• Front end activities
– requirements, Specifications and architectures
– Hardware and software aspects
• Back end activities
– Integration and Testing
• Middle activities
– Hardware and software Developments
16
 4. Hierarchical design flow

• Embedded systems must be designed across multiple

levels of abstraction:
– system architecture;
– hardware and software systems;
– hardware and software components.
• Often need design flows within design flows.

17
A hierarchical design flow for an
embedded system.

18
Elements of Concurrent Engineering
Cross-functional teams: include members from various
disciplines involved in the process, including manufacturing,
hardware and software design, marketing, and so forth.

Concurrent product realization: is the heart of concurrent

engineering. Doing several things at once, such as designing
various subsystems simultaneously, is critical to reducing
design time.

Incremental information sharing: as soon as new

information becomes available, it is shared and integrated
into the design. Cross-functional teams are important to the
effective sharing of information in
a timely fashion. 19
Elements of Concurrent Engineering
Integrated project management: ensures that someone is
responsible for the entire project, and that responsibility is
not abdicated once one aspect
of the work is done.

Early and continual supplier involvement: helps make the

best use of suppliers’ capabilities.

■ Early and continual customer focus: helps ensure that the

product best meets customers’ needs.

20
 Course Name:
Embedded & Signal Processing Architectures

Course Code: ECE308

Unit – I
Introduction to ARM7TDMI Core
Courtesy: Andrew N. Sloss, Dominic Symes, Chris Wright.
ARM System Developer’s Guide: Designing and Optimizing
System Software, Elsevier, 2004.

1
 RISC DESIGN PHILOSOPHY
• RISC is a design philosophy aimed at delivering
simple but powerful instructions that execute
within a single cycle at a high clock speed

• RISC philosophy is implemented with four major

design rules

• Instructions—RISC processors have a

reduced number of instruction classes. These
classes provide simple operations that can each
execute in a single cycle

2
 RISC DESIGN PHILOSOPHY
• Pipelines—The processing of instructions is
broken down into smaller units that can be
executed in parallel by pipelines

• Registers—RISC machines have a large

general-purpose register set. Any register can
contain either data or an address

• Load-store architecture—The processor

operates on data held in registers. Separate
load and store instructions transfer data
between the register bank and external memory
3
 ARM DESIGN PHILOSOPHY
• ARM processor has been specifically designed
to be small to reduce power consumption and
extend battery operation

• Single-chip solution, the smaller the area used

by the embedded processor, more available
space for specialized peripherals.

• High code density

• Incorporated hardware debug technology

4
 ARM DESIGN PHILOSOPHY
• ARM core is not a pure RISC architecture because
instruction set differs from the pure RISC

– Variable cycle execution for certain instructions

– Inline barrel shifter leading to more complex

instructions

– Thumb 16-bit instruction set

– Enhanced instructions (DSP Functions)

5
 ARM7TDMI CORE ARCH.

• ARM 7TDMI is a member of ARM family

• General purpose 32 bit microprocessor core

• Reduce instruction set computer

• ARM7 has used Von Neumann, with single 32

bit data bus for both data and instruction

• Load Store Architecture- operations operate on

registers and not in memory locations

6
 TDMI ?
– T: Thumb, 16-bit compressed instruction set
– D: on-chip Debug support, enabling the
processor to halt in response to a debug
request
– M: enhanced Multiplier, yield a full 64-bit
result, high performance
– I: Embedded ICE hardware

7
 ARM7TDMI CORE ARCH.
• Three stage pipeline: fetch, decode and execute
• Support two instruction set
– 32-bit ARM instruction set
– 16-bit Thumb instruction set
• 32-bit ARM plus 16-bit Thumb extension
• Seven processor modes are used to run user
tasks
• 37 total registers divided among seven different
processor modes

8
 ARM7TDMI CORE ARCH.
• Embedded ICE on-chip debug

• Hard Macro cell IP

• Industry leading 0.25 mW/MHz

9
ARM7TDMI core architecture

10
 ARM7TDMI CORE ARCH.
• Register Bank is connected to ALU via two data
paths A bus, B bus

• Program counter generates address for next

function

• Debug extensions used to monitor what is

occurring on the data path of the CPU

11
 ARM7TDMI CORE ARCH.
• In-line decompression process of Thumb
instructions while in the decode stage of the
pipeline

• This process creates a 32-bit ARM equivalent

instruction from the 16-bit Thumb instruction,
decodes the instruction, and passes it on to the
execute stage

• The Embedded ICE logic monitors the ARM

core signals every cycle to check if a
breakpoint or watch point has been hit
REGISTERS

13
REGISTERS

14
 MODES
• The processor enters abort mode when there is a failed attempt
to access memory
• Fast interrupt request and interrupt request modes correspond
to the two interrupt levels available on the ARM processor
• Supervisor mode is the mode that the processor is in after reset
and is generally the mode that an operating system kernel
operates in
• System mode is a special version of user mode that allows full
read-write access to the CPSR
• Undefined mode is used when the processor encounters an
instruction that is undefined or not supported by the
implementation
• User mode is used for programs and applications

15
 ARM STATE REGISTER SET
• The ARM state register set contains 16 directly-
accessible registers, r0 to r15

• Registers r0 to r13 are general-purpose registers

used to hold either data or address values

• Registers r14 and r15 have the following special

functions

• An additional register, the Current Program

Status Register (CPSR), contains condition code
flags, and the current mode bits
16
 ARM state register set (Cont.)

• Link register :Register 14 is used as the subroutine Link

Register (LR).

• R14 receives a copy of r15 when a Branch with Link

(BL) instruction is executed.

• Program counter : Register 15 holds the Program

Counter (PC).

17
Program Status Registers format (Cont.)

• The N, Z, C, and V bits are the condition code flags used

in arithmetic and logical operations.

• Remaining bits of a PSR are control bits such as

Interrupt disable bits ,T bit, Mode bits (M[4:0]determine
the processor operating mode).

• The remaining bits in the PSRs are unused but are

reserved.

18
ARM state register set (Cont.)

19
 Thumb state Register Set
• The Thumb state register set is a subset of the ARM state set.

• The programmer has direct access to:

• Eight general registers, r0–r7
• PC
• Stack Pointer (SP)
• Link Register (LR)
• CPSR.

20
Thumb state register set (Cont.)

21
 Relationship between
ARM state and Thumb state registers

• Thumb state r0–r7, and ARM state r0–r7 are identical

• Thumb state CPSR and SPSRs, and ARM state CPSR and
SPSRs are identical

• Thumb state SP maps onto ARM state r13

• Thumb state LR maps onto ARM state r14

• The Thumb state PC maps onto the ARM state PC (r15).

22
 Mapping of
Thumb state registers onto ARM state registers

23
 Program status registers

• ARM7TDMI-S core contains a CPSR and five SPSRs

for exception handlers

• Hold the condition code flags

• Control the enabling and disabling of interrupts

• Set the processor operating mode.

24
Program Status Registers format

25
 Program Status Registers (Cont.)
• Interrupt disable bits :
• I and F bits are the interrupt disable
• I bit is set, IRQ interrupts are disabled
• F bit is set, FIQ interrupts are disabled.
T bit :
• Reflects the operating state
•T bit is set, the processor is executing in Thumb state
• T bit is clear, the processor executing in ARM state.

26
PSR - Mode bits

27
 Three –stage pipeline
 Three-stage instruction pipeline
 Fetch
instruction is fetched from memory
 Decode
instruction is decoded and the data path control
signals prepared for the next cycle
 EXECUTE
operands are read from the register bank, shifted,
combined in the ALU and the result written back

28
Three-stage pipeline (Cont.)

Single cycle instructions

• complete at a rate of one per clock cycle
29
ARM -Three-stage pipeline organization
(Cont.)

30
Principal components Three-stage pipeline

• The register bank, which stores the processor state.

• It has two read ports and one write port

• Each to be used to access any register, plus an additional read

port and an additional write port that give special access to
r15, the program counter (pc).

• The barrel shifter, which can shift or rotate one operand by

any number of bits.

31
 Principal components of Three-stage pipeline
(Cont.)
• The ALU, which performs the arithmetic and logic functions
required by the instruction set.

• The address register and Incrementer, which select and hold

all memory addresses and generate sequential addresses when
required.

• The data register, which hold data passing to and from

memory.

• The instruction decoder and associated control logic.

32
 Three- stage Execution performance

• Tprog = the time required to execute a given program

• Ninst = the number of ARM instructions executed in the
program
• CPI =the average number of clock cycles per instruction
• Fclk = the processor’s clock frequency

33
 Optimal Pipelining

• All operations here are on registers (single cycle execution)

• In this example it takes 6 clock cycles to execute 6 instructions
• Clock cycles per Instruction (CPI) = 1
34
 ARM Exception Types
– ARM Exception Types
• Reset
• Undefined instruction
• Software Interrupt (SWI)
• Prefetch Abort
• Data Abort
• IRQ
• FIQ

35
 ARM Exceptions Types (Cont.)
• Reset
– Occurs when the processor reset pin is asserted
– For signalling Power-up
– For resetting as if the processor has just
powered up
– Software reset
– Can be done by branching to the reset vector
(0x0000)
• Undefined instruction
• Occurs when the processor or coprocessors
cannot recognize the currently execution
instruction
36
 ARM Exceptions Types (Cont.)
• Software Interrupt (SWI)
– User-defined interrupt instruction
– Allow a program running in User mode to request
privileged operations that are in Supervisor mode
For example, RTOS functions
• Prefetch Abort
– Fetch an instruction from an illegal address, the
instruction is flagged as invalid
– However, instructions already in the pipeline continue
to execute until the invalid instruction is reached and
then a Prefetch Abort is generated.

37
 ARM Exceptions Types (Cont.)
• Data Abort
– A data transfer instruction attempts to load or store
data at an illegal address
• IRQ
– The processor external interrupt request pin is
asserted (LOW) and the I bit in the CPSR is clear
(enable)
• FIQ
– The processor external fast interrupt request pin is
asserted (LOW) and the F bit in the CPSR is clear
(enable)

38
 Handling an exception
• Exceptions arise whenever the normal flow of a program
has to be halted temporarily

• ARM state : Copies the address of the next instruction

into the LR (current PC + 4, or PC + 8 depending on the
exception)

• Thumb state : writes the value of the PC into the LR,

offset by a value (current PC + 4, or PC + 8 depending
on the exception).

39
 Handling an exception (Cont.)

• Copies the CPSR into the appropriate SPSR

• Forces the CPSR mode bits to a value which

depends on the exception

• Forces the PC to fetch the next instruction from

the relevant exception vector

40
 Leaving an exception

• Move the LR, minus an offset to the PC. The

offset varies according to the type of exception

• Copy the SPSR back to the CPSR

• Clear the interrupt disable flags that were set on

entry.

41
Exception vectors Table

42
ARM Exception Vector Table

43
ARM Exception Priorities

44
 Course Name:
Embedded & Signal Processing Architectures

Course Code: ECE308

Introduction to Embedded C
Unit 1
Embedded C Programming Fundas.
Characteristics of Embedded System

• Embedded system consist of software and hardware

• Embedded devices are resource constrained
• Embedded system typically uses smaller, lesser power
consuming components
• It is more tied to the hardware

Features of ES Programming

• Machine code – speed & size

• Maximum utilization in minimum space
• Supports low level & high level languages

2
 Embedded C Programming Fundas.
C Vs. Embedded C

C programming Embedded C programming

C is a general purpose programming language, Embedded C is an extension of C language, it is

which can be used to design any type of desktop used to develop micro-controller based applications
based applications.

C programming language code - No need to know You must have good knowledge about the hardware
about computer hardware i.e. C language is not for that you’re developing any code. Embedded C is
hardware dependent language. fully hardware dependent language.

3
 Embedded C Programming Fundas.
C language program is hardware independent. Embedded C program is hardware dependent.

Standard compilers can be used to compile and Specific compilers that are able to generate
execute the program. particular hardware/micro-controller based output.

Need to write full program from scratch while The compiler generates some initial code
developing a C language code. automatically based on the selected μP/μC.

we can use standard function like printf(), scanf() etc These functions may not work, because in an
for output and input. embedded device there may not any standard output
device you have to write code to display output to
connected display unit like 16X2 LCD, graphics
display etc.

4
 Embedded C Programming Fundas.
C language compilers generate operating system Embedded C language compilers generate
dependent executable files that can be run on the hardware dependent files that you have to upload
same operating system. in the micro-controller

Readability modifications, bug fixing are very easy It’s not too easy to read, understand, modify and fix
in a C language program. the bugs in an Embedded C language program.

GCC (GNU Complier collection), Borland turbo C, Keil compiler (An Arm company compilers), AVR
Intel C++ compiler are some of the popular GCC – are some of the popular compilers to
compilers which are used to compile, execute a C compile, run an Embedded C language program.
language program.

5
Embedded C Programming Fundas.
Basic Embedded C Program Structure

#include <avrio.h> void main

int count; {
int fun_delay(int x) int k;
{ pi = 0x00; k = 10;
int i; while(1)
for(i=0;i<=x;i++) {
} pi = 0xFF;
fun_delay(k);
pi = 0x00;
fun_delay(k);
}
}
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 Embedded C Programming Fundas.
Device specific header file contains memory
#include <avrio.h> map details
void main Main program. Program should have only one
main function.
{
int k; Local variable
pi = 0x00; k = 10; Initialization section. Instructions to initialize
while(1) variables, IO ports, devices, function registers.
{ Endless loop (Repeat forever). Can also be
pi = 0xFF; used: For(;;)
fun_delay(k); Function call #1
pi = 0x00;
fun_delay(k); Function call #2
}
}

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Embedded C Programming Fundas.