BE 315 Homework 1 Due Tuesday, January 25, 2022 SOLUTIONS 1, An amplifier operating from :+3 V supplies provides a 2.2 V peak sine wave across a 100 90 load when provided with a 0.2 V peak input from which 1.0 mA peak current is drawn, Find the voltage gain, current gain, and power gain expressed as ratios and in decibels. Ifthe amplifier efficiency is 10% find the supply power, supply current, and amplifier power dissipation av Zz, +o = ; ow \Y, =20.7ue | 1 » rey 3 > Ke i> Bes Mee a9% = 20.848 A Ap= Ava = (a2) = 242 Wy = 23ede = 2oBs2ED Wo. (av 22mA = p= Lee. baad) 2 9H,2 a i = wo = 1015 Pac = Pre. aS ee Ty+ ER 7 40B ma p= Gaeay = Ww a Pass = Be tPp “PT Qu teW tleW W2RW = 2179nW2 Consider the voltage-amplifercieuit model shown below, in which Aye = 100 V/V under the following conditions: (©) R= R,/10, Re = Ro/10 Calculate the overall voltage gain v/v, in each case, expressed both directly and in decibels, MF 1A. = A, v, Re RQ fo ee cee ve Vs Ree Qik _ an Re ve A. Reh BOER @) Ri =10Rs, Ry =10k, Vo = to By LORS —s = v= Vs Re 11% B2ONY = 3e.348 by Ri=M%, R=R, _ ts ke e = B 1 a age AYE 284 sc) Riz tks, Ru =! Re | We NRL 8 Mz - oe Oe one Go dBAyo =4088 = 19a 100 3. An amplifier with 40 dB of open-circuit voltage gain, resistance of 100 1, drives a load of 500 92. What volt you expect with the load connected? If the amplifier he ‘what is the rms value of the largest sine-wave in is the corresponding output power available? ‘an input resistance of 1 MM, and an output, age and power gains (expressed in dB) would is @ peak output-current limitation of 20 mA, put for which an undistorted output is possible? What 500 uM sig = = %= 1% onm 7 Av ~ WH FOG *F33y = 38448 2 = = R > Fon ie % Ve Joon tao 7s = = 5 7 Per = Whine A, Sen * 139 Xi0 =Fla4da Loney + On A Vomey = (20nAYS00.) = lov a q |e Veep eee | KV Ay ov Cet ee Oe R= (OVYQOmA) _ mex — 7 ~F \O mW res4. 8.10 mV signel source having an internal resistance of 5 kf? is connected to an amplifier for which the input resistance is 1 kA, the open circuit voltage gain is 100 V/V, and the output resistance is 200 0. ‘The amplifier is connected in turn to 8 100 9 load. (a) What overall voltage gain results as measured from the source internal voltage to the load? What would the gain be if the source was connected directly to the load? (b) Now instead, replace the source by its Norton equivalent and the amplifier with the equivalent current amplifier from Table 1.1 (also in your notes). What is the current gain i/i,? o) KD 200. Mo = Wl = Ve “es ‘02% = -~344B Ye si ey d te sy >) = Aa tA, BE ; a Ais Aw % oh Vest Ai a ° vee *™D Da 0) We oe = Ma a US ee 2 tot Angie Ben 7(0(E) iE aE )(2 Nsw) = 277-8 a = 43.9dB5. You are given two amplifiers A and B, to connect in cascade between a 10 mV, 100 kf source and a 100 9 load. The amplifiers have the following characteristics: jpop FL L A B aa voltage gain 100 V/V | 10 V/V input resistance | 100 kM | 10 KO Vs 10023 Vo output resistance | 10K | 10 Ss Eo Your problem is to decide how the amplifiers should be connected. To proceed, evaluate the two possible connections between source $ and load L, namely SABL and SBAL. Find the voltage gain {or each both as a ratio and in decibles, Which amplifier arrangement is best? A lok B 1K o— + g Ny Vika e lov, Vs lors. \O%, Cose SAQL 1ooK2. ' A — = ay, Ye Vs Toon seinen 2 ‘ Oe oy 2 —DLrtét—SC 50%, 7 a loo == wo, = 25000 Vo = 10%g jenvion 1100 Mg ns © M = ag73% = avrde Ys Cose SBAL ey 1K sy 1 . Vig = % Teen von YN loon = Jo 100 Vi, > lov, TwoK Hk TY tor % [ . 100g 10000, 1D We ay Yo > 100Vig TOK HO rol0o 1) yor? % 2 gq % = -1dB Pre&r SARL “ : Con aur Sion6. Design an amplifier that provides 0.5W of signal power to a 1000 oad resistance, ‘The signal source roves «90 nV rms signal and has a resistance of 0.5 MP. Three types of volagweunaior nerve ate availble 3 : (0) A high-input resistance type with Ry =1 MO, Ave = 10,and Ry = 10k 1S* Ge high Re (0) A high-gain type with Re = 1040, Ave = 100, and Ry = 1 KO (©) A towoutput resistance type with R= 10K0, Aye = 1,and Re=209 &— Last Br tou Ro Design a suitable amplifier using a combination of thes stages. Your design should utilize the minimom umber of stages and should ensure that the signal level is not reduced below 10 mV at any point in ‘he amplifier chain, Find the la voltage and the power output realized SMD IDkN. Veo + 30NG 128 Vig a 2 ite | ole 8 Lok = 5% ig ~ 1O%, Towtion — %,. —CrrC— i ce 160 ee Vo* Vie Tape20 Cet Since Vg = ZOmVems OAS bbw aon a Signal uel Vig = 100 Ves above lOnV . ML Poin Vie = 9.09 Vems oe [ Vo = 7. 56Vems 7 R= Mee = .opw 1OOse 6