Electronics design II

Exercise 2. Amplifiers
Examples
E1. Calculate parameters a), b) and c) of the source follower in figure 1
a) Voltage gain, b) output resistance and c) linear range of the output. Vdd is
5V.

Fig.1 Source follower.

E2. A common-gate stage is showed in Figure 2. Calculate

a) The input impedance
b) The voltage gain

Rs=50

Fig2. A common-gate stage.

E3. Calculate following parameters of the differential pair shown in Fig. 3.
a) Voltage gain (without load)
b) transconductance (short circuit load)
c) output resistance
d) input common mode range

Input common mode voltage is 3 V.

Electronics design II 9/8/20 1

 V dd
5

W=10 W=10
L=5 L=5
M3 M4
V out

W=10
in+ L=5 in-
M1 M2
20A

W=10
L=10
M6 M5

Kuva 2.

Fig. 3. The differential pair.

Task to be calculated:
H1. Define the gain of the CS-amplifier shown in Fig 4. Ibias is selected so that
a) ID1 = ID2= 10A, W1/L1=W2/L2=10m/1m=10 (Av ~ -45,
150mV<Vout<4.74V)
b) ID1 = ID2= 40A, W1/L1=W2/L2=10m/1m=10 (Av ~ -23,
300mV<Vout<4.48V)
c) The increase of bias current leads to the decrease of gain and the narrowing of
the output range. What aspect ratio should be used in transistors M1 and M2 if the
output range is wanted to remain the same. How large is the gain in such design?

Fig. 4. Common Source amplifier

H2. Give an estimate for the AV, Rout of the amplifier shown in Fig.5. (Av ~ -
18400V/V, Rout ~ 19.2M) L1=L2=1m, W1=W2=100m, Ibias=50A. You may
assume, that R2  R

Electronics design II 9/8/20 2

 Fig. 5 Telescopic cascode amplifier.

H3. Give an estimate for the differential pair shown in Fig. 6. Iref=300A.

a) Transconductance(950S)

b) Output resistance (44 k)

c) Av (42 V/V)

d) Common mode range of the input (0,255V<Vincm<3,24V)

e) Linear output range (0,26V-4V) , when the common mode voltage of input is
3V.

20 mV AC signal is at the input of the differential pair and the common mode
signal at the input is 3V. Evaluate the following questions according to the result
of the above.

f) AC- Signal at the source of the M3 and M4?

g) AC-current through transistors M3-M6.

h) AC-signal at the output.

i) Assume that DC-voltage at the output is 2.1 V. Is the output signal clipped/sat-
urated when input signal is 20 mV.

j) The reference current is not ideal and there is 20 uA disturbance in a current

source. Evaluate what are the currents through transistors M2-M6 and what kind
of voltage signal is seen at the output.

Electronics design II 9/8/20 3

 Fig.6. Differential pair.

Answers to the examples:

E1. The source follower is usually used as an output buffer. Check that source fol-
lower is biased in active region.

1 𝑊
𝐼𝑑 ≈ 2 ∙ 𝜇𝑛 𝐶𝑜𝑥 ∙ ∙ (𝑉𝐺𝑆 − 𝑉𝑡𝑛 )2solve VGS,
𝐿

2 ∙ 𝐼𝑑 2 ∙ 50𝜇𝐴 ∙ 10𝜇𝑚
𝑉𝐺𝑆3 = √ + 𝑉𝑡𝑛 = √ + 1 𝑉 = 2,04 𝑉
𝑊 92𝜇/𝑉 2 ∙ 10𝜇𝑚
𝜇𝑛 𝐶𝑜𝑥 ∙ 𝐿

Output DC-voltage have to be calculated by iterating because of body effect and

we do not know the threshold voltage of the transistor M1 and the output voltage
so that we could solve VSB. Vgs1 is first calculated without taking into account
the body effect. 𝜇𝑛 𝐶𝑜𝑥 = 𝐾𝑝

𝐼𝑑2 = 𝐼𝑑3 = 𝐼𝑑1

Electronics design II 9/8/20 4

 2LI D
UGS1 = ------------ + V T0 = 0,47V + 1V = 1,47V
Kp W
Uout = Vin – UGS1 = 4V – 1,47V = 2,53V

𝑉𝑜𝑢𝑡 = 𝑉𝑆𝐵

Thus the threshold voltage of the M1 is

VT = VTo +  ( 2 F + VSB – 2 F ) = 1 + 0,5( 0,6 + 2,53 – 0,6 )

V T = 1,50V

and again VGS1

2LI D
UGS1 = ------------ + VT = 0,47V + 1,50V = 1,97V
Kp W

𝑉𝑜𝑢𝑡 = 𝑉𝑆𝐵 = 𝑉𝑖𝑛 − 𝑉𝐺𝑆1 = 4𝑉 − 1,97𝑉 = 2,03𝑉

𝑉𝑇 = 𝑉𝑇𝑜 + 𝛾 (√2|| + 𝑉𝑆𝐵 − √2||) = 1 + 0,5(√0,6 + 2,03 − √0,6) = 1,42𝑉

After the couple of the iteration

UGS1 = 1,90V VT = 1,43V Uout = 2,10V

The drain of the M2 can go one threshold below the gate voltage. Gate voltage is 2.04
V so that Veff2=2.04 V-1 V=1.04V< Vout thus the amplifier is active region.

a) Voltage gain

Draw the small signal model. M2 can be replaced by an resistor rds2 because gate of
M2 is ac-ground (AC-current source open circuit and then no current can go through
diode connected transistor) Vgs1=vin-vout and body-effect transconductance
VSB=Vout:

We can calculate the needed small-signal parameters:

W 1
gm = 2K p ----- I D rds = ---------
L ID

Electronics design II 9/8/20 5

 gm1 = 0,214mS rds1 = 400k rds2 = 2M
𝛾 0,5
𝑔𝑠1 = 𝑔𝑚1 ∙ = 0,214𝑚 ∙ = 32,6𝜇𝑆
2√0,6 + 2,1
2 ∙ √2|𝐹 | + 𝑉𝑆𝐵

Now we have to solve the node equation of the output node to find out the gain:

𝑉𝑜𝑢𝑡 𝑉𝑜𝑢𝑡 𝑉𝑜𝑢𝑡

−𝑔𝑠1 𝑉𝑜𝑢𝑡 + 𝑔𝑚1 (𝑉𝑖𝑛 − 𝑉𝑜𝑢𝑡 ) = + =
𝑟𝑑𝑠1 𝑟𝑑𝑠2 𝑟𝑑𝑠2 ‖𝑟𝑑𝑠1

𝑉𝑜𝑢𝑡
𝑔𝑚1 𝑉𝑖𝑛 = +𝑔𝑠1 𝑉𝑜𝑢𝑡 + 𝑔𝑚1 𝑉𝑜𝑢𝑡
𝑟𝑑𝑠2 ‖𝑟𝑑𝑠1

𝑉𝑜𝑢𝑡 𝑔𝑚1 𝑔𝑚1

= ≈ ≈ 0.867
𝑉𝑖𝑛 1⁄ + 𝑔 + 𝑔 𝑔𝑠1 + 𝑔𝑚1
𝑟𝑑𝑠2 ‖𝑟𝑑𝑠1 𝑠1 𝑚1

Beacause of the body-effect the voltage gain of the NMOS-source follower is under
one. Without the body-effect the gain would be ~ 0.986 if taking account rds.

b) Output resistance

Set Uin = 0 and apply the test voltage Vx to the output node and solve the current Ix.
From the small-signal model of the a) -section we get

Summing current at the output node

𝑣𝑥
𝑖𝑥 − 𝑔𝑠 𝑣𝑥 − 𝑔𝑚1 𝑣𝑥 =
𝑟𝑑𝑠1 ‖𝑟𝑑𝑠2

Now the output resistance is Vx / ix we get

𝑣𝑥 1 1
= ≈
𝑖𝑥 𝑔 + 𝑔 + 1 𝑔𝑚1 + 𝑔𝑠
𝑚1 𝑠 𝑟𝑑𝑠1 ‖𝑟𝑑𝑠2
Rout = 4055 Ω

To decrease the output resistance the transconductance of the input transistor have to
be increased by increasing the W/L ratio and DC-current.

Electronics design II 9/8/20 6

c) Output linear range

The minimum voltage is limited by the effective voltage (Veff also known Vds_sat) :

2 ∙ 𝐼𝑑
𝑉𝐺𝑆2 − 𝑉𝑡𝑛 = 𝑉𝑒𝑓𝑓2 = 𝑉𝑑𝑠2𝑠𝑎𝑡 = √ = 1,04 𝑉
𝑊
𝜇𝑛 𝐶𝑜𝑥 ∙ 𝐿

Upper limit is limited by the VGS1 and the maximum voltage at the gate is the Vdd so
we get:
Uomax = Vdd – UGS1

Ugs1 have to be calculated by iterating because the threshold voltage of the M1 is un-
known when Vin = 5 V. After couple of the iteration we get
UGS1 = 2 02V VT = 1,56V Uout = 2 98V

The output linear range is [1.04 V,2.98 V] ie. 1.94 V.

E2. A common-gate stage is showed in Figure 3. Calculate

a) The input impedance
b) The voltage gain
Rs=50,

Fig. 3. A common-gate stage.

a) The input impedance can be calculated by inserting the test voltage at the input and
then solving the vin/iin=rin. Small-signal model shown below a) :

Electronics design II 9/8/20 7

 Fig. 4 a) Rin and b) gain.
𝑣𝑖𝑛 − 𝑣𝑑1
𝑖𝑖𝑛 = 𝑔𝑚1 𝑣𝑖𝑛 +
𝑟𝑑𝑠1

𝑣𝑑1 = 𝑖𝑖𝑛 𝑟𝑑𝑠2

Now inserting the below equation to top one we get:

𝑣𝑖𝑛 − 𝑖𝑖𝑛 𝑟𝑑𝑠2

𝑖𝑖𝑛 = 𝑔𝑚1 𝑣𝑖𝑛 +
𝑟𝑑𝑠1

rearranging

𝑟𝑑𝑠2 1
𝑖𝑖𝑛 (1 + ) = 𝑣𝑖𝑛 (𝑔𝑚1 + )
𝑟𝑑𝑠1 𝑟𝑑𝑠1
𝑟
𝑣𝑖𝑛 (1 + 𝑟𝑑𝑠2 ) 1
𝑑𝑠1
= , 𝑔𝑚1 ≫
𝑖𝑖𝑛 (𝑔 + 1 ) 𝑟𝑑𝑠1
𝑚1 𝑟 𝑑𝑠1

𝑣𝑖𝑛 1 𝑟𝑑𝑠2 2
≈ (1 + )≈ , 𝑖𝑓 𝑟𝑑𝑠2 ≈ 𝑟𝑑𝑠1
𝑖𝑖𝑛 𝑔𝑚1 𝑟𝑑𝑠1 𝑔𝑚1

W
gm = 2C OX ----- ID
L

1 1
r ds = --------- = -------
I D g ds

and

I D3 ( W  L )3
------- = -------------------
I D2 ( W  L )2

we can calculate the values of the small-signal model parameters and currents of the
transistors in figure 3.

Electronics design II 9/8/20 8

 W –2
gmM1 = 2C OX ----- I D = 2  30AV  125  500A = 1 94mS
L

1 1
rdsM1 = ------------------------------------------
–7
= ------------- = 20k
2  10 50S
-  500S
-------------------
–6
2  10

W/L Id gm gs  gds
M1 250m/m=125 500A 1,94mS 520S 0,1 50S

M2 250m/m=250 500A 0,1 50S

M3 50m/m=50 100A

1 1
rdsM2 = ------------------------------------------
–7
= ------------- = 20k
1  10 50S
-------------------
–6
-  500S
1  10

By inserting the values to the equation of the input impedance we get

r ds2
Rin  --------  1 + --------- = --------------------  1 + ------------- = 1k
1 1 20k
g m1 r ds1 1 94mS 20k

b) The voltage gain can be calculated from the small-signal model showed in Fig. 4 b).
Now we can produce node equation for output node and the gain is Vout/Vs1.
𝑣𝑜𝑢𝑡 𝑣𝑜𝑢𝑡 𝑣𝑠1
+ − = 𝑔𝑚1 𝑣𝑠1
𝑟𝑑𝑠2 𝑟𝑑𝑠1 𝑟𝑑𝑠1

1 1 1
𝑣𝑜𝑢𝑡 ( + ) = 𝑣𝑠1 (𝑔𝑚1 + )
𝑟𝑑𝑠2 𝑟𝑑𝑠1 𝑟𝑑𝑠1

1
𝑣𝑜𝑢𝑡 (𝑔𝑚1 + 𝑟𝑑𝑠1 )
= ≈ 𝑔𝑚1 ∙ 𝑟𝑑𝑠2 ‖𝑟𝑑𝑠1 ,
𝑣𝑠1 1 1
(𝑟 + 𝑟 )
𝑑𝑠2 𝑑𝑠1

1 1
𝑏𝑒𝑐𝑎𝑢𝑠𝑒 𝑔𝑚1 ≫ 𝑎𝑛𝑑 = 𝑟𝑑𝑠2 ‖𝑟𝑑𝑠1
𝑟𝑑𝑠1 1 1
𝑟𝑑𝑠2 + 𝑟𝑑𝑠1

The result is a gain from source to output and we need to calculate what is the effect
of the Rs. Now we can use the input impedance and Rs to calculate the voltage divi-
sion at the input and that is:

2
𝑟𝑖𝑛 𝑣𝑠1 𝑔𝑚1
𝑣 = 𝑣𝑠1 => =
𝑟𝑖𝑛 + 𝑅𝑠 𝑖𝑛 𝑣𝑖𝑛 2
𝑔𝑚1 + 𝑅𝑠

Electronics design II 9/8/20 9

Now the total gain is

2
𝑣𝑜𝑢𝑡 𝑣𝑠1 𝑔𝑚1
∙ = 𝑔𝑚1 ∙ 𝑟𝑑𝑠2 ‖𝑟𝑑𝑠1 ∙
𝑣𝑠1 𝑣𝑖𝑛 2
𝑔𝑚1 + 𝑅𝑠

and we get

2
𝑣𝑜𝑢𝑡 1.94 𝑚𝑆
= 1.94 𝑚𝑆 ∙ 20𝑘𝛺‖20𝑘𝛺 ∙ ≈ 18.5 𝑉/𝑉
𝑣𝑖𝑛 2
1.94𝑚𝑆 + 50𝛺

Electronics design II 9/8/20 10

E3. First calculate DC operating point. Input common mode voltage is 3V.
5 V dd

W=10 W=10
L=5 L=5
M3 M4
v2 vout

in+ W=10 in-

M1 L=5 M2
20A
v1

W=10
L=10
M6 M5

2I D5 L 5
U gs5 = V T0 + ----------------- = 1,66V
W5 K pn
2I D5 L 5
Udsat5 = ----------------- = 0,66V
W5 K pn

Ugs1 have to be calculated by iterating. Ugs1 without body-effect.

2L1 I D1
UGS1 = ----------------- + V T0 = 0,33V + 1V = 1,33V
Kp W 1
U v1 = Vin – UGS1 = 3V – 1,33V = 1,67V

Thus, the threshold voltage of M1 taking account the body-effect is

VT = VTo +  ( 2 F + VSB – 2 F ) = 1 + 0,5( 0,6 + 1,67 – ( 0,6) )
VT = 1,37V

and again
2L1 I D1
UGS1 = ----------------- + V T = 0,33V + 1,37V = 1,70V
Kp W 1

After the couple of iterations

UGS1 = 1,64V V T1 = 1,31V Uv1 = 1,36V

Because Uds5 = 1.36 V > Udsat5 =Veff5= 0.66 V, M5 is in an active region.

The saturation voltage of the M1 is Ugs1 - VT1 = 0.33 V.

Next calculate the voltage V2.

Electronics design II 9/8/20 11

 2I D3 L3
Usg3 = V T0 + ----------------- = 1,58V
W 3 K pp
2I D3 L3
Udsat3 = ----------------- = 0,58V
W 3 K pp

Uv2 = Vdd – Usg3 = 5 – 1,58 = 3,42V

Because Ud1 = 3.42V > Ug1 - VT1 = 3V - 1.31V = 1.69V, M1 is also in active region.

The DC operating point of M1 and M2 and secondly M3 and M4 are same.

Because every transistors are operating in active region is the whole amplifier in ac-
tive region.

a) Voltage gain without output load.

Draw a small-signal model.

vout
uin u3
in+ in- gm4u3
ugs1 ugs2 gm1ugs1 gm2ugs2
rds1 rds3 1/gm3 rds4 rds2

M1 M3 M4 M2

Node u3:
0 − 𝑣3
𝑔𝑚1 𝑣𝑔𝑠1 =
𝑟𝑑𝑠1 ‖𝑟𝑑𝑠3 ‖1⁄𝑔𝑚3
g m1 ugs1
u3 = –g m1 u gs1  r ds1  r ds3  --------  –------------------
1
-
g m3 g m3

1/gm<<rds
Inserting above u3 to below
g m1 u gs1
gm4 u 3 = –g m4 ------------------- = –g m1 ugs1
g m3

because gm3=gm4.
0 − 𝑣𝑜𝑢𝑡
𝑔𝑚4 𝑢3 + 𝑔𝑚2 𝑢𝑔𝑠2 =
𝑟𝑑𝑠4 ‖𝑟𝑑𝑠2

v out = –( g m4 u 3 + gm2 u gs2 ) ( rds2  rds4 ) = ( g m1 u gs1 – g m2 u gs2 ) ( r ds2  rds4 )

= g m1 ( u gs1 – u gs2 ) ( rds2  r ds4 ) = g m1 v in ( rds2  r ds4 )
vout gm1
A = --------- = g m1 ( r ds2  rds4 ) = --------------------------
vin g ds2 + g ds4

Electronics design II 9/8/20 12

 W 1
gm = 2K p ----- I D rds = ---------
L ID

–6
60,7 10
A = ------------------------
–6
= 101
0,6 10

u3
in+ uin in- gm4u3
i out
ugs1 ugs2 gm1ugs1 gm2ugs2
rds1 rds3 1/gm3

M1 M3 M4 M2

b) transconductance to the short circuit load.

Draw a small-signal model.

g m4 u3 = –g m1 u gs1
i out = g m1 ugs1 – gm2 u gs2 = g m1 v in
i out
g m = -------
- = g m1 = 60,7S
v in

c) output resistance
r out = rds2  rds4 = 1,67M

d) Input common mode range

From down

2I D5 L5 2L1 I D1
U inmin = 0 + U dsat5 + U GS1 = ----------------- + ----------------- + VT1
W 5 Kpn Kp W 1

V1_min is Udsat5=0.66V. This is also Usb_M1_min. So Vt1_min

VT = VTo +  ( 2 F + VSB – 2 F ) = 1 + 0,5 ( ( 0,6 + 0,66 ) – ( 0,6 ) ) = 1,17V

Uinmin = 0 + Udsat5 + UGS1min = 0,66 + 1,50V = 2,16V

To up
2I D3 L3 2I D1 L1
UV1max = Vdd – U SG3 –Udsat1 = 5 – ----------------- – VT ( M3 ) – ----------------- = 3,093V
W 3 K pp W 1 K pn

thus Vtn caused by bodyeffect is

𝑉𝑡𝑛 = 1 + 0,5(√0,6 + 3,093 − √0,6) = 1,574 𝑉

Electronics design II 9/8/20 13

 2 ∙ 𝐼𝑑
𝑉𝑒𝑓𝑓1 = √ = 0,33 𝑉
𝑊
𝜇𝑛 𝐶𝑜𝑥 ∙ 𝐿

VGS1max=Vtn+Veff1=1,904 V
·
Uinmax = UV1max + UGS1max = 3,093V + 1,904V = 5 00V

Input common mode range is then 2.1V <VinCM<5V.

Electronics design II 9/8/20 14