Tmax 2017.09 LG

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CUSTOMER EDUCATION SERVICES
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TetraMAX
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Workshop
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Lab Guide
30-I-021-SLG-017
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Synopsys Customer Education Services

690 E. Middlefield Road
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Mountain View, California 94043

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Workshop Registration: http://training.synopsys.com

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www.synopsys.com
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For Internal Microchip Training Purposes Only

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Disclaimer
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Synopsys, Inc.
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690 E. Middlefield Road

Mountain View, CA 94043
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www.synopsys.com
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Document Order Number: 30-I-021-SLG-017

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TetraMAX Lab Guide

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Synopsys Customer Education Services

Handling Designs
2 and Libraries
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Learning Objectives
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During this lab, you will debug reading library and design
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building problems.
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After performing this lab, you should be able to:

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 Debug problems with the Core cell library

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 Define Black Box model for missing modules

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Lab Duration
45 minutes
Handling Designs and Libraries Lab 2-1

Synopsys 30-I-021-SLG-017

Lab 2
Getting Started
The UNIX directory for this entire lab is lab2_build.
Answers and suggestions are located at the end of this lab.
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If you need help…
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Use the lecture material, man pages, TetraMAX On-Line Help, or the User
Guide.
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BUILD-T> help –v read_netist
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DRC-T> man run_drc
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DRC-T> man s22
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TEST-T> man set_atpg
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Remember the history commands! lM
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BUILD-T> history
BUILD-T> !!
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You do not need to type the entire command or option names!

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BUILD-T> read_net orca_final.v

TEST-T> set_atpg –capt 3 –abor 50 –pat 0
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You can also hit the TAB key while typing to complete command names.
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Lab 2-2 Handling Designs and Libraries

Synopsys TetraMAX Workshop

Lab 2
Background
The design used for ATPG during this entire workshop, ORCA, is depicted below.
The design has two main interfaces, a PCI interface and an SDRAM bus. The PCI
interface can operate at frequencies of 33 and 66 MHz. The SDRAM bus is capable
of addressing PC133 type memory.
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The processor core consists of a high-speed RISC machine. Under normal
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circumstances RISC_CORE operates at a frequency of 200 MHz. In power save
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mode the frequency drops down to 100 MHz. The remaining components of ORCA
always operate at a frequency of 100 MHz.
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All asynchronous interfaces are isolated with two-port FIFOs.
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100
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ORCA
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Instructions
PARSER
66/33 66/33
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100
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200/100
PCI_RFIFO
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PCI Bus PCI_CORE

RISC_CORE
PCI_WFIFO
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133 100 100

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133
SDRAM_RFIFO
BLENDER
SDRAM
SDRAM_IF
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Bus
SDRAM_WFIFO
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It is not important to understand the full functionality of this design (in fact, this
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design is NOT fully functional!). This design is merely intended to give you an
understanding of the issues that can occur when performing ATPG on multi-clock
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designs.
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The structural Verilog simulation descriptions for the technology library used by the
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ORCA design are stored in a core.v file for the core cells (nand/nor/not/xor gates,
flip-flops, latches, etc.) and an io.v file for the I/O pads.


Lab 2
Instructions
Answers / Solutions
There is an Answers / Solutions section at the back of each lab. You are encouraged
to refer to this section to verify your answers, or to obtain help with the execution of
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some steps. Solution files can be found in the .solutions directory.
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Task 1. Invoke TetraMAX
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1. Make sure your current working directory is lab2_build.
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2. Start the TetraMAX GUI and observe the startup messages.
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unix% cd lab2_build
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unix% tmax &
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Task 2. Read I/O and Core Library Files
1.
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To read in the I/O cell library, enter this command at the input line:
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BUILD-T> read_netlist ../libs/io.v
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Question 1. Were any errors reported during the read?

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.....................................................................................................
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2. Confirm the error status with the following command.
BUILD-T> report_modules -errors

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3. Read in the library models for the core cells, ../libs/core.v.

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BUILD-T> read_netlist ../libs/core.v

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Question 2. What violations were reported? Which is most severe?

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...................................................................................................
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4. Determine where the violations occurred using the following command:

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BUILD-T> report_violations n2


Lab 2
Question 3. What construct seems to be the cause for all the warnings?
...................................................................................................
Question 4. Is this construct a behavioral or structural construct in

Verilog?
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5. Generate a summary modules report and answer the following questions.
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BUILD-T> report_modules -summary
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Question 5. How many modules were structural?
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Question 6. How many modules contained behavioral constructs?
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...................................................................................................
Question 7. lM
How many UDPs were combinational versus sequential?
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Task 3. Building the ORCA Design

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1. Read the ORCA design, orca_final.v.

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BUILD-T> read_netlist ../design_data/orca_final.v

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2. Build the ATPG model for the ORCA design.

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BUILD-T> run_build_model
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Question 8. Is TetraMAX in DRC mode? If not, why?

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Question 9. Can you analyze this violation graphically? Why?

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...................................................................................................


Lab 2
3. Bring up the man page for this violation.
BUILD-T> man b5
4. Perform the first suggestion in the What Next section and answer the
following questions.
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Question 10. How many modules are undefined?
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...................................................................................................
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Question 11. What command can be used to define a black box?
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5. Define the black boxes for all the undefined modules.
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BUILD-T> set_build –black_box [list CLKMUL PLL]
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BUILD-T> set_build –black_box [list ram32x32 ram32x64
ram16x128] lM
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6. Try building the ORCA design again.

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Examine the run build transcript and answer the following questions.
How many primitives did TetraMAX use to model the
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Question 12.
ORCA design functionality?
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...................................................................................................
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Question 13. What netlist related violations are now reported?

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Lab 2
7. Generate a summary primitives report and answer the following questions.
DRC-T> report_summaries primitives
Question 14. What primitive is used the most?
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Question 15. What primitive is used only once?
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8. Enter TEST mode by running DRC with the SPF file, orca_final.spf.
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DRC-T> run_drc ../design_data/orca_final.spf
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Question 16. Did the B and N violations stop TetraMAX from proceeding
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to TEST mode?
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...................................................................................................
9.
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Use the following command to run automatic ATPG.
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Note: The run_atpg –auto command will automatically
populate the fault list (add_faults –all) if there are no
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existing faults
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TEST-T> run_atpg –auto

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Question 17. What is the test coverage when using black box models for
the RAMS?
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Question 18. Were there any warnings during ATPG related to possible
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library problems?
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Lab 2
Task 4. Reading RAM Models
1. Return to BUILD mode with the following command.
TEST-T> build –force
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2. Remove all the black box definitions.
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BUILD-T> set_build –reset_boxes
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3. Read in the ../libs/rams_sim.v file, which contains the simulation
models for the memory cells.
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BUILD-T> read_netlist ../libs/rams_sim.v
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What violation occurred?
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Question 19.
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...................................................................................................
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Read in the ../libs/rams.v file which contains the ATPG models for the
memory cells.
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BUILD-T> read_netlist ../libs/rams.v

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Question 20. What error occurred?

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...................................................................................................
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5. Work around the error by entering the following commands.

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BUILD-T> set_rules n25 warning

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BUILD-T> read_netlist ../libs/rams.v

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6. Re-apply the black box specification only on the CLKMUL and PLL blocks,
Build the ORCA design and answer the following questions.
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BUILD-T> set_build –black_box { CLKMUL PLL }

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Question 21. How many memory primitives were used?
.....................................................................................................


Lab 2
7. Use the following command to generate a memory report and then answer
following question.
DRC-T> report_memory -all
Question 22. Which module in ORCA contains the most memories?
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8. Regenerate the report with the -verbose option and answer the following
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question.
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Question 23. Which type of ram is used the most?
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9. Enter TEST mode:
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10.
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Use the following commands to run fast sequential ATPG.
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TEST-T> set_atpg –capture 4
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TEST-T> run_atpg -auto

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Question 24. How does the test coverage with memory models compare to
the test coverage obtained with black box models?
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You have completed the “Handling Designs and

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Libraries” lab of the TetraMAX Workshop.

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Lab 2 Answers / Solutions
Answers / Solutions
Task 2. Read I/O and Core Library Files

Question 1. Were any errors reported during the read?
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No errors were reported.
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Question 2. What violations were reported? Which is most severe?
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N2 and N5. N2 is most severe since it indicates an illegal
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construct in the model.
Question 3. What construct seems to be the cause for all the warnings?
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Most violations were caused by the double equal (“= =”)
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operator.
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(Operator "==" not supported).
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There were also warnings due to “always”, “specify”,
“initial”, “task”, and “event” not supported. They are all
behavioral constructs. lM
Question 4. Is this construct a behavioral or structural construct in
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Verilog?
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Behavioral.
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Question 5. How many modules were structural?

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report_modules –summary reports 629

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Question 6. How many modules contained behavioral constructs?
report_modules –summary reports 97

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Question 7. How many UDPs were combinational versus sequential?

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report_modules –summary shows 42 and 334

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respectively.
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Answers / Solutions Lab 2
Task 3. Building the ORCA Design

Question 8. Is TetraMAX in DRC mode? If not, why?
No, a B5 violation (undefined module) was reported.

Question 9. Can you analyze this violation graphically? Why?
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No, because until an ATPG model is built, you cannot enter
DRC mode. The Graphical Schematic Viewer (GSV) is not
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available during BUILD mode.
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Question 10. How many modules are undefined?
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report_modules –undefined indicates there are 5
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Question 11. What command can be used to define a black box?
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set_build –black_box [list PLL CLKMUL]
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set_build –black_box [list ram32x32 ram32x64
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ram16x128]
Question 12. lM
How many primitives did TetraMAX use to model the
ORCA design functionality?
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#primitives=30831
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Question 13. What netlist related violations are now reported?

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N20 and N21.

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Question 14. What primitive is used the most?

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There are 7861 #XOR primitives in the ORCA model.

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Question 15. What primitive is used only once?
There is only one #DLAT.

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Question 16. Did the B and N violations stop TetraMAX from proceeding
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to TEST mode?
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No, TetraMAX is now in TEST mode.

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Question 17. What is the test coverage when using black box models for
the RAMS?
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TetraMAX reports 96.09% test coverage.

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Question 18. Were there any warnings during ATPG related to possible
library problems?
Yes, N20 is a possible library problem. C13 is design

related.
***********************************************************
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* NOTICE: The following DRC violations were previously *
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* encountered. The presence of these violations is an *
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* indicator that it is possible that the ATPG patterns *
* created during this process may fail in simulation. *
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* *
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* Rules: N20 C13 *
***********************************************************
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Task 4. Reading RAM Models.
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Question 19. What violation occurred?
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N2 violations are reported.
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Question 20. What error occurred?
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The read_netlist command reports N25 errors.

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Question 21. How many memory primitives were used?

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10 memory primitives were used. From the

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report_summaries primitives command.

Question 22. Which module in ORCA contains the most memories?
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I_ORCA_TOP/I_CONTEXT_MEM contains 4 of the 10

memories.
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Question 23. Which type of ram is used the most?

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ram32x64 is used in 6 of the 10 memories.

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Question 24. How does the test coverage with memory models compare
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to the test coverage obtained with black box models?

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The coverage is higher when memory models are used,

97.90%.
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3 Running DRC
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Learning Objectives
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During this lab, you will create a Test Protocol for the
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ORCA design using Quick STIL commands and analyze
typical DRC violations.
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 Create a STIL Test Protocol file using Quick STIL

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commands
 Debug S1 violations using the GSV and Analyze button
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 Save a Test Protocol in STIL format

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Lab Duration
30 minutes
Running DRC Lab 3-1


Lab 3
Background
The Test Protocol is not yet available for the version of the ORCA design in this
lab. You will create a STIL format Test Protocol using Quick STIL commands. A
partial command file is provided. You will debug a common DRC violation to
determine what additional commands are needed.
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Lab 3-2 Running DRC


Lab 3
Instructions
Answers / Solutions
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Task 1. Invoke TetraMAX
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1. Make sure your current working directory is lab3_drc.
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unix% cd lab3_drc
unix% tmax &
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Task 2. Read Design and Enter DRC Mode lM
1. Read the design netlist for the ORCA design.
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2. Attempt to build the ATPG model for the ORCA design.

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BUILD-T> run_build_model ORCA

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Question 1. Why did you not have to read in the core and I/O cell files
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(Hint: look at the .tmaxtclrc file in the lab3 directory)?

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Task 3. Run Design Rule Checks

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A file has already been prepared that contains some of the scan specifications for the
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ORCA design using Quick STIL commands.

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Running DRC Lab 3-3


Lab 3
1. Execute this script by entering the following command:
DRC-T> source –e spf.tcl
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2. Perform the scan design rule checks (there is no STIL Protocol File to specify
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yet.)
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DRC-T> run_drc
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Question 2. Did you enter TEST mode?
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Question 3. What violation(s) occurred?
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....................................................................................................
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Task 4. Debug S1 Violations
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1. Move the mouse so the cursor is directly over the first S1 violation in the
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DRC transcript.
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Click on your RMB (Right Mouse Button) and select Analyze Violation.
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Question 4. Did any of the scan chains trace correctly?
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Question 5. Looking at the graphics in the GSV what appears to be the

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cause for the S1 violation (Hint: look at the values of any

primary inputs shown)?
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Note: In the GSV, the scan path is annotated with the “S” character when
viewing Shift pin data (shown as “SSS” in the GSV). This can
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help with debug of S1 violations. The command

set_pindata –shift_character S was added to the
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.tmaxtclrc file to enable this cabability.
Question 6. Which specification seems to be missing from the spf.tcl file?
.....................................................................................................
Lab 3-4 Running DRC


Lab 3
2. Specify this additional information and run DRC again.
DRC-T> add_ . . .
DRC-T> run_drc
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Question 7. Do any of the scan chain trace correctly now?
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3. Move the mouse so the cursor is directly over the first S1 violation in the
DRC transcript.
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cause for the S1 violation now?
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.....................................................................................................
Question 9.
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Which specification seems to be missing from the spf.tcl file?
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DRC-T> add_ . . .
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DRC-T> run_drc
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Question 10. What is the only chain that traces correctly now?
.....................................................................................................
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5. Move the mouse so the cursor is directly over one of the remaining S1
violations in the DRC transcript.
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cause of the S1 violation?

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......................................................................................................
Question 12. Which specification seems to be missing from the spf.tcl file?
....................................................................................................
Running DRC Lab 3-5


Lab 3
DRC-T> add_ . . .
DRC-T> run_drc
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7. You should now be in TEST mode.
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8. Save the Test Protocol in STIL format.
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TEST-T> write_drc my.spf -replace
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9. Run ATPG to check your results.
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Question 13.
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What Test Coverage did you get?
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....................................................................................................
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10. Optional: Investigate and analyze the S and C violations reported during DRC
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checking.
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Question 14. Why are the various S and C violations reported?

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You have completed the “Running DRC” lab of

the TetraMAX Workshop.
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Lab 3-6 Running DRC


Answers / Solutions
Task 2. Read Design and Enter DRC Mode

Question 1. Why did you not have to read in the core and I/O cell files
(Hint: look at the .tmaxtclrc file in the lab3 directory)?
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Because the .tmaxtclrc file includes this command:
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read_net ../libs/libs_tmax.v.gz
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Task 3. Run Design Rule Checks
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Question 2. Did you enter TEST mode?
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No
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Error: Design . . .cannot exit DRC command mode. (M100)
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Question 3. What violation(s) occurred? These S1 violations:
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Error: Chain c0 blocked at MUX gate U149 (24860) after

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tracing 0 cells. (S1-1)

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Running DRC Lab 3-7


Task 4. Debug S1 Violations

Question 4. Did any of the scan chains trace correctly?
No, all had S1 violations.

Question 5. Looking at the graphics in the GSV what appears to be
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cause for the S1 violation (Hint: look at the values of any
primary inputs shown)?
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The scan enable pin has value “XXX” (which means
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unconstrained).
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Question 6. Which specification seems to be missing from the spf.tcl
file?
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DRC-T> add_scan_enables 1 scan_en
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Question 7. Do any of the scan chain trace correctly now?
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No, you now have these S1 violations:
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Error: Chain c0 blocked at DFF gate
I_ORCA_TOP/I_SDRAM_IF/\DQ_out_1_reg[13] (32366) after
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I_ORCA_TOP/I_SDRAM_IF/\mega_shift_0_reg[26][14] (32279)
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after tracing 0 cells. (S1-2)

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I_ORCA_TOP/I_PCI_CORE/\d_out_i_bus_reg[0] (29457)
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I_ORCA_TOP/I_PCI_CORE/\mega_shift_reg[33][12] (29941)
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I_ORCA_TOP/I_PCI_CORE/\pad_out_buf_reg[13] (30390)
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I_ORCA_TOP/I_PCI_WRITE_FIFO/\this_addr_g_reg_reg[1]1
(32732) after tracing 0 cells. (S1-6)
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cause for the S1 violation now?
The test_mode PI is unconstrained.

Lab 3-8 Running DRC


file?
DRC-T> add_pi_constraints 1 test_mode
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Question 10. What is the only chain that traces correctly now?
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Chain c0 successfully traced with 488 scan_cells.
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Tr
I_ORCA_TOP/I_RESET_BLOCK/sdram_rst_ff_reg (32702) after
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I_ORCA_TOP/I_PCI_CORE/\d_out_i_bus_reg[0] (29457) after
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I_ORCA_TOP/I_PCI_CORE/\mega_shift_reg[33][12] (29941)
Error: Chain c4 blocked at DFF gate lM
I_ORCA_TOP/I_PCI_CORE/\pad_out_buf_reg[13] (30390)
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I_ORCA_TOP/I_PCI_WRITE_FIFO/\this_addr_g_reg_reg[1]1
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(32732) after tracing 0 cells. (S1-5)

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Error: Design rules checking failed: cannot exit DRC

command mode. (M100)
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cause for the final S1 violation?

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The prst_n is not declared to be a return-to-1 clock.

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file?
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DRC-T> add_clocks 1 prst_n

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Running DRC Lab 3-9


Question 13. What Test Coverage did you get?
96.10%. If you are seeing lower coverage, double check

your previous steps.
Question 14. Why are the various S and C violations reported?
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# -------------------------------------------------------
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# DRC Summary Report
# -------------------------------------------------------
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# Warning: Rule S19 (nonscan cell disturb) was violated 608
times.
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Look at the run_drc output closely
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Begin nonscan rules checking...
RAM summary: #RAMS=10, #clock_unstable=0, #load_unstable=10…
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Nonscan cell summary:
#DFF=32 #DLAT=1 #RAM_outs=576 tla_usage_type=hot_clock_tla
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Nonscan behavior: #TLA=1 #LE=16 #TE=16 #RAM_outs=576
Nonscan rules checking completed, CPU time=0.00 sec.
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# Warning: Rule S22 (multiply clocked scan chain) was violated
2 times.
Does design have lockup latches? If not, usually neg-edge from one clock
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domain mixed with rising-edge from other clock domain without a lockup
latch. Need to be in primitive view in GSV to see the “clock pin bubble”.
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# Warning: Rule S30 (unstable RAM during test procedure

operation) was violated 10 times.
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report_memory –all –verbose shows all 10 are load unstable

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# Warning: Rule C6 (TE port captured data affected by new

capture) was violated 598 times.
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ORCA has so many because the RAMs are written on the neg-edge. The
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RAM outputs are modeled as neg-edge flops…..ORCA has only 16 real neg-
edge flops. Again, look closely at the run_drc log. Read the C6 man page.
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TetraMAX handles this by default.

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# Warning: Rule C12 (LE port captured data affected by clock)

was violated 16 times.
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# Warning: Rule C13 (TE port captured data affected by clock)

was violated 16 times.
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This is a “clock-as-data” type of violation was part of the design intent for
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ORCA.
# Warning: Rule C17 (clock connected to PO) was violated 18

times.
This is the effect of the sdr_clk going to sd_CK, sd_CKn and the 16
sd_DQ pins. Again, this is part of the original design intent.
Lab 3-10 Running DRC

# Warning: Rule C21 (RAM port unable to capture) was violated

10 times.
Because all the WE2 write clock pins on all the rams are tied-off to 0. These
“2” ports are used in the design as “read” ports.
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# Warning: Rule Z9 (bidi bus driver enable affected by scan
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cell) was violated 44 times.
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Bring up man page. TetraMAX handles this. The only way to avoid this is to
change the design so that in test_mode there is no active path from a scan
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flip-flop to any bidi output enable pin.
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Running DRC Lab 3-11


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Lab 3-12 Running DRC


4 Controlling ATPG
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Learning Objectives
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lM
During this lab, you will use any and all methods to obtain
the target stuck-at test coverage for the ORCA design.
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er

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 Select specific ATPG engines

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 Determine the best capture cycle depth

Fo
 Develop an initial ATPG strategy on a sampled fault list

 Compare regular TetraMAX to TetraMAX II
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Lab Duration
45 minutes
Controlling ATPG Lab 4-1


Lab 4
Background
Follow the flow depicted below to obtain at least 99% stuck-at test coverage for the
ORCA design. Experiment and develop an ATPG strategy on your own or use the
detailed instructions that follow.
ng
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Develop
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initial ATPG
strategy
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ip
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Create sampled fault list
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Experiment with ATPG
engines lM
na
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Explore other ATPG

options
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Coverage High
Enough?
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U
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Run final ATPG

strategy on complete
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fault list
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Lab 4-2 Controlling ATPG


Lab 4
Instructions
Answers / Solutions
ng
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Task 1. Develop Initial ATPG Strategy
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1. Make sure your current working directory is lab4_controlling_atpg.
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unix% cd lab4_controlling_atpg
ch
unix% tmax &
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3. Get into TEST mode, add faults, and create a sampled fault list.
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lM
BUILD-T> run_build
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TEST-T> add_faults –all

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TEST-T> remove_faults –retain 1

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Question 1. What is the advantage of developing an ATPG strategy using

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a sampled fault list?
....................................................................................................
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4. See what Basic-Scan can do:

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TEST-T> set_atpg –capture 0 –abort 10

TEST-T> run_atpg basic_scan_only
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Question 2. What is the starting test coverage?

es
....................................................................................................
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5. Try again with -auto:
TEST-T> reset_state


Lab 4
Question 3. What is the test coverage using -auto?
....................................................................................................
Question 4. What is the maximum sequential depth (use

report_summaries) for this design?
ng
....................................................................................................
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Question 5. Since this design contains memories, what can you conclude
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about the calculation of the sequential depth and what should
the minimum capture depth be for Fast-Sequetial ATPG?
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....................................................................................................
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....................................................................................................
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6. Try a limited Fast-Seq ATPG on the remaining undetected faults:
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TEST-T> set_atpg –capture_cycles 4 –abort 100
TEST-T> run_atpg fast_sequential_only -auto
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Question 6. How much did Fast-Sequential ATPG increase the coverage?
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.....................................................................................................
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Question 7. If a data path exists from one memory to another memory

what sequential depth should be used?
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Fo
....................................................................................................
....................................................................................................
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7. Enable historgram reporting

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TEST-T> set_patterns –histogram_summary

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TEST-T> report_summaries
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Question 8. How did enabling the histogram summary affect the summary
report?
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....................................................................................................
R


Lab 4
8. Improve the test coverage by giving Fast-Seq ATPG some more depth.
TEST-T> set_atpg –capture_cycles 8 –abort 1000

Question 9. What is the coverage now?
ng
....................................................................................................
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Question 10. What is the benefit of using the maximum sequential depth
for Fast-Sequential ATPG?
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....................................................................................................
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....................................................................................................
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9. Try the maximum Fast-Sequential depth:
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TEST-T> set_atpg –capture 10
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Question 11. What are the results after using the maximum Fast-Sequential
depth?
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....................................................................................................
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10. Try enabling the “new_capture” feature:

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When the –new_capture option is set, Fast-Sequential ATPG will more

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accurately simulate faults based on Leading Edge (LE) Trailing Edge (TE)
relationships between sequential elements.
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TEST-T> set_atpg –new_capture

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TEST-T> run_atpg fast_sequential_only –auto

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Question 12. What are the final Fast-Sequential results?

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....................................................................................................
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11. Try using Full-Sequential ATPG (this will take a bit longer):
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TEST-T> set_atpg –full_seq_atpg

TEST-T> run_atpg full_sequential_only -auto


Lab 4
Question 13. What are the final results on the sampled fault list?
....................................................................................................
12. Quit TetraMAX.
Task 2. Repeat on Complete Fault List
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1. Rerun the script on the complete fault list. A script has been provided for you.
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Note: There’s not enough time to run Full-Sequential ATPG on
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the full fault list, so compare results after Fast-Sequential.
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unix% vi full_faults.tcl
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unix% tmax –tcl –shell full_faults.tcl
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Question 14. How do the results on the complete fault list compare to the
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sampled fault list?
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....................................................................................................
Task 3. Compare to a TetraMAX II run

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1. Run ATPG with TetraMAX II and compare the script and the results to the
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previous run
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unix% vi run_tmax2.tcl
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unix% tmax2 –shell run_tmax2.tcl

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Question 15. How does the TetraMAX II script (tmax2_full_faults.tcl)

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compare to the regular TetraMAX script (full_faults.tcl)?

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....................................................................................................
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Question 16. How does the test coverage and pattern count compare?
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....................................................................................................
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You have completed the “Controlling ATPG” lab

es
of the TetraMAX Workshop.

R


Answers / Solutions
Task 1. Develop Initial ATPG Strategy

Question 1. What is the advantage of developing an ATPG strategy
using a sampled fault list?
ng
ATPG will run much quicker and you can complete a
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greater number of experiments in a given amount of time.
ai
Question 2. What is the starting test coverage?
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95.09% with 115 Basic-Scan Patterns.
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Question 3. What is the test coverage using -auto?
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95.02 % with 42 Basic-Scan Patterns.
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Question 4. What is the maximum sequential depth for this design?
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(use report_summaries sequential_depths)
lM
5 is the maximum reported detect depth.
The same information is also provided during run_drc:
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-----------------------------------------------------
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Begin DRC dependent learning...

nt
Fast-sequential depth results: control=4(32806),

observe=3(25117), detect=5(31872), CPU time=0.02 sec
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DRC dependent learning completed, CPU time=0.05 sec.

Fo
----------------------------------------------------
Question 5. Since this design contains memories, what can you conclude
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about the calculation of the sequential depth and what

should the minimum capture depth be for Fast-Sequential
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ATPG?
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Detecting address faults on memories usually requires 4

capture cycles (write to memory, write to memory, read
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from memory, capture to scan flip-flop) which should be the

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starting capture depth for Fast-Sequential ATPG for a

design with ATPG memory models. Notice that
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TetraMAX’s sequential depth calculation does not account

for memories.
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Question 6. How much did Fast-Sequential ATPG increase the

coverage?
95.67 % with 42 Basic-Scan and 6 Fast-Sequential Patterns.


Question 7. If a data path exists from one memory to another memory

what sequential depth should be used?
It depends. For a simple case of data read from one memory

being written directly into another memory you would need
5 capture cycles (write to memory one, read from memory
one, write to memory two, read from memory two, capture
ng
into a scan flip-flop). If memory address faults are being
targeted, it could be even higher.
ni
Question 8. How did enabling the histogram summary affect the
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summary report?
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The report now includes histogram information on the Fast-
Sequential patterns.
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#fast_sequential patterns 6
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# 2-cycle patterns 1
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# 1-load patterns
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Question 9. What is the coverage now?
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96.46% with 42 Basic-Scan and 10 Fast-Sequential patterns.

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Question 10. What is the benefit of using the maximum sequential depth
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for Fast-Sequential ATPG?

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Fast-Sequential ATPG runs much faster than Full-

Sequential ATPG. Running Fast-Sequential ATPG with its
maximum depth of 10 perhaps can detect multiple faults that
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only have a depth of 2, for example, between the time-

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consuming scan chain load_unload operations between one

test pattern and the next.
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Question 11. What are the results after using the maximum Fast-
Sequential depth?
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tri

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Question 12. What are the final Fast-Sequential results?

R


Question 13. What are the final results on the sampled fault list?
98.98% with 42 Basic-Scan 19 Fast-Sequential and 13 Full-

Sequential patterns.
Task 2. Repeat on Complete Fault List
ng
Question 14. How do the results on the complete fault list compare to the
sampled fault list?
ni
99.19% with 248 Basic-Scan and 291 Fast-Sequential
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patterns.
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Task 3. Compare to a TetraMAX II run
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Question 15. How does the TetraMAX II script (run_tmax2.tcl) compare
to the regular TetraMAX script (full_faults.tcl)?
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The TetraMAX II script doesn’t control any set_atpg
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settings other than -capture_cycles.
ic
Question 16. How does the test coverage and pattern count compare?
lM
After Fast-Sequential ATPG the coverage is higher and the
pattern count is lower with TetraMAX II.
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99.27% with 289 Basic-Scan and 224 Fast-Sequential
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patterns.
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Minimizing
5 ATPG Patterns
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Learning Objectives
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During this lab, you will generate a minimal set of stuck-at
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patterns for the ORCA design.
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 Describe how the dynamic pattern compression reduces

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the number of test patterns

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 Explain how clock grouping helps reduce the number

of Basic-Scan ATPG patterns
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 Describe how the minimum detected options can be

used to reduce the number of patterns
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Lab Duration
45 minutes
Minimizing ATPG Patterns Lab 5-1


Lab 5
Background
Test coverage is usually the primary metric of ATPG, but the number of patterns
required to achieve that coverage can be equally important. In terms of the amount
of ATE time allowed, it may even be a more important performance indicator. In
this lab, you will use a variety of techniques to reduce the test pattern size required
ng
for the ORCA design without dramatically affecting the test coverage achieved.
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Lab 5-2 Minimizing ATPG Patterns


Lab 5
Instructions
Answers / Solutions
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Task 1. Invoke TetraMAX and Determine Baseline
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Pattern Count
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1. Make sure your current working directory is lab5 _minimizing_atpg.
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unix% cd lab5_minimizing_atpg
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unix% tmax &
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3. Read the design netlist for the ORCA design.
lM
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4. Attempt to build the ATPG model for the ORCA design.

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BUILD-T> run_build_model ORCA

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5. Disable clock grouping.

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DRC-T> set_drc –clock –any

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Note: Recall that dynamic clock grouping is enabled by default.

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6. Peform the scan design rule checks.

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7. Run the Basic-Scan and Fast-Sequential ATPG engines to establish a baseline

pattern count which neither uses dynamic pattern merging nor dynamic clock
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grouping.
R

TEST-T> set_atpg –capture 8 –merge off
TEST-T> run_atpg


Lab 5
Question 1. What is the starting test coverage and pattern counts?
....................................................................................................
Task 2. Dynamic Pattern Compaction
1. Re-run ATPG with dynamic compaction enabled.
ng
Enable verbose reporting to see more information during ATPG.
ni
ai
TEST-T> reset_state
TEST-T> set_atpg -verbose
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TEST-T> set_atpg –merge high
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TEST-T> run_atpg
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Question 2. How do the test coverage and pattern count change?
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....................................................................................................
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Task 3. Dynamic Clock Grouping and -Auto lM
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1. Enable dynamic clock grouping and re-run ATPG using both dynamic pattern
compaction and dynamic clock grouping:
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TEST-T> drc -force

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DRC-T> set_drc -clock –dynamic -disturb

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DRC-T> run_drc
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TEST-T> add_faults -all

TEST-T> run_atpg
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Question 3. What is the test coverage and pattern counts using clock
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grouping?
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....................................................................................................
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2. Re-run ATPG simply with -auto.

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TEST-T> reset_state
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Lab 5
Question 4. What is the test coverage and pattern counts merely using
run_atpg -auto?
....................................................................................................
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Task 4. Reducing Patterns using Minimum Detect
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1. We’re going to start with the “full faults” script from the previous lab (single
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core) and use the minimum detection limits specified below.
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unix% vi task4.tcl
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. . .
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set_atpg –basic_min_det 10 \
–fast_min_det 5
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. . .
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unix% tmax –shell task4.tcl
Note:
lM
Recall that for runs with the full fault list, we are not
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running Full-Sequential ATPG, in the interests of time.
Compare results after Fast-Sequential.
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Question 5. How do the test coverage and pattern counts compare with
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the full fault list results of the previous lab?

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....................................................................................................
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Task 5. Reducing Patterns with –optimize_patterns

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1. Run a modified script from the previous lab to see how results compare when
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run_atpg –optimize_patterns is used.

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unix% tmax –shell .solutions/task5.tcl

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Question 6. How do the Basic-Scan test coverage and pattern counts

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compare when using –auto vs. –optimize_patterns?

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....................................................................................................
R


Lab 5
Task 6. Adaptive Scan ATPG
1. Perform “what-if” analysis for Scan Compression. A script called

“what_if.tcl” is provided for you to do this task. The script make three
runs of the analyze_compressors command. One with default x-tolerance
and two with high x-tolerance.
ng
unix% tmax what_if.tcl
ni
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Question 7. How do the analyze_compressor runs compare in terms
of test coverage, patterns, and estimated area overhead?
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....................................................................................................
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2. Optional: try some other configurations of analyze_compressors and see
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how much estimated compression you can achieve with sacrificing too much
test coverage.
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TEST-T> analyze_compressors –num_chains <d> \
lM
-num_inputs <d> -num_scanouts <d> \
-xtolerance [ default | high]
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3. View the adaptive_scan.tcl script in the lab5_minimizing_patterns directory:

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nt
unix% vi adaptive_scan.tcl
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Question 8. What is the main difference between this script and the one
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used in the previous tasks?
....................................................................................................
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4. Run the adaptive_scan.tcl script and look at the log file :

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unix% tmax –shell adaptive_scan.tcl

unix% vi adaptive_scan.log
ct
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Question 9. How many compressed scan chains are in the adaptive scan
mode? What is the longest chain length?
es
....................................................................................................
R


Lab 5
Question 10. Check the log when the STIL patterns are written. How many
test cycles are in the compression mode patterns?
....................................................................................................
5. Now run Tetramax using the internal_scan.tcl script. This generates patterns
for the reconfigured scan mode.
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unix% tmax -shell internal_scan.tcl
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unix% vi internal_scan.log
ai
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Question 11. How many “regular” scan chains are in the reconfigured scan
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....................................................................................................
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Question 12. Check the log when the STIL patterns are written. How many
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test cycles are in the internal scan mode patterns?
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....................................................................................................
6.
lM
Compare the ATPG results in compression mode vs. reconfigured scan mode.
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Question 13. Compare the test cycles between compression mode and
reconfigured scan mode. What is the effective compression
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ratio?
nt
....................................................................................................
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Question 14. How does test coverage and pattern count compare between
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scan-compression atpg and internal_scan atpg?

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....................................................................................................
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You have completed the “Minimizing ATPG

ed
Patterns” lab of the TetraMAX Workshop.

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tri
es
R


Answers / Solutions
Task 1. Enter TEST mode and Determine Baseline

Pattern Count
ng
Question 1. What is the starting test coverage and pattern counts?
ni
98.60% 744 Basic-Scan, 288 Fast-Sequential patterns
Task 2. Dynamic Pattern Compaction
ai
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Question 2. How do the test coverage and pattern count change?
ip
ch
Task 3. Dynamic Clock Grouping and -Auto
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Question 3. What is the test coverage and pattern counts using clock
grouping?
ic
lM
Significant reduction for Basic-Scan and since Dynamic
Clock grouping is a Basic-Scan option, no significant
change in Fast-Sequential patterns (slight increase).
na
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Question 4. What is the test coverage and pattern counts merely using
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run_atpg -auto?
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Task 4. Reducing Patterns using Minimum Detects

Question 5. How do the test coverage and pattern counts compare with
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the final results of the previous lab?

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There was a drop in coverage in the task4 run versus the

lab4 results (98.80% vs. 99.19%), but lab4 generated over
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2X the number of patterns (251 vs. 539).

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Task 5. Reducing Patterns with –optimize_patterns

tri
es
Question 6. How do the Basic-Scan test coverage and pattern counts

compare when using –auto vs.
R
–optimize_patterns?
Test coverage is pretty close (96.08% vs. 96.02%), but -

auto used more patterns than –optimize_patterns
(252 vs. 224).


Task 6. Adaptive Scan ATPG

Question 7. How do the two analyze_compressors runs compare in
terms of test coverage, patterns, and estimated area
overhead?
ng
analyze_compressors -num_chains 30 \
-num_inputs 5 -num_scanouts 5
ni
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test coverage 90.75%
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basic_scan patterns 354
Data reduction per pattern: 5.91X
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Cycle reduction per pattern: 5.91X
ch
Compressors area overhead per internal chain: 10.0
equivalent two-input NAND gates
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ic
lM
-num_inputs 5 -num_scanouts 5 –xtolerance high

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er

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Fo
The coverage with high xtolerance is slightly less because

an extra scan input is required to enable the xtolerance
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modes. This takes away a shared scanin input from the load
decompressor. To get an apples-to-apples comparison of the
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compression logic itself with and without high xtolerance,

an additional input would need to be accounted for.
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-num_inputs 6 -num_scanouts 5 –xtolerance high

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es

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With the added input for the xtolerance enable, high x-

tolerance gives better test coverage at the expense of some
additional area overhead.
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Question 8. What is the main difference between this script and the one
used in the previous tasks?
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It reads in the scan-compression netlist and uses the scan-
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compression STIL protocol file generated from DFT-
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Compiler:
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read_netlist ./design_data/ORCA_COMP_scan.v
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run_drc ./design_data/scancompress.spf
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ic
Question 9. How many compressed scan chains are in the adaptive scan
lM
Number of internal chains: 30, longest chain length: 98

na
You can find this information in “run_drc” report.
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Question 10. Check the log when the STIL patterns are written. How
many test cycles are in the compression mode patterns?
nt
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> write_patterns pats_comp.stil -format stil -replace

Patterns written reference 1045 V statements, generating 35149 test cycles
Fo
Question 11. How many “regular” scan chains are in the reconfigured
scan mode? What is the longest chain length?
se
Number of chains: 5, longest chain length: 585

U
Question 12. Check the log when the STIL patterns are written. How
many test cycles are in the internal scan mode patterns?
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> write_patterns pats_is.stil -format stil -replace

Patterns written reference 1039 V statements, generating 203103 test
ct
cycles
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Question 13. Compare the test cycles between compression mode and
es
reconfigured scan mode. What is the effective compression

ratio?
R
203103 / 35149 = 5.78X

Question 14. How does test coverage and pattern count compare between
scan-compression ATPG and internal_scan ATPG?
Adaptive_scan: 92.17% 347 patterns


Internal_scan: 92.60% 345 patterns

Adaptive-scan ATPG provided similar coverage and the
same number of patterns as regular scan. Default x-tolerance
was use in this case. If high x-tolerance was used, the test
coverage numbers would have been closer between regular
scan and adaptive scan.
ng
Coverage and pattern count for scan compression is almost
the same as regular scan. However, the number of scan
ni
cells per chain is significantly less, so the overall test-time
ai
will be greatly reduced for scan compression with minimal
impact on coverage.
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6 Pattern Validation
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Learning Objectives
ic
lM
During this lab, you will successfully save ATPG patterns
na
and TetraMAX reports to be used later during ATPG
pattern simulation and to transfer patterns to an ATE.
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nt
After completing this lab, you should be able to:

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 Save and restore TetraMAX session images

Fo
 Save ATPG patterns in a format suitable for later

simulation and application to ATE
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 Generate reports useful when troubleshooting ATPG

pattern simulation mismatches
U
 Simulate scan patterns with parallel load

ed
 View simulation signal in a Waveform viewer

ct
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es
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Lab Duration
45 minutes
Pattern Validation Lab 6-1


Lab 6
Background
Your goal is to handoff the results of ATPG. In prior labs you achieved the target
test coverage and test pattern count for the ORCA design. In preparation for later
test pattern validation you will save the test patterns in a simulation- and tester-
ready format. You will also save reports useful for test pattern simulation
ng
debugging. This lab emulates generating the patterns in one TetraMAX session and
saving the final patterns in separate session.
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Lab 6-2 Pattern Validation


Lab 6
Instructions
Answers / Solutions
ng
ni
Task 1. Save Patterns and Session Image after ATPG
ai
To save time a script, tmax_atpg.tcl, is provided which reads a saved ATPG
Tr
pattern set for the ORCA design.
ip
1. Make sure your current working directory is
lab6_pattern_validation.
ch
2. Edit the tmax_atpg.tcl file and add commands at the end of the script to:
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a. Quickly get back to TEST mode in a later session
ic
b. Save the test patterns in a format that can later be translated to any
c.
format lM
Ensure both files you save consume as little disk space as possible
na
3. Execute your atpg.tcl script.
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unix% cd lab6_pattern_validation
nt
unix% tmax –shell tmax_atpg.tcl

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Fo
Task 2. Restore Session and Generate Reports
A template for your tmax_handoff.tcl script is provided. Add the appropriate

se
commands as indicated in the steps below. You can try these commands
U
one-by-one interactively (in the tmax GUI), or if you are more comfortable, you can
verify that your script works in shell mode (tmax –shell).
ed
1. Restore your TetraMAX session from before by reading the image file.
ct
unix% tmax &

tri
BUILD-T> read_image ORCA.img.gz

es
R
Question 1. What TetraMAX mode are you now in (check the prompt in
shell mode or the TetraMAX GUI)?
....................................................................................................


Lab 6
Question 2. Are there any ATPG patterns associated with this session (use
report_patterns -summary)?
....................................................................................................
2. Read in the patterns generated by the tmax_atpg.tcl script.
ng
TEST-T> set_patterns -external ORCA.pats.gz
ni
3. Generate an external pattern summary report and answer the following
ai
questions.
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TEST-T> report_patterns -summary
ip
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Note: If you get a M130 message about “Unable to find pattern 0”,
use the option to report patterns that selects the external
ro
pattern set.
ic
Question 3. How many patterns were read in?
lM
....................................................................................................
na
Question 4. How many were Basic-Scan, Fast-Sequential and Full-
Sequential ATPG patterns?
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....................................................................................................
nt
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Question 5. When do patterns get stored in the internal buffer?

Fo
....................................................................................................
4. Save a report that documents which capture clocks are used by each test
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pattern. Redirect the report output to a pattern_detail.rpt file.

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TEST-T> report_ ... > pattern_detail.rpt

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Question 6. Which capture clock(s) are used in pattern one?

ct
....................................................................................................
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5. Save another report that helps translate TetraMAX scan chain names and scan
cell position to actual design netlist scan flip-flop instance names. Redirect
R
this report output to a scan_cell.rpt file.
TEST-T> redirect scan_cell.rpt {report_ ...}


Lab 6
Question 7. What is the name of the scan flip-flop in chain c4, position
317?
....................................................................................................
Task 3. Save Test Patterns
ng
Add the appropriate commands to the tmax_handoff.tcl script as indicated in
the steps below.
ni
ai
1. Write out patterns in a format that can be used for Verilog simulation. Write
the patterns to the “pattern” directory.
Tr
Question 8. What pattern format is used for Verilog simulation?
ip
ch
....................................................................................................
ro
Question 9. Do you need to write out separate pattern sets for parallel and
serial simulation of the patterns?
ic
lM
....................................................................................................
....................................................................................................
na
TEST-T> write_patterns ...

er
nt
2. Use the write_testbench command to create a Verilog testbench for

parallel simulation of the scan patterns:
rI
a. Write the testbench to the “pattern” directory.

Fo
b. Name the testbench as “pat_parallel_tb“.

se
Note: Specify that the default simulation mode for all these
patterns will be parallel load scan chain operation.
U
TEST-T> write_testbench ...

ed
ct
Question 10. What two files are written to the pattern directory when
tri
you ran the write_testbench command?

es
....................................................................................................
R
3. Use the write_testbench command to create a Verilog testbench for

serial simulation of a the scan patterns:
a. Write the testbench to the pattern directory.
b. Name the testbench as “pat_serial_tb“.


Lab 6
c. Specify an SDF file for back annotated simulation with the

–sdf_file parameter option. The location of the SDF file
from the “pattern” directory is:
../../design_data/orca_final.sdf
Note: Specify that the default simulation mode for this pattern will
be serial load scan chain operation.
ng
TEST-T> write_testbench ...
ni
ai
Task 4. Simulate Patterns in Parallel Mode
Tr
1. Change working directory to “pattern”.
ip
Source the file vcs_parallel. After simulation Verdi will be launched.
ch
unix% cd pattern
ro
unix% source vcs_parallel
ic
2. Look at the run_parallel.log file lM
Question 11. How many patterns were simulated?
na
....................................................................................................
er
Was the simulation successful?

nt
Question 12.
rI
....................................................................................................
Fo
Question 13. How many serial shifts (i.e. “N-shifts”) were used for the
simulation?
se
....................................................................................................
U
Question 14. How many ATE cycles were simulated?

ed
....................................................................................................
ct
tri
es
R


Lab 6
3. From the top tab click on “View  Signal List” to add the signals pane to the
Verdi GUI
ng
ni
ai
Tr
ip
ch
ro
ic
4.
lM
Make sure that “ORCA_test” is selected in the “Instance” pane. In the “Signal
List” pane (View -> Signal List), select the testbench signals of interest. You
na
should add “cur_pat”, “cur_StmtName[0:1599]”, and “nbfails”. Plus any other
signals of interest. When a signal(s) is selected, Right-Mouse-Click the signal
er
and then select “Add Signal(s) to Waveform”.

nt
rI
Fo
se
U
ed
ct
tri
es
R
You can also add signals from the nWave pane (Signal  Get Signals…).

Lab 6
5. Now use the nWave “Get Signals…” to select signal of interest from the “dut”
level. You should add the following signals: pclk, sdr_clk, sys_clk, prst_n,
scan_en, test_mode, and any other signals you are interested in.
ng
ni
ai
Tr
ip
ch
ro
ic
lM
na
Select to only show input signals in the signal list
6. Once all of the signals of interest have been added to the nWave waveform
er
viewer, you can change the order of the signal in nWave by selecting the
signal and then using Middle-Button-Click to drag the signal to a new postion.
nt
You will also need to chang the radix of the cur_StmtName[0:1599] signal to
rI
“ASCII” in order to see the statement names.

Fo
se
U
ed
ct
tri
es
R


Lab 6
7. Explore the nWave waveform viewer.

Try zomming in/out. Note the simulation behavior with regard to the cur_pat
number, scan_en, and curStmtName. Notice the scan capture cycle and the
clocks that pulse during capture for a given pattern.
8. Save the current session so that it can be recalled later. From the Verdi menu,
select FileSave Session… . Save the session to a .ses file of you choice. The
ng
session can be restored later with FileRestore Session… .
Alternately, you can choose to save only signals displayed in the waveform
ni
viewer. From the nWave menu, select FileSave Signal… . Save the signals
ai
to a .rc file of you choice. The signals shown can be restored in a later session
Tr
with FileRestore Signal… (from the nWave menu).
Task 5. Simulate Patterns in Serial Mode
ip
ch
1. Source the file vcs_serial. After simulation, Verdi will be launched.
ro
unix% source vcs_serial
ic
2. Look at the run_serial.log simulation log
Question 15.
lM
How many patterns were simulated?
na
....................................................................................................
er
Question 16. Was the simulation successful?

nt
....................................................................................................
rI
Fo
Question 17. How can you confirm that a serial simulation was performed?
....................................................................................................
se

U
....................................................................................................
ed
3. Follow the same steps from the previous task or restore the session/signals to
ct
view the waveforms.

tri
4. Exit all the tools.

es
You have completed the “Pattern Validation” lab

R


Answers / Solutions
Task 2. Restore Session and Generate Reports

Question 1. What TetraMAX mode are you now in (check the prompt in
the shell mode or the TetraMAX GUI)?
ng
You should now be in TEST mode after restoring a session
ni
image saved while you were previously in TEST mode.
ai
Question 2. Are there any ATPG patterns associated with this session
Tr
(use report_patterns -summary)?
ip
No patterns have been saved as part of the image.
ch
Question 3. How many patterns were read in?
When the patterns are read, the number of patterns read is
ro
reported:
ic
End reading 150 patterns, CPU_time = 0.01 sec, Memory = 0MB
lM
Also, report_patterns –summary indicates that 150
patterns are in the external pattern set.
na
Question 4. How many were basic scan, fast seq and full seq ATPG
patterns?
er
report_patterns –summary reports 100, 50 and 0

nt
basic, fast and full seq ATPG patterns respectively. The

rI
same info can be obtained from report_summaries.

Fo
Question 5. When do patterns get stored in the internal buffer?
Usually patterns are saved into the internal pattern set

se
during run_atpg.
U
Question 6. Which capture clock(s) are used in pattern one?

ed
This information is contained in the report_patterns

–all –external –type report. sdr_clk, sys_clk, pclk
ct
are all pulsed during the capture cycle for test pattern
number one. The comma-separate list means TetraMAX
tri
dynamically grouped these clocks for that pattern.

es
Question 7. What is the name of the scan flip-flop in chain c4, position
317?
R
report_scan_cells –all shows that chain c4,

position 317 correspond to the design flip-flop
I_ORCA_TOP/I_RESET_BLOCK/prst_ff_reg


Task 3. Save Test Patterns

Question 8. What pattern format is used for Verilog simulation?
The STIL pattern format is used for Verilog simulation, i.e.,

“-format stil”.
ng
Question 9. Do you need to write out separate pattern sets for parallel
and serial simulation of the patterns?
ni
No. Only a single pattern set needs to be written. Parallel vs.
ai
serial simulation can be determined when translating the
Tr
pattern to a Verilog testbench or during simulation runtime.
write_pattern pattern/pat.stil -external -format stil -replace
ip
write_testbench -input ./pattern/pat.stil \
-output ./pattern/pat_parallel_tb \
ch
-parameter {-parallel -replace -log pat_parallel_tb.log}
ro
Question 10. What two files are written to the pattern directory when
you ran the write_testbench command?
ic
lM
The instructions were to name the testbench pat_parallel_tb
when running write_testbench. Therefore, the two files that
will be created in the pattern directory are:
na
pat_parallel_tb.v (testbench) and
pat_parallel_tb.dat (datafile).
er
write_testbench -input ./pattern/pat.stil \

nt
-output ./pattern/pat_serial_tb \
-parameter {-serial -replace -log pat_serial_tb.log \
rI
-sdf_file ../../design_data/orca_final.sdf}
Fo
Task 4. Simulate Patterns in Parallel Mode

se
150 patterns.
U
XTB: Starting parallel simulation of 150 patterns

ed

ct
Yes.
tri
XTB: Simulation of 150 patterns completed with 0

errors
es
Question 13. How many serial shifts (i.e. “N-shifts”) were used for the
simulation?
R
0 serial shifts. From the simulation logfile:

XTB: Using 0 serial shifts


375.
XTB: Simulation of 150 patterns completed with 0 errors (time: 37500.00
ns, cycles: 375)
Task 5. Simulate Patterns in Serial Mode
ng
ni
11 patterns. In the simulation script. the
ai
+define+tmax_n_pattern_sim=10 run time option
Tr
was used to limit the number of patterns simulated. This
specified that that last pattern to be simulated is pattern 10.
Patterns are numbered from 0, so 11 total patterns are
ip
simulated. This is reflected in the simulation logfile
ch
XTB: Total number of patterns 150
ro
XTB: Setting compile-time option "tmax_n_pattern_sim" to 10.
XTB: User requesting simulating patterns 0 to 10
ic
XTB: Setting compile-time option "tmax_msg" to 1.
XTB: Starting serial simulation of 11 patterns lM
na
Yes.
er
XTB: Simulation of 11 patterns completed with 0

nt
errors
rI
Question 17. How can you confirm that a serial simulation was
performed?
Fo
From the logfile you can see that serial simulation was
performed:
se
XTB: Starting serial simulation of 11 patterns

U
XTB: Begin serial scan load for pattern 0 (T=100.00 ns, V=2)
ed
ct
Also by looking at the waves, you can confirm that every

scan shift cycle was simulated.
tri

es
5380. Since we are simulated every serial shift, there are

R
many more ATE cycles simulated even though only a

fraction of the patterns were simulated.
XTB: Simulation of 11 patterns completed with 0 errors (time: 538000.00
ns, cycles: 5380)


8 Power-Aware ATPG
ng
ni
ai
Tr
ip
Learning Objectives
ch
ro
In this lab, you will invoke TetraMAX and use the Power-
ic
Aware ATPG feature.
lM
 Reduce switching activity during scan shift
na
 Limit switching activity during scan capture by setting a
er
switching budget
nt
 Report the actual switching activity after ATPG on a per

pattern basis
rI
Fo
se
U
ed
ct
tri
es
Lab Duration:
20 minutes
R
Power-Aware ATPG Lab 8-1


Lab 8
Background
By default, ATPG will generate patterns that exercise as much of the design as
possible in order to reduce overall pattern count. Since ATPG can direct control
over the clocks that will pulse during ATPG, it’s likely that the switching activity
ng
during scan testing will be much greater than the expected functional (“mission
mode”) switching activity. The greater switching activity can draw more power than
ni
the design is able to provide. This is especially true when generating scan patterns
ai
that are intended to be run At-Speed.
Tr
Your goal is to use TetraMAX to evaluate the switching activity and then use
Power-Aware ATPG to limit the switching activity during scan capture and scan
ip
shift.
ch
ro
ic
lM
na
er
nt
rI
Fo
se
U
ed
ct
tri
es
R
Lab 8-2 Power-Aware ATPG


Lab 8
Instructions
Answers / Solutions
ng
ni
Task 1. Evaluate switching activity in TetraMAX
ai
Tr
1. Make sure your current working directory is lab8_power_aware.
ip
2. Start the TetraMAX GUI and run the power_aware.tcl script.
ch
unix% cd lab8_power_aware
ro
unix% tmax power_aware.tcl &
ic
3. Determine a switching activity budget.
Question 1. lM
What components of a design can TetraMAX use in order to
reduce switching activing during scan capture?
na
...................................................................................................
er
Question 2. What command can be used after run_drc to report details

nt
of the design’s clocking to determine limits of switching

rI
activity reduction during Power-Aware ATPG?

Fo
...................................................................................................
4. Run the report.

se
U
report_* ...
ed
Question 3. Analyze the generated report. What is reported as the

Minimum Recommended Low-Power ATPG Budget?
ct
tri
...................................................................................................
es
Question 4. Is it advisable to use the minimum budget as the Power-

Aware budget during ATPG?
R
...................................................................................................


Lab 8
5. Run the following commands to generate a baseline set of Transition Delay

ATPG patterns for this design:
add_faults -all
run_atpg -auto
ng
6. Note the number of pattens and the Test Coverage for the baseline run.
ni
7. Analyze the switching activity of the generated pattern
ai
Question 5. What command can be used to report a summary of the
Tr
ATPG pattern switching activity as a percentage?
ip
...................................................................................................
ch
8. Run the report.
ro
report_* ...
ic
Question 6.
lM
Which pattern has the highest peak switching activity and
what is the percent switching activity for that pattern?
na
...................................................................................................
er
Task 2. Reduce switching activity during scan capture

nt
In this task you will use Power-Aware ATPG to reduce the switching activity during
rI
At-Speeed scan capture.

Fo
Question 7. What command can be used to set a Power-Aware ATPG

switching activity budget for scan capture?
se
...................................................................................................
U
1. Reset the current ATPG patterns and set a capture budget of 30%:
ed
reset_state
ct
set_atpg ...
tri
es
2. Re-run ATPG and report the switching activity for the new pattern set:
R
run_atpg -auto
report_power -percentage
Note: To report the switching activity on a per pattern basis, you

can add the -per_pattern command option

Lab 8
Question 8. Was the peak capture swiching activity reduced from the
earlier baseline ATPG run?
...................................................................................................
Question 9. Is the peak switching activity during capture at or below the
ng
switching activity budget that was set?
ni
...................................................................................................
ai
3. Reset the current ATPG patterns and increase the power effort:
Tr
reset_state
ip
set_atpg -power_effort high
ch
run_atpg -auto
ro
ic
Question 10. Is the peak capture switching activity for this new ATPG run
lM
below the budget that was set?
na
...................................................................................................
er
4. Compare the number of patterns and the Test Coverage to the baseline
values you noted earlier:
nt
Question 11. Did the number of patterns and/or the Test Coverage change
rI
after Power-Aware ATPG was enabled?

Fo
...................................................................................................
Task 3. Reduce switching activity during scan shift

se
U
In this task you will use Power-Aware ATPG to reduce the switching activity during
scan shift.
ed
Question 12. What is the peak and average switching activity reported for
ct
scan shift?
tri
...................................................................................................
es
By default, ATPG will “fill” non care bits with random values by loaded random
R
values in those cells. Try to lower the switching activity during scan shift by instead
filling the non care bits with the same value as the next adjacent care bit


Lab 8
1. Reset the current ATPG patterns and enable adjacent fill
reset_state
set_atpg -power_effort high
run_atpg -auto
ng
ni
ai
Question 13. Did adjacent fill lower the peak and average switching
activity during scan shift? What are the values now?
Tr
...................................................................................................
ip
2. You can set a switching activity budget for scan shift as well. Set a switching
ch
activity budget of 40% and re-run ATPG.
ro
reset_state
ic
set_atpg -shift_power_budget 40
run_atpg -auto lM
na
er
Question 14. Was the shift power budget met?

nt
...................................................................................................
rI
In many cases, the chain test patterns have the highest switching activity depending
Fo
on the load pattern sequence used for the chain test (default is repeating 0011). If the
chain test patterns exceed the power budget (which is not an issue for the design
used in this lab), then “quiet” chain test patterns can be generated. When quiet chain
se
test patterns are enabled, ATPG will create multiple chain test patterns where only
one of the scan channels is active in a given pattern.
U
3. Note the switching activity during shift for the first 10 scan patterns. The
ed
chain test pattern is pattern 0:

ct
report_power -last 10 -shift -per_pattern -percentage

tri
es
R


Lab 8
4. Reset the patterns and lower the switching activity during shift for the chain
test patterns by enabling quiet chain test patterns.
reset_state
set_atpg -quiet_chain_test
ng
run_atpg -auto
ni
report_power -last 10 -shift -per_pattern -percentage
ai
Tr
Question 15. The chain test patterns are now patterns 0 – 6 (pattern 0 pre-
loads all 0’s). Is the switching activity during scan shift lower
ip
with the quiet chain test patterns?
ch
...................................................................................................
ro
ic
You have completed the “Power-Aware ATPG”
lab of the TetraMAX Workshop.
lM
na
er
nt
rI
Fo
se
U
ed
ct
tri
es
R


Answers / Solutions
Task 1. Evaluate switching activity in TetraMAX
ng
Question 1. What components of a design can TetraMAX use in order to
reduce switching activing during scan capture?
ni
Power-Aware ATPG uses the existing functional clock
ai
gating cells to limit switching activity during scan capture
Tr
Question 2. What command can be used after run_drc to report
ip
details of the design’s clocking to determine limits of
ch
switching activity reduction during Power-Aware ATPG?
ro
report_clocks -gating
ic
Question 3.
lM
Analyze the generated report. What is reported as the
Minimum Recommended Low-Power ATPG Budget?
na
Minimum Recommended Low-Power ATPG Budget: 22.97% (164)
er
Question 4. Is it advisable to use the minimum budget as the Power-

nt
Aware budget during ATPG?

rI
No. The reported value is the minimum switching activity

Fo
that can be achieved by the design. Using this value as the

Power-Aware ATPG budget could have an adverse effect on
pattern count and potentially Test Coverage as well.
se
U
Question 5. What command can be used to report a summary of the

ATPG pattern switching activity as a percentage?
ed
ct
tri
Question 6. Which pattern has the highest peak switching activity and
es
what is the percent switching activity for that pattern?

R
Pattern 2. From the report_power -percentage

report:
Peak Shift Switching 575 80.53% (pattern: 2 cycle: 1)
Peak Capture Switching 413 57.84% (pattern: 2)


Task 2. Reduce switching activity during scan capture

Question 7. What command can be used to set a Power-Aware ATPG
switching activity budget for scan capture?
ng
set_atpg -power_budget <n>
ni
ai
Question 8. Was the peak capture switching activity reduced from the
Tr
earlier baseline ATPG run?
ip
Yes. Average switching activity and peak switching activity
is reduced.
ch
Average Shift Switching 386.30 54.10%
Average Capture Switching 53.30 7.47%
ro
ic
Question 9.
lM
Is the peak switching activity during capture at or below
the switching activity budget that was set?
na
No. The budget was set at 30%. The peak switching activity
er
during capture is 33.33%

nt
rI
Question 10. Is the peak capture switching activity for this new ATPG
run below the budget that was set?
Fo
Yes.
se
Note the M834 messages during ATPG. This indicates that

U
ATPG generated a pattern to detect a fault that didn’t meet

the power budget with -power_effort high. This can
ed
cause a drop in Test Coverage.

ct
1 patterns were rejected for exceeding Capture Power during simulation

interval (M834).
tri
es
Question 11. Did the number of patterns and/or the Test Coverage change
after Power-Aware ATPG was enabled?
R
Yes. There are ~50% more patterns. The Test Coverage is

slightly lower than the baseline.


Task 3. Reduce switching activity during scan shift

Question 12. What is the peak and average switching activity reported for
scan shift?
ng
ni
ai
Question 13. Did adjacent fill lower the peak and average switching
activity during scan shift? What are the values now?
Tr
Yes. The shift switching activity values are lower with
ip
adjacent fill enabled.
ch
ro
ic
Question 14. Was the shift power budget met?
lM
Yes. The peak shift switching activity is now below 40%.
na
er
Question 15. The chain test patterns are now patterns 0 – 6 (pattern 0 pre-
nt
loads all 0’s). Is the switching activity during scan shift

lower with the quiet chain test patterns?
rI
Yes. The switching activity for the chain test patterns is

Fo
much lower with quiet chain test patterns enabled.

se
U
ed
ct
tri
es
R


Transition Delay
9 ATPG
ng
ni
ai
Tr
ip
Learning Objectives
ch
ro
In this lab, you will run TetraMAX to perform ATPG for
ic
the Transition fault model. Also, you will simulate the
lM
patterns in VCS to see the at-speed launch and capture
clocks.
na
 Set the correct SPF and fault model needed for
er
Transition ATPG.
nt
 Describe the difference in the fault list for stuck-at and

rI
Transition ATPG
 List some extra constraints needed for Transition ATPG.
Fo
 Generate and save the patterns for Transition ATPG

using both the Last shift launch and System clock
se
launch.
U
 Simulate the patterns in VCS to see the at-speed launch

and capture pulses.
ed
 Run PrimeTime to generate slack data for Slack-Based

ct
ATPG
 Setup ATPG for Slack-Based Transition Delay testing
tri
es
Lab Duration:
45 minutes
R
Transition Delay ATPG Lab 9-1


Lab 9
Introduction
Objective
In this lab, the focus will be on Transition ATPG. You will not be targeting for high
ng
test coverage. You will generate a few patterns for both the “Last Shift” and
“System Clock” launch methods using external clock sources. The intention here is
ni
to see the at-speed clocks when the patterns are simulated in VCS.
ai
Then Slack-Based Transition Delay testing will be explored including the
Tr
generation of the slack data from PrimeTime.
ip
ch
ro
ic
lM
na
er
nt
rI
Fo
se
U
ed
ct
tri
es
R
Lab 9-2 Transition Delay ATPG


Lab 9
Instructions
Answers / Solutions
ng
ni
Task 1. Invoke TetraMAX, read the design, and Run
ai
DRC checks
Tr
In this task, you will invoke TetraMAX and read the design and Run DRC.
ip
ch
1. Make sure your current working directory is lab9 _transition_delay.
2. Use the provided script to invoke TetraMAX and run through the
ro
run_build_model step.
ic
unix% cd lab9_transition_delay
unix% tmax tmax_transition_delay.tcl
lM
na
3. The timing exceptions generated in PrimeTime do not set the false path
er
between the clock domains.

nt
Question 1. What command should be used to constrain the tool to use a

common launch and capture clock ?
rI
...................................................................................................
Fo
DRC-T> set_delay ………………

se
U
4. Constrain the reset and the scan enable.

Question 2. You will constrain reset and scan enable to what values?
ed
...................................................................................................
ct
tri
DRC-T> add_pi_constraint ……… prst_n

es
DRC-T> add_pi_constraint ………… scan_en

R
5. Read the SDC file “orca_scan_user_violation_exceptions.sdc”.
DRC-T> read_sdc \
orca_scan_user_violation_exceptions.sdc


Lab 9
6. Run drc.
DRC-T> run_drc -patternexec ScanCompression_mode_occ_bypass
Question 3. How many nonscan flip flops are there in the design?
ng
...................................................................................................
ni
Question 4. How many scan chains are there and what is the maximum
ai
chain length?
Tr
...................................................................................................
ip
Question 5. Are there any capture violations?
ch
...................................................................................................
ro
Note: You should be in TEST mode, once you have given the
ic
“run_drc” command.
Task 2. Run ATPG

lM
na
1. In this task, you will set up ATPG for Transition fault model and then
generate 10 patterns of each kind of launch technique.
er
Question 6. What is the default fault model in TetraMAX?

nt
rI
...................................................................................................
Fo
Question 7. What is the default launch type for At-Speed fault models?
...................................................................................................
se
Note: At any point in the flow you can use the command
U
“report_setting” to see the default or the current

settings of any command.
ed
2. Set the fault model to Transition and launch type to last shift launch.
ct
tri
TEST-T> set_fault –model transition

es
TEST-T> set_delay –launch_cycle last_shift

R
3. Add the faults.


Lab 9
Question 8. How many faults have been added?
...................................................................................................
Question 9. Is the fault list of Stuck-At and Transition Delay fault models
the same?
ng
...................................................................................................
ni
Transition Delay fault model by default does not add faults on
ai
Question 10.
what signals?
Tr
...................................................................................................
ip
...................................................................................................
ch
4. Constrain ATPG to generate only 10 patterns.
ro
TEST-T> set_atpg –pattern 10
ic
5. Run atpg lM
na
er
Question 11. What warning messages are you getting ?

nt
...................................................................................................
rI
Question 12. What type of patterns have been generated ?

Fo
...................................................................................................
se
Use the command report_pattern to see what clocks have been used to
U
capture the faults

ed
TEST-T> report_pattern –type –all

ct
Question 13. Are there multiple capture clocks per pattern?

tri
es
...................................................................................................
R
6. Generate the system clock launch pattern.
TEST-T> set_delay –launch_cycle system_clock



Lab 9
Question 14. Are there any new patterns generated ? Why ?
...................................................................................................
7. Increase the pattern limit to 25 and then generate the patterns.
ng
TEST-T> set_atpg –pattern 25
ni
ai
Question 15. What type of patterns are generated now?
Tr
...................................................................................................
ip
Question 16. Are there multiple capture clocks in the new patterns
ch
generated?
ro
...................................................................................................
ic
TEST-T> report_pattern lM
–type –all
na
Question 17. Are there any inter-clock domain patterns generated ?
er
...................................................................................................
nt
Task 3. Save the patterns

rI
To save the patterns and generate the testbenches for simulation, source a prepared
Fo
script.
1. In the TetraMAX session, source the tmax_write_patterns.tcl script.

se
U
TEST-T> source –e tmax_write_patterns.tcl

ed
Task 4. Simulate patterns in VCS in Parallel mode

ct

tri
Source the file vcs_tran_parallel. After simulation, nWave will be

es
launched in order to view the waveforms.

R
unix% source vcs_tran_parallel
2. To save time, a signal list is provide that can be restored in nWave. Select
FileRestore Signal… and select the “tran_signals.rc” file.


Lab 9
ng
ni
ai
Tr
ip
ch
ro
ic
lM
na
er
3. Additional signals of interest can be added to the nWave waveform viewer.

nt
4. Take a look at the simulated waveforms to see the At-Speed clocks in both the
rI
last shift launch and system clock launch patterns.

Fo
Task 5. Simulating Patterns in VCS in Serial mode

(Optional)
se
1. Source the file vcs_tran_serial. After simulation, nWave will be

U

ed
unix% source vcs_tran_serial

ct
2. Follow the same steps from the previous task again to view the waves
tri

es
R


Lab 9
Task 6. Generate the Slack Data for Slack-Based ATPG
In this Task, you will invoke PrimTime and generate the slack data to be used
during Slack-Based ATPG. The pt_slack.tcl script is already constrained to be
used for At-Speed ATPG.
ng
1. Return to the lab9_transition directory
ni
uxix% cd ..
ai
Tr
Question 18. What is the command to report slack data on each pin?
ip
……………………………………………………………
ch
2. Update the pt_slack.tcl script to redirect the output of the above
command to file orca_scan_comp_mode_occ_bypass.slack (let
ro
this be last command before exit)
ic
report_global_slack >
orca_scan_comp_mode_occ_bypass.slack lM
na
3. Run PrimeTime to generate the slack data.
er
pt_shell –f pt_slack.tcl | tee pt.log

nt
rI
4. Exit PrimeTime.
Fo
Task 7. Run Slack-Based ATPG

se
In this task, you will set up ATPG for Slack-Based Transition Delay testing.
1. Use the provided script to invoke TetraMAX and run through the run_drc
U
step.
ed
unix% tmax tmax_slack_based_td.tcl

ct
tri
Question 19. Is there any change required in the Transition SPF file for
Slack-Based ATPG?
es
… ...............................................................................................
R


Lab 9
2. Define Transition fault model and setup for “system clock” launch
TEST-T> set_faults –model transition

TEST-T> set_delay –launch_cycle system_clock
ng
3. Constrain ATPG to generate 20 patterns.
ni
TEST-T> set_atpg –patterns 20
ai
Tr
Question 20. If you run ATPG at this step will it perform Slack-Based
ATPG?
ip
...................................................................................................
ch
Question 21. What is the command to read the slack timing data ?
ro
...................................................................................................
ic
4. Read the slack timing data into TetraMAX
lM
TEST-T> read_....
na
er
5. Max Tmgn and Delta for ATPG

Question 22. What is the default value of max_tmgn and Delta? How
nt
does it effect the quality and number of patterns?

rI
...................................................................................................
Fo
6. Set the max_tmgn to 30%

se
TEST-T> set_delay –max_tmgn 30%

U
Question 23. Can the faults with tmgn more than max_tmgn have a DS
ed
classification?
ct
… ...............................................................................................
tri
7. Run ATPG
es

R
Question 24. What is absolute value of max_tmgn calculated by

TetraMAX ?
-------------------------------------------------------------------------- .


Lab 9
Task 8. Reports of Slack-Based Run
1. Take a report on the following fault “ Slow to rise :

I_ORCA_TOP/I_PCI_TOP/I_PCI_CORE/mult_43_L01109_C240_I49/U13/A”
ng
TEST-T> report_faults \
I_ORCA_TOP/I_PCI_TOP/I_PCI_CORE/U965/Z -slow r
ni
Question 25. What is the tmgn and delta for this fault?
ai
Tr
… ...............................................................................................
ip
TEST-T> report_faults –slack delta 1.0
ch
Question 26. How many faults have deltas between “3.00 and 4.00”?
ro
… ...............................................................................................
ic
2. Report on fault “report_fault lM
I_ORCA_TOP/I_CONTEXT_MEM/CONTEXT_RAM_0/A1[0] –slow
na
er
I_ORCA_TOP/I_CONTEXT_MEM/CONTEXT_RAM_0/A1[0] –slow r
nt
rI
...................................................................................................
Fo
Question 28. Why does the fault not have a delta value?
se
.. .................................................................................................
U
3. Report on fault “I_ORCA_TOP/I_PARSER/pci_w_mux_select_reg_0_/D”

ed
I_ORCA_TOP/I_PARSER/pci_w_mux_select_reg_0_/D –slow f
ct
tri
es
R
.. .................................................................................................
Question 30. Can you explain the reason for the tmgn value?
.. .................................................................................................


Lab 9
Task 9. Simulate Patterns in VCS (Optional)
The pattern simulation will be exactly the same as for the standard Transition Fault
model. If time permits simulate the patterns.
1. In the TetraMAX session, source the tmax_write_patterns.tcl script.
ng
ni
ai
Tr
3. Source the file vcs_trans_parallel. After simulation, nWave will be
ip
ch
unix% cd pattern
ro
unix% source vcs_trans_parallel
ic
4. Select/Restore waveform signals of interest in nWave as desired in the same
5. Exit all tools.

lM
way that was done for regular Transition Delay.
na
er
You have completed the “Transition Delay ATPG”

nt
lab of the TetraMAX Workshop.

rI
Fo
se
U
ed
ct
tri
es
R


Answers / Solutions
Task 1. Invoke TetraMAX, read the design, and Run

DRC checks
ng
Question 1. What command should be used to constrain the tool to use a
ni
common launch and capture clock?
ai
set_delay –common_launch_capture_clock
Tr
Question 2. You will constrain reset and scan enable to what values?
ip
add_pi_constraints 1 prst_n
add_pi_constraints 0 scan_en
ch
Question 3. How many nonscan flip flops are there in the design?
ro
37
ic
Question 4. How many scan chains are there and what is the maximum
chain length? lM
na
96 Chains, Maximum cells 78
er
Question 5. Are there any capture violations?

nt
Yes, C6, C12, C13, C16, C17 and C21

rI
Fo
Task 2. Run ATPG

se
Question 6. What is the default fault model in TetraMAX?

U
Stuck-At is the default fault model.

Question 7. What is the default launch type for At-Speed fault models?
ed
The default launch type is “system_clock”.

ct
Question 8. How many faults have been added?

tri
241576
es
Question 9. Is the fault list of Stuck-At and Transition Delay fault

R
models the same?
No.


Question 10. Transition Delay fault model by default does not add faults
on what signals?
The transition fault model does not add faults on the clocks
ng
and the ScanEnable signals.
Question 11. What warning messages are you getting?
ni
M495: Warning: Merging and pattern limits enabled without basic-scan
ai
minimum detections per pattern.
Tr
Warning: 605 shifts of 9 patterns used X tolerance modes during simulation
interval. (M659)
ip
Warning: ATPG terminated due to meeting pattern count limit. (M234)
ch
Note: you may notice that 15 patterns were generated
instead of the requested 10. The extra patterns are “padding
ro
patterns” that are sometimes added when generating patterns
in compression mode. The padding patterns don’t pulse
ic
clocks during capture. Their purpose is to ensure that the
lM
previous pattern can be observed through the compressor
when unloaded.
na
Question 12. What types of patterns have been generated?
er
Basic-Scan patterns. Last shift launch uses the Basic-Scan

ATPG engine to generate the patterns.
nt
Question 13. Are there multiple capture clocks per pattern?

rI
Yes, there are multiple capture clocks in most of the

Fo
patterns. Again, the patterns that don’t pulse any clocks are
compression mode padding patterns (or chain test patterns).
se
Question 14. Are there any new patterns generated? Why?

U
NO, since the pattern limit is still 10 patterns.

Question 15. What types of patterns are generated now?
ed
Fast-Sequential patterns have been generated.

ct
Question 16. Are there multiple capture clocks in the new patterns
tri
generated?
es
Yes, there are multiple capture clocks in most of the

patterns. Use command “report pattern –type –
R
all”.


Question 17. Are there any inter-clock domain patterns generated?
Can’t tell from just reporting the patterns but there shouldn’t
be since “set_delay -common_launch_capture”
was specified earlier in the script. Multiple capture clocks
are pulsed in most patterns which could exercise inter-clock
ng
domain paths depending on how the clock domains interact.
However, TetraMAX will manage this by masking any
ni
inter-clock domain paths as part of disturb clock grouping.
ai
Task 6. Generate the Slack Data for Slack-Based ATPG
Tr
Question 18. What is the command to report slack data on each pin?
ip
report_global_slack
ch
Task 7. Run Slack-Based ATPG
ro
Question 19. Is there any change required in the Transition SPF file for
ic
Slack-Based ATPG?
lM
No, there is no change needed for the SPF file. The same
SPF file used for regular Transition Delay ATPG can be
na
used for Slack-Based ATPG.
Question 20. If you run ATPG at this step will it perform Slack-Based
er
based ATPG?
nt
NO, as the slack data has not been read yet.

rI
Question 21. What is the command to read the slack timing data?
Fo
read_timing
read_timing orca_scan_comp_mode_occ_bypass.slack
se
Question 22. What is the default value of max_tmgn and Delta? How
U
does it affect the quality and number of patterns?

ed
The default value for max_tmgn is “infinity”.

Higher the value of max_tmgn, the better is the quality of
ct
the patterns.
tri
As the value of max_tmgn is raised, the number of patterns

es
generated increases and the ATPG runtime also increases.

R
The default value for delta is 0.

The higher the value of delta, the lower will be the number
of patterns.


As the value of delta is increased, the quality of the patterns

decreases.
Question 23. Can the faults with tmgn more than max_tmgn have a DS
classification?
ng
No. If detected, those faults will be classified as TP.
Question 24. What is the absolute value of max_tmgn calculated by
ni
TetraMAX?
ai
Tr
The max tmgn for small delay defect faults has been set to 6.0400
Task 8. Reports of Slack-Based Run
ip
ch
ro
str TP I_ORCA_TOP/I_PCI_TOP/I_PCI_CORE/U965/Z 14.4900 0.5400
ic
Tmgn = 14.49 Delta = 0.54
lM
Note that the fault is TP because the tmgn value is higher
than max_tmgn.
na
Question 26. How many faults have deltas between “3.00 and 4.00”?
804
er
nt
rI
Tmgn = 9.52 Delta = “undefined”

str AN I_ORCA_TOP/I_CONTEXT_MEM/CONTEXT_RAM_0/A1[0] 9.52
Fo
Question 28. Why does the fault not have any delta value?
se
This fault is not detected so it does not have a delta value.

U
Tmgn = 9.52 Delta = “undefined”

ed
stf NO I_ORCA_TOP/I_PARSER/pci_w_mux_select_reg_0_/D Inf

ct
Question 30. Can you explain the reason for the tmgn value?
tri
es
The fault shows a tmgn of “Inf” (i.e. “infinite”) because

there is a timing exception (set_false_path) on that pin in
R
PrimeTime.


ng
ni
ai
Tr
ip
ch
ro
ic
lM
na
er
nt
rI
Fo
se
U
ed
ct
tri
es
R


l5
10 Using On-Chip Clocks

for Transition Delay
ng
ni
ai
Tr
ip
Learning Objectives
ch
ro
In this lab, you will invoke TetraMAX to perform ATPG
ic
using PLL clocks. In capture mode the fast clocks from the
lM
PLL will be used to launch and capture the faults. Also,
you will simulate the patterns in VCS to see the at-speed
launch and capture clocks.
na
er
 List commands needed to control the number of ATE

nt
and Capture clocks during the capture mode.

rI
 Generate and save the patterns for Transition ATPG for

system clock launch.
Fo
 Simulate the pattern in VCS to see the at-speed launch

and capture pulses.
se
 Optional task: Use QuickSTIL to define the clocks in

PLL flow and edit the SPF file to suit the OCC
U
requirements.
ed
ct
tri
es
Lab Duration:
30 minutes
R
Transition ATPG using PLL clocks Lab 10-1


Lab 10
Background
In this lab, you will perform Transition ATPG on the given design with internal
generated clocks from a PLL using OCC. At-speed launch and capture clocks are
provided by the PLL, instead of the top level external clock sources.
ng
Your goal is to take the netlist and generate 30 patterns using system clock launch
ni
where the at-speed clocks come from PLL. After generating these patterns, simulate
ai
the patterns in VCS and view the at-speed launch and capture pulses.
Tr
DFT Compiler/DFTMAX can generate the SPF which has the necessary constructs
to run ATPG using PLL clocks with OCC. The main part of this lab uses the SPF
ip
from DFT Compiler.
ch
Optional Task: use the QuickSTIL commands in TetraMAX to generate the SPF
file. Once the SPF file is generated, you will edit the SPF to suit the controller
ro
requirements. Since this flow is using the QuickSTIL flow to generate the SPF, you
ic
cannot use the design in Scan Compression mode. Describing the Compressor
structures with QuickSTIL is not supported.
lM
na
er
nt
rI
Fo
se
U
ed
ct
tri
es
R
Lab 10-2 Transition ATPG using PLL clocks


Lab 10
Instructions
Answers / Solutions
ng
ni
Task 1. Understand the Design Specifications
ai
Tr
In this task we will understand the design. Get to know the various clocks, port
constraint , scan chains etc which are needed to create the SPF file.
ip
ch
ORCA
ro
snps_clk_chain
ic
lM
na
er
nt
ate_pclk snps_pll_controller
rI
ate_sdrclk
I_CLOCK_GEN/sdr_occ/U4/Z
Fo
ate_sysclk
pll_reset I_CLOCK_GEN/pclk_occ/U4/Z
se
pll_bypass
U
TM_OCC I_CLOCK_GEN/sys_occ/U6/Z
ed
I_CLOCK_GEN/
I_CLOCK_GEN/sys_occ/U7/Z
sdr_clk I_PLL_PCI/CLK
ct
I_PLL_SD/CLK
pclk I_CLKMUL/CLK_1X
tri
sys_clk I_CLKMUL/CLK_2X
es
scan_en
R
TM_MODE
prst_n
test_mode


Lab 10
Reference Clocks:
 sdr_clk
 sys_clk
 pclk
ng
PLL Clocks:
ni
 I_CLOCK_GEN/I_PLL_PCI/CLK (16ns period)
ai
 I_CLOCK_GEN/I_PLL_SD/CLK (8ns period)
Tr
 I_CLOCK_GEN/I_CLKMUL/CLK_1X (10ns period)
ip
 I_CLOCK_GEN/I_CLKMUL/CLK_2X (20ns period)
ch
Signal used by the OCC block:
ro
 ate_pclk, ate_sdrclk, ate_sysclk : Slow ATE clock.
ic
 pll_reset: Reset pin to reset the OCC.
 lM
pll_bypass: Pin to put the pll in bypass mode.
na
 scan_en: Scan enable pin of the design
 TM_MODE: Test mode pin of the design
er
 TM_OCC : Pin to put the OCC in testmode

nt
rI
The Internal clocks from the OCC have the following connections with the PLL
Fo
clock and conditions in which the clock is allowed to pass to core.

se
Clock 1 :
U
Internal Clock I_CLOCK_GEN/pclk_occ/U4/Z

ed
PLL Source I_CLOCK_GEN/I_PLL_PCI/CLK (16ns period)

ct
Cycle 0 Condition I_CLOCK_GEN/snps_clk_chain_0/U_shftreg_0/ff_1/q_reg/Q

tri
set to 1
es

R
set to 1


Lab 10
Clock 2:
Internal Clock I_CLOCK_GEN/sdr_occ/U4/Z
PLL Source I_CLOCK_GEN/I_PLL_SD/CLK (8ns period)
ng
set to 1
ni
ai
set to 1
Tr
ip
Clock 3:
ch
Internal Clock I_CLOCK_GEN/sys_occ/U6/Z
ro
PLL Source I_CLOCK_GEN/I_CLKMUL/CLK_1X (10ns period)
ic
lM
set to 1
na
set to 1
er
nt
rI
Clock 4:
Fo
Internal Clock I_CLOCK_GEN/sys_occ/U7/Z
PLL Source I_CLOCK_GEN/I_CLKMUL/CLK_2X (20ns period)

se

U
set to 1
ed

set to 1
ct
tri
es
Pin Constraints: The following pins have to be constrained during ATPG.

R
 Constrain 0 : pll_bypass, scan_en, pll_reset and TM_MODE

 Constrain 1 : test_mode, prst_n and TM_OCC
Note: Only the signals needed for DRC are shown here.


Lab 10
Scan Chains :
Chain Scan Input Scan Output
1 pad[1] sd_DQ[1]
2 pad[2] sd_DQ[2]
ng
3 pad[3] sd_DQ[3]
4 pad[4] sd_DQ[4]
ni
5 pad[5] sd_DQ[5]
ai
6 pad[6] sd_DQ[6]
7 pad[7] sd_DQ[7]
Tr
8 pad[8] Sd_DQ[8]
ip
Task 2. Use existing SPF to setup ATPG for OCC
ch
1. Make sure your current working directory is lab10_occ.
ro
ic
unix% cd lab10_occ
2. lM
The existing SPF file provided is named orca_scan_occ.spf.
na
3. Inspect the SPF file in a text editor
Question 1. What section of the SPF contains information specific to the
er
OCC setup?
nt
……………………………………………………....... ............
rI
Question 2. Is it always needed to pulse the ATE clocks during capture?

Fo
…………………………………………………………
se
4. Reference clocks
Question 3. Can reference clocks have a period different from the ATE
U
clocks?
ed
…………………………………………………….......
Can the patterns be written in all the formats if the ATE and
ct
Question 4.
Reference clocks are not same?
tri
………………………………………………………….
es
Question 5. What is the only supported format if the Reference and ATE
R
clocks have a asynchronous relation?
…………………………………………………………


Lab 10
5. PLL clocks
Question 6. Is the PLL clock a free running clock?
………………………………………………………… ...........
Question 7. What is the source of a PLL clock in TetraMAX ?
ng
………………………………………………………….
ni
ai
6. Internal Clocks
Tr
Question 8. Will the DRC fail if there is not a valid path from PLL clock
to internal clock during capture?
ip
...................................................................................................
ch
Task 3. OCC ATPG Settings
ro
In the task, you will edit a script that is given. You will look for the section “LAB
ic
STEP”, add the required commands to the script, and then run TetraMAX with the
modified script. lM
1. A TetraMAX script has already been prepared as a starting point. The script
na
name is tmax_occ.tcl
er
nt
rI
unix% tmax tmax_occ.tcl

Fo
3. Set the correct fault model

se
DRC-T> set_fault –model transition

U
4. Set the launch cycle to system clock launch.

ed
DRC-T> set_delay –launch_cycle system_clock

ct
tri
5. Constrain ATPG to use the same clocks for launch and capture.
es
DRC-T> set_delay -common_launch_capture_clock

R
6. Define the number of ATE cycles


Lab 10
Question 9. What is the default number of ATE cycles for which scan
enable is low?
...................................................................................................
The default number of ATE cycles is sometimes not enough cycles for the
ng
OCC to provide the internal clocks to the core. The number of cycles required
is dependent on the OCC used. For the Synopsys OCC it’s determined by the
ni
relationship between the ATE clock period and the period of the slowest PLL
ai
clock source as well as the number of fast clocks supported by the OCC
(num_pll_cycles) according to the formula below.
Tr
ATE clock period + (5+num_pll_cycles) * PLL period (slowest)
ip
min_ate_clock_cycles = ------------------------------------------------------------------------------ + 1
ATE clock period
ch
ro
For this design, the number of ATE cycles should be set to 3.
ic
DRC-T> set_atpg -min_ateclock_cycles 3
Question 10.
lM
What happens if the number provided for
na
-min_ateclock_cycles is less than it should be?
er
...................................................................................................
nt
7. Run the DRC checks

rI
DRC-T> run_drc
Fo
Question 11. What additional DRC checks are done if the OCC is present
se
in the netlist?
U
……………………………………………………....... ............
ed
Task 4. Run ATPG

ct
In this task, you will set up ATPG for the Transition fault model and then perform
tri
ATPG to generate 30 patterns.

es
1. Run ATPG
R
TEST-T> set_atpg -patterns 30

2. Find the internal clocks used for a pattern


Lab 10
Question 12. How can we know which PLL clock has been used for the
fault detection for a given pattern?
………………………………………………………………
Add a command to report the PLL clock(s) used in pattern 5 to your script.
ng
3. In the TetraMAX session, source the tmax_write_patterns.tcl script
ni
ai
Tr
ip
ch
ro
ic
lM
na
er
nt
rI
Fo
se
U
ed
ct
tri
es
R


Lab 10
Task 5. Simulate Patterns in VCS in Parallel mode

2. Source the file vcs_pll_paralllel. After simulation, nWave will be launched in
order to view the waveforms.
ng
unix% cd pattern
ni
unix% source vcs_occ_parallel
ai
Tr
ip
ch
ro
ic
lM
na
er
nt
rI
Fo
se
U
ed
ct
4. Additional signals of interest can be added to the nWave waveform viewer.

tri
Add the output of each OCC to the waves.

es
a. I_CLOCK_GEN/pclk_occ/U4/Z
b. I_CLOCK_GEN/sdr_occ/U4/Z
R
OCC Capture clocks

c. I_CLOCK_GEN/sys_occ/U6/Z
d. I_CLOCK_GEN/sys_occ/U7 /Z
Select SignalGet Signals… to add the OCC internal clocks to the waves.


Lab 10
ng
ni
ai
Tr
ip
ch
5. Take a look at the simulated waveform to see the at-speed clocks pulse in each
pattern.
ro
ic
Note: The rest of the tasks/steps in this lab are all optional
lM
na
Task 6. Simulate Pattern in Serial Mode (Optional)
er
1. Source the file vcs_occ_serial. After simulation, nWave will be

nt

rI
unix% source vcs_occ_serial

Fo
2. Follow the same steps from the previous task again to view the waves.
se

U
Task 7. Generate SPF using QuickSTIL (Optional)

ed
ct
In this task your will run a TetraMAX script that is given. The script uses
QuickSTIL commands to define all the clocks of the OCC and generate the SPF file.
tri
The necessary pin constraints, scan paths and the clock information will be defined
es
to match the design described in Task 1.

R
1. Inspect the script. Open the tmax_occ_quick_stil.tcl script in your

favorite text editor


Lab 10
2. Note the commands used to define the OCC related clcocks. Such as:
a. Reference clocks
b. ATE clocks
c. PLL clocks
ng
d. Internal clocks
Question 13. What command is used to declare the number of pll clock
ni
cycles that is supported by the OCC and needs to be declared
ai
prior to declaring an internal clock with Quick STIL?
Tr
...................................................................................................
ip
3. Run the provided TetraMAX script to generate an SPF for OCC.
ch
unix% tmax tmax_occ_quick_stil.tcl
ro
4. The DRC file is written out at the end of the script.
ic
lM
DRC-T> write_drc_file occ_quick_stil.spf -replace
na
5. Try running DRC checks
er
DRC-T> run_drc
nt
6. The DRC checks will fail. Edits need to be made to the SPF in order to pass
rI
the the DRC checks with an SPF generated with Quick STIL commands.
Fo
7. Keep the TetraMAX session open
Task 8. Edit the SPF file to suit the OCC (Optional)

se
U
In this task you will edit the SPF file generated in the previous Task to suit the OCC
requirements.
ed
The SPF file generated from TetraMAX can be used in most cases as is. In cases
ct
where there are specific requirements for OCC, you need to edit the SPF and prior
to using it for DRC checks. The OCC implemented in this design requires a vector
tri
before the shift starts. All the ATE and the Reference clocks need to be pulsed in
es
this vector. Also, it is required that the OCC is reset before it can be used for ATPG.
To reset the OCC you will assert the OCC's reset pin in the test_setup macro
R
for one cycle with ATE and the Refclocks constrained to their off state.
1. Open the spf file generated in the previous task (occ_quick_stil.spf)

in an editor.


Lab 10
2. Edit the load_unload procedure to put a vector before the shift procedure
which pulses the ATE and Reference clocks.
3. Edit the test_setup macro in Macrodef section to assert the
pll_reset ( PLL Reset) signal for one cycle with ATE, reset, and refclocks
constrained to their off state. Make sure the signal is returned to its inactive
ng
state before the end of test_setup.
4. Save the updated SPF file.
ni
Question 14. Do you need to alter the timing in the waveform tables
ai
(WFT) when using the OCC ?
Tr
……………………………………………………....... ............
ip
5. Now try running the drc checks.
ch
DRC-T> run_drc
ro
ic
6. The DRC checks should now pass. If not then double check your edits to the
SPF.
lM
Task 9. Use the modified SPF file to pass DRC checks
na
and generate patterns (Optional)
er
A script has been prepared to use the modified SPF generated by Quick STIL.
nt
1. In your TetraMAX session, source the provided script:

rI
Fo
TEST-T> source –e tmax_occ_quick_stil_atpg.tcl
2. The script will write out patterns with the same names that were used earlier
se
in the lab
U
3. Optional step: use the same procedure describe earlier to simlate the generated
patterns in VCS
ed
You have completed the “Using On-Chip Clocks

ct
for Transition Delay” lab of the TetraMAX

tri
Workshop.
es
R


Answers / Solutions
Task 2. Use existing SPF to setup ATPG for OCC
ng
Question 1. What section of the SPF contains information specific to the
OCC setup?
ni
The ClockStructures section.
ai
Question 2. Is it always needed to pulse the ATE clocks during capture?
Tr
No, it is dependent on the OCC implementation. However,
ip
the Synopsys OCC implementation does require that the
ATE clock pulsed in the capture procedure.
ch
Question 3. Can reference clocks have a period different from the ATE
ro
clocks?
ic
Yes, reference clocks can have a period different from the
Question 4.
lM
ATE clock period. This is often the case.
Can the patterns be written in all the formats if the ATE and
Reference clocks are not same?
na
No, not all the formats are supported

er
Question 5. What is the only supported format if the Reference and ATE
nt
clocks have an asynchronous relation?

rI
STIL format only.

Fo
Question 6. Is the PLL clock a free running clock?
Yes
se
Question 7. What is the source of the PLL clock in TetraMAX?

U
For TetraMAX the source of the PLL clocks is a black box.

ed
Question 8. Will the DRC fail if there is not a valid path from PLL clock
to internal clock in the capture mode?
ct
tri
Yes, a C34 violation is reported.

es
R


Lab 10
Task 3. OCC ATPG Settings

Question 9. What is the default number of ATE cycles for which scan
enable is low?
By default, the number of ATE Clock cycles is the same as
ng
the value of PLLCycles in the SPF (if an SPF-based flow is
used) or the value set by “set_drc -num_pll_cycles
ni
<n>” (if a Quick-STIL commands flow is used). In this
ai
case, the default value was overridden by the “set_atpg
Tr
–min_ateclock_cycles 3” command.
Question 10. What happens if the number provided for
ip
-min_ateclock_cycles is less than it should be?
ch
Patterns will likely fail during simulation (mismatches). The
core logic will not see the expected clock pulses from the
ro
OCC.
ic
Question 11. What additional DRC checks are done if the OCC is present
in the netlist?
lM
Violations like C34, C39. Violations C27 – C40 are related
na
to OCC.
er
Task 4. Run ATPG

nt
rI
Question 12. How can we know which PLL clock has been used for the
fault detection?
Fo
report_patterns <pattern_#> -clocking

will give this information.
se
U
Task 5. Generate SPF using QuickSTIL (Optional)

ed
Question 13. What command is used to declare the number of PLL clock
ct
cycles that is supported by the OCC and needs to be

declared prior to declaring an internal clock with Quick
tri
STIL?
es
The set_drc –num_pll_cycles <#> command

R
needs to declare the number of PLL cycles that the OCC

supports.


Task 6. Edit the SPF file to suit the OCC (Optional)

Question 14. Do you need to alter the timing in the waveform tables
(WFT) when using the OCC?
ng
During capture the internal clocks are driven by the PLL.
ni
TetraMAX does not support defining PLL clock timing.
ai
There is no WFT which captures this timing.
Tr
The ATE and Reference clock pulse as per the
“multiclock_capture” procedure during capture. If you need
ip
to control its timing you can change the WFT which is used
ch
by this procedure.
ro
In designs which have both the Internal PLL clocks as well
ic
as External clock ports used for At-Speed test, it will be
required to change the WFTs used for At-Speed capture
lM
using the external clocks.
na
er
nt
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Fo
se
U
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ng
ni
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Tr
ip
ch
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ic
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na
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Fo
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11 Path Delay ATPG
ng
ni
ai
Tr
ip
Learning Objectives
ch
ro
In this lab, you will run TetraMAX to perform ATPG
ic
targeting the Path Delay fault model. You will first use
lM
PrimeTime to generate the paths file and exceptions and
then perform ATPG on those faults. At the end, you will
simulate the patterns in VCS to see the at-speed launch and
na
capture clocks.
er

nt
 Use PrimeTime to generate the Paths on which ATPG

will be performed.
rI
 In TetraMAX set the correct SPF and fault model

Fo
needed for Path Delay ATPG.

 List constraints needed for Path Delay ATPG.
se
 Generate and save the patterns which detect the faults on

Paths generated in PrimeTime.
U
 Simulate the pattern in VCS to see the at-speed launch

ed
and capture pulses (optional).

ct
tri
es
Lab Duration:
30 minutes
R
Path Delay ATPG Lab 11-1


Lab 11
Background
In this lab, you will do Path Delay ATPG. You will use PrimeTime to generate the
Paths which will be read by TetraMAX.
ng
You will select paths from all the clock domains in the design and then target both
the rising and falling transitions on these paths.
ni
ai
Tr
ip
ch
ro
ic
lM
na
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Fo
se
U
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Lab 11-2 Path Delay ATPG


Lab 11
Instructions
Answers / Solutions
ng
ni
Task 1. Generate Paths and Exceptions Files using
ai
PrimeTime
Tr
In this Task, you will invoke PrimTime and generate the paths on which Path Delay
ip
ATPG will be performed.
ch
1. Make sure your current working directory is lab11_path_delay.
ro
unix% cd lab11_path_delay
ic
2. lM
A PrimeTime script has already been prepared to generate the paths. The
script name is pt_delay_paths.tcl
na
This script is constrained for At-Speed ATPG and is setup to write out critical
paths, on which Path Delay ATPG will be run.
er
nt
Question 1. What command in the pt_delay_path.tcl script is used to

write the path delay critical paths?
rI
………………………………………………………….
Fo
3. Run PrimeTime
se
unix% pt_shell –f pt_delay_paths.tcl | tee pt.log

U
4. Examine the output of the PrimeTime run

ed
Question 2. How many delay path files were created by the script?
ct
………………………………………………………….
tri
Question 3. How many delay paths were written per clock domain?
es
………………………………………………………….
R
Task 2. Invoke Tetrmax, read design, and Run DRC
In this task, you will invoke TetraMAX and read the design and Run DRC.


Lab 11
unix% tmax tmax_path_delay.tcl
ng
2. Read the SDC file orca_scan_user_violation_exceptions.sdc
generated in Task 1.
ni
ai
DRC-T> read_sdc \
orca_scan_user_violation_exceptions.sdc
Tr
3. Define Constraints
ip
Question 4. What ports need to be constrained during At-Speed ATPG?
ch
………………………………………………………….
ro
ic
DRC-T> add_pi_constraints 0 <Scan Enables>
DRC-T> add_pi_constraints
lM 1 <Resets>
na
Question 5. If the primary inputs and outputs cannot transition At-Speed,
then what should be done?
er
………………………………………………………….
nt
Question 6. What are the commands in TetraMAX to prevent PIs from

rI
changing between launch/capture and mask to POs?

Fo
………………………………………………………….
4. Constraint the ATPG to use the same launch and capture clocks.
se
DRC-T> set_delay -common_lauch_capture_clocks

U
5. Run DRC checks

ed
ct
DRC-T> run_drc -patternexec ScanCompression_mode_occ_bypass

tri
Task 3. Run ATPG

es
R
In this task, you will set up the ATPG for Path Delay fault model and then run
ATPG on the Paths which were generated in Task1.
1. Define Path Delay fault model.


Lab 11
TEST-T> set_fault –model path_delay
Question 7. Does the command "set delay –launch_cycle"

have any effect when doing Path Delay ATPG?
ng
………………………………………………………..
ni
Question 8. If we want to generate patterns only with system clock
launch what shall be done?
ai
Tr
………………………………………………………..
Question 9. Is scan enable constrained? What command can you use to
ip
confirm that?
ch
………………………………………………………..
ro
2. Read the paths files generated in Task1.
ic
TEST-T> add_delay_paths ……………………
TEST-T> add_delay_paths …………………… lM
TEST-T> add_delay_paths ……………………
na
er
Question 10. Are there any warning messages?

nt
……………………………………………………………
rI
Question 11. Refer to TetraMAX Online Help and give the reason why
we get P22 violations?
Fo
……………………………………………………………
se
Question 12. Will the Paths with P22 violations be targeted for ATPG and
what will be their classification before and after ATPG?
U
……………………………………………………………
ed
3. Add faults
ct
TEST-T> add_fault -all

tri
es
Question 13. How many faults were added?

R
……………………………………………………………
Question 14. What command should be used if you want to add faults for
both rising and falling transition?
……………………………………………………………


Lab 11
4. Run ATPG
Task 4. Save the patterns and Simulate the patterns in
ng
VCS (Optional)
ni
In this task, you will save the patterns and validate them by simulating in VCS.
ai
Tr
1. In the TetraMAX session, source the tmax_write_patterns.tcl script
ip
ch
ro
3. Source the file vcs_path_parallel. After simulation, nWave will be
ic
unix% cd pattern lM
unix% source vcs_path_parallel
na
er

nt
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Fo
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Lab 11
5. Take a look at the simulated waveform to see the at-speed clocks.
Task 5. Simulating Patterns in VCS in Serial mode

(Optional)
ng
1. Source the file vcs_path_serial. After simulation, nWave will be
ni
unix% source vcs_path_serial
ai
Tr
2. Follow the same steps from the previous task again to view the waves.
ip
ch
You have completed the “Path Delay ATPG” lab
ro
ic
lM
na
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nt
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Fo
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U
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tri
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Answers / Solutions
Task 1. Generate Paths and Exceptions Files using

PrimeTime
ng
Question 1. What command in the pt_delay_path.tcl script is used
ni
to write the path delay critical paths?
ai
The write_delay_paths command
Tr
Question 2. How many delay path files were created by the script?
ip
Three files were generated. Each file targets delay paths
within a particular clock domain.
ch
Question 3. How many delay paths were written per clock domain?
ro
50 delay paths were written per clock domain.
ic
Task 2. Invoke TetraMAX Read design and Run DRC
Question 4.
lM
What ports need to be constrained during At-Speed ATPG?
na
Scan enable and the reset ports.
er
add_pi_constraints 0 scan_en
nt
add_pi_constraints 1 prst_n
rI
Question 5. If the primary inputs and outputs cannot transition At-Speed,

then what should be done?
Fo
If these ports cannot transit At-Speed, then these should not

be allowed to toggle between the launch and capture clocks.
se
Question 6. What are the commands in TetraMAX to prevent PIs from

U
changing between launch/capture and mask to POs?

ed
The command to constrain the PI changes and mask PO’s:

set_delay -nopi_change
ct
add_po_mask -all
tri
Task 3. Run ATPG

es
Question 7. Does the command "set delay –launch_cycle" have

R
any effect when doing Path Delay ATPG?
No, this command does not have any effect for Path Delay
ATPG.


Question 8. If we want to generate patterns only with system clock launch

what shall be done?
If Fast-Sequential Path Delay is enabled (the default), then

only system clock patterns will be created by Fast-
Sequential ATPG. If Full-Sequential ATPG is used for Path
ng
Delay and only system clock patterns are needed, then
constrain the scan enable to 0 in capture mode.
ni
ai
Question 9. Is scan enable constrained? What command you can use to
Tr
confirm that?
ip
Yes, you can use the command report_pi_constraints
ch
Question 10. Are there any warning messages?
ro
P8 and P22
Question 11. Refer to TetraMAX Online Help and give the reason why we
ic
get P22 violations?
lM
Delay paths that violate this rule are may have reconvergent
na
logic on the off-path values or they could be sequential false
paths (i.e. a transition along the specified path cannot be
launched, propagated, and captured).
er
Question 12. Will the Paths with P22 violation be targeted for ATPG and
nt
what will be their classification before and after ATPG?

rI
If the delay path definition is not removed, the associated

Fo
path delay faults are classified as ATPG untestable (AU)

and will not be targeted for testing.
se
Question 13. How many faults were added?

U
150
Question 14. What command should be used if you want to add faults for
ed
both rising and falling transition?

ct
set_delay -relative_edges
tri
es
R


This page was left blank intentionaly.
ng
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12 Diagnosis
ng
ni
ai
Tr
ip
ch
ro
Learning Objectives
ic
lM
During this lab, you will run diagnosis on ATE failures to
na
determine the cause of the failure.
er

nt
 Setup for Diagnosis with previously saved binary image

rI
file and pattern set

Fo
 Run diagnosis to analyze failure in functional logic

 Run diagnosis to analyze a chain test failure
se
U
ed
ct
tri
es
R
Lab Duration:
20 minutes
Diagnosis Lab 12-1


Lab 12
Background
Your goal is to determine the root cause of ATE pattern failures by running
TetraMAX diagnosis. You will use a previously saved image file and pattern set to
run the analysis.
ng
ni
Lab 12 Tasks
ai
Tr
ip
ch
ORCA
Image Read Image File
ro
File
ic
ORCA lM
Read Binary
Pattern Patterns
na
er
nt
Run Functional
Diagnosis
rI
Fo
Run Chain Test

se
Diagnosis
U
ed
ct
tri
es
R
Lab 12-2 Diagnosis


Lab 12
Instructions
Answers / Solutions
ng
ni
Task 1. Run Functional Diagnosis
ai
Ensure that the current working directory is lab12_diagnosis.
Tr
1. Invoke the TetraMAX GUI in TCL mode.
ip
ch
unix% cd lab12_diagnosis
unix% tmax &
ro
ic
2. Enter TEST mode for the ORCA design by reading a previously saved image
file.
lM
BUILD-T> read_image ../design_data/ORCA_scan_img.gz
na
er
3. View the fail data file.

nt
unix% vi ate_func_datalog.txt
rI
Question 1. What format is the fail data file, pattern-based or cycle-

Fo
based? How can you tell?
.....................................................................................................
se
Question 2. Is there expected data in the failure data file? Does

U
TetraMAX use the expected data?

ed
.......................................................................................................
ct
4. Read the binary pattern set that goes with the image file.
tri
TEST-T> set_patterns –external \

es
../design_data/orca_standard_scan_pats.bin
R
Question 3. Why do the patterns need to be read separate from the image
file?
.....................................................................................................
Diagnosis Lab 12-3


Lab 12
Question 4. How many patterns were read?
.......................................................................................................
5. Run diagnosis.
ng
TEST-T> run_diagnosis ate_func_datalog.txt -verbose
ni
ai
Question 5. Was TetraMAX able to find the defect? What fault location
does TetraMAX report as the cause of failures?
Tr
....................................................................................................
ip
ch
....................................................................................................
ro
Question 6. What is the match score?
ic
....................................................................................................
lM
Task 2. Chain Test Diagnosis
na
er
TetraMAX uses a separate diagnosis engine to diagnose chain test faiures.

nt
1. Look at the chain_test.txt fail data file.

rI
unix% vi ate_chain_datalog.txt
Fo
Question 7. By default, TetraMAX will automatically choose the proper

se
diagnosis engine to use during run_diagnosis. How does

TetraMAX know to use the chain_failure engine on the fail
U
data file?
ed
....................................................................................................
ct
2. Run chain test diagnosis.

tri
TEST-T> run_diagnosis ate_chain_datalog.txt

es
Question 8. Was the chain test diagnosis successful?

R
....................................................................................................
Lab 12-4 Diagnosis


Lab 12
3. Dealing with large fail data files

Chain test defects can produce very long fail data files. The ATE may not be
able to capture all the failures. TetraMAX assumes that is has fail data for all
of the patterns read in. If this is not the case, TetraMAX needs to know that
some failure data may be missing.
Question 9. What command and option can be used to tell TetraMAX that
ng
it doesn’t have a complete set of fail data?
ni
....................................................................................................
ai
4. Adjust the diagnosis settings.
Tr
Enter the command determined above:
ip
TEST-T> set_diagnosis ...
ch
Question 10. Was the chain test diagnosis successful this time?
ro
ic
....................................................................................................
Question 11. lM
What fault location was identified by diagnosis?
na
....................................................................................................
er
nt
You have completed the “Diagnosis” lab of the

rI
TetraMAX Workshop.
Fo
se
U
ed
ct
tri
es
R
Diagnosis Lab 12-5


Answers / Solutions
Task 1. Run Functional Diagnosis

Question 1. What format is the fail data file, pattern-based or cycle-
based? How can you tell?
ng
It’s pattern-based. The cycle-based format has “C” in the
ni
first column.
ai
Question 2. Is there expected data in the failure data file? Does
Tr
TetraMAX use the expected data?
Yes, there is. If expected data exists, by default TetraMAX
ip
will check the pattern data to ensure that there were no
ch
pattern translation issues.
ro
Question 3. Why do the patterns need to be read separate from the image
file?
ic
The binary image file does not contain the patterns.
Question 4.
lM
How many patterns were read?
na
237.
er
Question 5. Was TetraMAX able to find the defect? What fault location
does TetraMAX report as the cause of failures?
nt
Yes, TetraMAX was able to find the defect.

rI
sa0 DS I_ORCA_TOP/I_BLENDER/U8511/B1 (oai21d1)

Fo
Question 6. What was the match score?

se
100%.
U
Task 2. Chain Test Diagnosis

ed
Question 7. By default, TetraMAX will automatically choose the proper

ct
diagnosis engine to use during run_diagnosis. How does

TetraMAX know to use the chain_failure engine on the fail
tri
data file?
es
If the fail data file includes failures on pattern 0,

R
TetraMAX assume that is the chain test pattern and will

automatically use the chain_failure algorithm (unless
set_diagnosis –noauto is specified). You can
explicitly run chain_failure diagnosis with
run_diagnosis –chain_failure.
Lab 12-6 Diagnosis


Question 8. Was the chain test diagnosis successful?
Yes, but only after extra analysis. Note the M633 message.
ng
Check expected data completed: 3440 out of 3440 failures were checked
Warning: Both values (0 and 1) were unloaded from the last scan cell in
ni
chain=5. (M633)
ai
ate_chain_datalog.txt scan chain diagnosis results: #failing_patterns=20
Tr
------------------------------------------------------------------------
ip
defect type=stuck-at-0
match=100.00% chain=5 position=257
ch
master=I_ORCA_TOP/I_PCI_WRITE_FIFO/empty_int_reg (sdcrn1)
CPU_time=0.05 #sim_patterns=10 #sim_failures=1757
ro
Warning: 217 passing patterns were ignored during chain diagnosis
ic
(pat1=20). (M633)
Question 9.
lM
------------------------------------------------------------------------
What command and option can be used to tell TetraMAX

na
that it doesn’t have a complete set of fail data?
There are several ways to do this:

er
set_diagnosis –incomplete_failures
nt
set_diagnosis –failure_memory_limit <#fails>

rI
run_diagnosis –truncate <pat#>

Fo
The first option is easiest to use, since it doesn’t require an

argument. TetraMAX will ignore the last failing pattern and
all the patterns that follow it for the purposes of the analysis.
se
Question 10. Was the chain test diagnosis successful this time?
U
ed
set_diagnosis –incomplete_failures
ct
Yes.
tri
es
R
Diagnosis Lab 12-7


Question 11. What fault location was identified by diagnosis?

Check expected data completed: 3440 out of 3440 failures were checked
Warning: 84 failure(s) were ignored in the last failing pattern. (M267)
ng
ate_chain_datalog.txt scan chain diagnosis results: #failing_patterns=19
------------------------------------------------------------------------
ni
defect type=stuck-at-0
ai
match=100.00% chain=5 position=257
Tr
master=I_ORCA_TOP/I_PCI_WRITE_FIFO/empty_int_reg (sdcrn1)
CPU_time=0.03 #sim_patterns=10 #sim_failures=1757
ip
------------------------------------------------------------------------
ch
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Lab 12-8 Diagnosis


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ng

CUSTOMER EDUCATION SERVICES

Synopsys Customer Education Services

Mountain View, California 94043

Workshop Registration: http://training.synopsys.com

For Internal Microchip Training Purposes Only

Destination Control Statement

690 E. Middlefield Road

Document Order Number: 30-I-021-SLG-017

TetraMAX Lab Guide

Synopsys Customer Education Services

For Internal Microchip Training Purposes Only

After performing this lab, you should be able to:

 Debug problems with the Core cell library

 Define Black Box model for missing modules

Handling Designs and Libraries Lab 2-1

For Internal Microchip Training Purposes Only

The UNIX directory for this entire lab is lab2_build.

Answers and suggestions are located at the end of this lab.

You do not need to type the entire command or option names!

BUILD-T> read_net orca_final.v

Lab 2-2 Handling Designs and Libraries

For Internal Microchip Training Purposes Only

PCI Bus PCI_CORE

133 100 100

Handling Designs and Libraries Lab 2-3

For Internal Microchip Training Purposes Only

Question 1. Were any errors reported during the read?

2. Confirm the error status with the following command.

BUILD-T> report_modules -errors

3. Read in the library models for the core cells, ../libs/core.v.

BUILD-T> read_netlist ../libs/core.v

Question 2. What violations were reported? Which is most severe?

4. Determine where the violations occurred using the following command:

Lab 2-4 Handling Designs and Libraries

For Internal Microchip Training Purposes Only

Question 4. Is this construct a behavioral or structural construct in

Task 3. Building the ORCA Design

1. Read the ORCA design, orca_final.v.

BUILD-T> read_netlist ../design_data/orca_final.v

2. Build the ATPG model for the ORCA design.

Question 8. Is TetraMAX in DRC mode? If not, why?

Question 9. Can you analyze this violation graphically? Why?

Handling Designs and Libraries Lab 2-5

For Internal Microchip Training Purposes Only

3. Bring up the man page for this violation.

6. Try building the ORCA design again.

Question 13. What netlist related violations are now reported?

Lab 2-6 Handling Designs and Libraries

For Internal Microchip Training Purposes Only

7. Generate a summary primitives report and answer the following questions.

DRC-T> report_summaries primitives

Question 14. What primitive is used the most?

TEST-T> run_atpg –auto

Handling Designs and Libraries Lab 2-7

For Internal Microchip Training Purposes Only

Task 4. Reading RAM Models

1. Return to BUILD mode with the following command.